Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STCLRLB

Test 1: uops

Code:

  stclrlb w0, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 70 nops): 3.000

Issues: 3.005

Integer unit issues: 1.006

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)0e0f1e1f22243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)cfd0d1d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
7300534052254191600129301053373387200219833007100220001000200011024169700493089733666340263103000100020002000400034013267511710011000100002000221002100136200720021496010632279773580751241433562444493837329951005188241690817717200010003412734052340163422334030
73004340082551521001003000531833928002192330041005200010002000110161705074930939337383397731030001000200020004000340472672117100110001000020001310061000042006400215141106071801236398352414335674440124044329971004190511672617465200010003401334114340323407634025
7300433987254141100100200053683385801220053005100220001000200011005169452493094433675340563103000100020002000400033929267411710011000100002000021002100006200640201507010797280353682740240863576444474139328921004189631677917624200010003411834102342023406334055
7300434061255219001006000534133895102192530051005200010002000110211697844930960336753403331030001000200020004000339192655117100110001000020002210041000072004602014942106131797935878372414536214440143935330051008188001675817628200010003396934168340953407234012
7300433969254131100100800053203395410219773007100520001000200011141169060493105133656340543103000100020002000400034045266311710011000100002000321006100005200360221503410697279973561742241793607444453536328961008191081681117713200010003400134025340573411734019
73004340012541113001008010533833845002202430071007200010002002109361704934930963336993397031030001000200020004000338412652117100110001000020003310061000062006602314908106642796035275452416936254436114343329501005189131680417563200010003403733985340143406034088
73004340842551513001009010532233895002197730051007200010002000112101711504930941336383399531030001000200020004000339672632117100110001000020002310021000072006700214970106842797335426342409935904441103743330391007188541684117705200010003399034032340583412034029
7300434039255131200100900053663395500218463005100620001000200011003170684493096633670340933103000100020002000400033964266511710011000100002000021041100004200650221498310652179713526741240903584444153837329941004190821658917698200010003398134025341713410533960
7300433961255141300100800053463394010219113006100720001000200011014169008493103633634340923103000100020002000400033973263311710011000100002000021006100004200340221496410536679413516837242043615443793933329881004187641679117759200010003412534036341423406734108
730043400825514910100800052513385200219793007100620001000200010954169026493095933720340903103000100020002000400034037265911710011000100012000211000100006200670321504310893179933497744240753558444373846329911007186811683317693200010003407533925340603399033982

Test 2: throughput

Code:

  stclrlb w0, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0f18191e1f202223293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
4020670073524000000507323410016527005423112345792425403342036020000201002000020450093323042082496698470033700696450736502740100202002000030200400007006964112020110099100100001010010000110020044015149198711005510001214032322007612414012901310116116985620291101020000201007007070070700707007070070
40204700695250000005048126100150700543921424577202540307203132000020100200002045356332126701004966989700147006964507365027401002020020000302004000070050631120201100991001000010100100000100200690149631987110062100021154058200561813416401310116116985620271101020000201007007070123700707007070070
4020470069525000000506122810012070054341142558609254035520242200002010020000204480433200770204496698970033700696450736502740100202002000030200400007006957112020110099100100001010010000010020047011154198711006210012214426512005412023311101310116116985620361101020000201007007070070700777007070070
402047006952400000050591271007070054181162258483254047020312200002010020000204508433207590208496698970028700696450736502740100202002000030200400007006963112020110099100100001010010000010020039011345198661004910003314114282007211923011201310116116985620315101020000201007006572069700707007070070
4020470069525000000504512810012070054251102858118254045520327200002010020000204406833201770101496698970028700696450736502640100202002000030200400007006768112020110099100100001010010000010020057011354198711007610011216230382004712353714701310116116985620277101020000201007007070070700707007070070
40204700695240000005039142100807005426111245783325403622033320000201002000020452563321486010849669897003370069645073650274010020200200003020040000700696311202011009910010000101001000001002002101124519871100511000931403019200301172271300131011611698562032101020000201007007070070700707007070070
4020470069525000000503232110011407005418114215817325403612049920000201002000020451763321278018149669897003370069645033650274010020200200003020040000700641251120201100991001000010100100000100200280574219866100491001351363821200521191277311310116116985620272101020000201007007070071700517007070070
4020470069525100000503412810019070054403122458497254033320351200002010020000204504633203320107496698970025700696450736502640100202002000030200400007006963112020110099100100001010010000010020038011243198661006310067601464028200551172347301310116116985620457101020000201007007170081700677007070070
4020470050525000000505022010070700543211020581862540327203062000020100200002044636332134607349669897003370069645073650274010020200200003020040000700696311202011009910010000101001000001002004002724019871100521001121640442003611713111001310117116985620368101020000201007206570051700707007070070
402047006952500000050560630001307005433113225824025403332049620000201002000020452973321459012749669897003370069644883650084010020200200003020040000700696311202011009910010000101001000001002002609136198711006510005100043200451182199001310116116985620257101020000201007008170070700707006570070

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0069

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2022233a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)67696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb6bbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
400267006952500000105051131101607003528316105807625406372024520000200102000020448483320838113496698970033700696452936504340010200202000030020400007006361112002110901010000100101000001020047092441987210037100012143342420047017034108012704167669856202216620000200107007070070700707005170064
400247006352500000005047127101107004819312115787225403512026220000200102000020449483320753254496698370029700696452336504340010200202000030248400007006961112002110901010000100101000001020152090331986610041100011113010172003301513872012705167769837203026920000200107007070070700707006470051
400247005052500000005035121101107005429310958366254028020237200002001020000204411633213011094966983700277006364529365492400102002020000300204000070069571120021109010100001001010000010200270106351987210041100015126242720050018129162012706165569837202706920000200107007070070700517007070070
4002470050525000000050431181014070054243141358754254052020377200002001020000204390233208111224966983700297006964529365049400102002020000300204000070050611120021109010100001001010000010200260105471987210058100012124342120047024141177012705165769856202640020000200107007070070700707006470070
40024700695240000000504611910807004817314105788425402322018620000200102000020449013320560544966989700237006364523365049400102002020000300204000070564571120021109010100001001010000110200300123431986810039100011128282220045021132142012705164569856202846620000200107007070563705677006470070
400247006952400000005041129101312700482921112585852540297201422000020010200002044520332045110749669897002370063645293650494001020020200003002040000700506111200211090101000010010100000102003701653319872100401000121373611272004811613790012705156669850205436020000200107007070064700707006470070
4002470566525000010050570381017070054232121258908254012320321200002001020000204367833218991544966970700107006364510365509400102002020000300204000070050611120021109010100001001010000010200410191481987210040100082137424320058031152181012706165669856202156620000200107007070070700647005170064
400247006952500000015061146101907003530315115879425402102036820000200102000020442203319746148496698370033700636452336504340010201722000030020400007006961112002110901010000100101000001020023012942198721004710001012426202003601913491012705164669856201659620000200107007070070700647006170064
400247006352500000005043024102070054243121258076254036420460200002001020000204430733210171054966989700297006364529365049400102002020000300204030470063611120021109010100001001010000110200370108251986610061100011145282220040017129178012705165469856206009620000200107007070061700707006470070
4002470063525000010050421291016070054283131057991254046020361200002001020000204431133211771574966983700337006964523365043400102002020000300204000070063611120021109010100001001010000010200240106421986610045100060125342820029013136145012705168669856204506620000200107005170064700727007270070

Test 3: throughput

Code:

  stclrlb w0, [x6]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 22.0136

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
302052201701649110101002692514001220097011122025752550801275632304610100200008467992105252110475492170900220158220160215477621634430100188516801020320005202064000922015389711102011009910010000100100000100200232333027378100141217290377211732114230242111716109940520022105412827377131302000010100220098220151220135220130220149
302042201361649100100002753815101220155311020222225505442775122594101002000088387241052458505074921704402201562201402154126216351301001940173310200200002020040000220139936111020110099100100001001000001002002221300268271001403170783668916868151829212111722105152252221942311328168131302000010100220135220131220129220133220107
3020422015316491100100027157150022201356111420161625505732831322265101002000088598331052679516074921709002201542201172154096216345301001589149710200200002020040000220154868111020110099100100001001000001002000021310272081001400172973704817363120021011171611299016002194551172755601402000010100220141220124220126220137220107
30204220136164900000000280631100220125501220180525503012803922284101002000086427381052498015434921707502201172201562154146216354301001477148610203200052020640009220143912111020110099100100001001000001002000003220278761000100177113747017277124310011172910423016002194221452822713002000010100220155220127220147220191220139
3020422014216491101000027232151012201535772023482550912280412282410100200008755811105232110551492170410220142220138215459621634430100161816361020320005202064000922016287511102011009910010000100100000100200232132372783910017001770038140175581417292311117161083101600219408812780601302000010100220183220132220147220121220159
302042201541649110100002788715101220130301320180625504622818622369101002000086644451052530314284921711202201412201312154916216332301001331183610203200052020640009220146915111020110099100100001001000001002002120330275401001600177653764817805152332230111716115910160021944515527676131302000010100220159220102220137220143220145
302042201661648110101002766015102220139610142019762550588282932245610100200008814709105252881495492170620220152220152215456621635030100174621981020320005202064000922015494111102011009910010000100100000100200242434027597100160017609374771700515180242111716111930160021946613428074131302000010100220137220120220194220103220143
302042201661649100100002756215000220129701420245825509582762823018101002000084656921052386315134921708402201452201482155096216343301001850194710203200052020640009220133913111020110099100100001001000001002002222320274041001600173123653416999152229202111716109250160021938921827672131302000010100220143220161220145220136220130
302042201401649110100002642814002220153689202501255060627650231221010020000842353610528195154649217066022013022012621548262163423010018442060102032000520206400092201328911110201100991001000010010000010020023233236275041004901175793716717375151932190111716104340160021941119127409131302000010100220147220135220116220160220159
302042201301649110100002756014000220125712020183334505642750222882101002000087351031052454815264921709002201342201582154286216363301002074197210203200052020640009220167941111020110099100100001001000011002002424334326394100160216469367791643415210231111716103090160021940524327729131302000010100220152220148220130220124220116

1000 unrolls and 10 iterations

Result (median cycles for code): 22.0267

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)797bmap int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbbbcl1d cache miss ld nonspec (bf)l1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd1d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
300252201821649112100317831500022022011010201245255295732881200671001020000106762681052372711370492171932202412202492154193216467300101129810020200002002040000220275721111002110956741101000010100001102045323130314821000110215264156621504129310000640152592162221937043288310102000010010220292220230220238220262220278
30024220277165000000431660110022024211414201218345287032792200541001020000106308201052398301329492171682202822202652153863216492300101611671007820000200204000022026673311100211094814210100001010000110200252528543155810018112154441527215101530026200693153122152221939903278213132000010010220222220279220299220261220287
30024220268165010000031534151012202509002015242552902327652008910010200001062911710524948014074921727622022922033621547632164923001013312910020200002002040000220241715111002110955930101000010100000102002828003156810015003077841571215991531322530064015218215222193321328971302000010010220258220227220254220251220230
3002422027616501010003147116102220241816172016322552910328842009310010200001057302410525144114134921719822030022027021537832165103001012711410020200002002040000220314729111002110963096101000010100000102002726375231637100170021588415922155015302926100640154162152221935513285913132000010010220277220231220229220236220211
3002422022016501110003150516102220243418182010042552868327852007310010200001061900810524360114204921715222029022025121533032165243001014815910020200002002040000220290698111002110948608101000010100000102002726385431593100170121574415422154916313726000640154032152221937203286813132000010010220255220263220216220269220235
300242202421650100000316761500222023701802015422552917328132007510059200001061323910524851013554921717822030422030621540232164603001013012310020200002002040000220268673111002110951769101000010100000102002726295131562100170021618414612159615292825000640152712162221944423287113132000010010220264220281220268220255220257
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