Firestorm: LDRSH (register, 64-bit) measurements

Code:

  ldrsh x0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	1	0	45	1	0	1	379	3	12	12	16	25	1000	1000	1000	15274	0	394	398	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	6	1	39	43	73	3	16	3	3	400	13	13	5	1000	395	395	399	395	399
1004	394	3	0	0	0	44	1	0	1	383	3	12	1	16	25	1000	1000	1000	17600	1	398	398	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1038	6	1	39	43	73	3	16	3	3	395	10	10	4	1000	395	399	395	399	395
1004	398	3	0	0	0	45	1	0	1	379	2	12	12	19	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1038	6	1	38	44	73	3	16	3	3	395	10	14	4	1000	395	395	395	399	399
1004	394	2	0	0	0	45	0	0	1	383	2	12	12	19	25	1000	1000	1000	15037	1	394	394	221	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	3	16	3	3	393	14	10	4	1000	395	395	501	395	399
1004	398	3	0	0	0	45	0	0	1	383	2	1	12	19	25	1000	1000	1000	14989	0	394	398	216	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1	1000	43	1038	0	39	1039	6	1	38	43	73	3	16	3	3	391	14	10	4	1000	395	395	395	395	395
1004	398	3	0	0	0	45	0	0	1	379	2	12	1	16	25	1000	1000	1000	15037	0	398	398	221	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	38	44	73	3	16	3	3	391	10	10	4	1000	399	395	395	395	395
1004	398	3	0	0	0	44	1	0	1	379	2	1	1	16	25	1000	1000	1000	15267	0	394	394	216	3	252	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	42	1038	1	39	1039	6	1	38	44	73	3	16	3	3	391	14	10	4	1000	395	399	395	395	395
1004	398	3	0	0	0	45	0	0	1	379	3	1	18	16	25	1000	1000	1000	15208	0	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1	1000	39	1038	0	38	1038	6	1	39	43	73	3	16	3	3	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15267	0	394	394	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1	1000	43	1038	0	39	1038	6	1	39	44	73	3	16	3	3	395	14	14	4	1000	399	399	399	395	399
1004	398	2	0	0	0	44	0	0	1	379	2	12	12	19	25	1000	1000	1000	15267	0	394	395	221	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	38	44	73	3	16	3	3	395	14	14	4	1000	399	399	399	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	524	1	1	0	0	0	1	0	1	0	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616005	3341470	49	66967	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70036	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	2	1	10004	0	0	1	1	10000	1	1	0	1	2	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70057	70054	70054	70054
40204	70056	524	1	0	1	0	0	0	0	2	1	0	0	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	49	66973	70041	70056	64652	3	64944	40100	30200	10000	60200	20000	70190	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	0	1	10000	1	1	0	1	1	0	2610	1	71	1	1	70225	30006	0	6	6	10000	30100	70054	70042	70055	70054	70057
40204	70054	525	1	0	0	1	0	0	0	2	0	0	0	70026	69784	59712	25	40108	30106	10002	30100	10000	616078	3341769	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	4	1	10002	0	0	1	1	10000	1	1	1	1	0	0	2610	1	71	1	1	69810	30003	6	0	9	10000	30100	70048	70048	70036	70036	70036
40204	70047	525	0	0	0	0	0	0	0	6	0	0	0	70038	69784	59702	25	40108	30106	10002	30100	10000	616032	3342350	49	66961	70053	70053	64649	3	64944	40100	30398	10000	60200	20000	70048	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69822	30003	0	6	0	10000	30100	70048	70048	70048	70048	70036
40204	70047	524	0	0	0	0	0	0	0	0	1	0	1	70026	69702	59712	25	40104	30106	10002	30100	10000	616078	3342350	49	66973	70041	70053	64649	3	64944	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	0	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	0	10000	30100	70054	70042	70054	70057	70054
40204	70053	525	1	0	1	1	0	0	0	1	1	0	0	70041	69784	59712	25	40108	30106	10001	30100	10000	616032	3341769	49	66973	70041	70053	64649	3	64956	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	0	0	1	1	10000	0	1	0	1	1	0	2610	1	71	1	1	69819	30006	0	0	6	10000	30100	70054	70042	70054	70054	70095
40204	70047	525	0	0	0	0	0	0	0	1	1	0	0	70032	69764	59695	25	40104	30103	10001	30100	10000	616015	3341470	49	66970	70035	70047	64643	3	64938	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10003	0	0	1	1	10000	1	1	1	1	1	0	2610	1	71	1	1	69804	30006	6	6	6	10000	30100	70054	70042	70054	70042	70042
40204	70053	525	1	1	0	0	0	0	0	1	1	0	1	70038	69702	59712	25	40104	30103	10002	30100	10000	616032	3341769	49	66961	70041	70041	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	1	0	1	10000	1	0	1	0	0	0	2610	1	71	1	1	69810	30003	6	0	6	10000	30100	70048	70048	70051	70036	70048
40204	70047	525	0	0	0	0	0	0	0	0	1	0	0	70038	69784	59701	25	40108	30106	10001	30100	10000	616032	3342350	49	66976	70041	70053	64649	3	64959	40100	30200	10000	60200	20000	70061	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	1	0	10002	0	0	1	1	10000	1	0	1	0	0	0	2610	1	71	1	2	69816	30006	6	0	6	10000	30100	70054	70054	70054	70054	70054
40204	70041	525	1	1	1	1	0	0	0	0	1	0	0	70038	69784	59712	25	40104	30106	10001	30100	10000	616078	3342350	49	66961	70053	70041	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10003	0	1	0	1	10000	1	1	1	1	2	0	2610	1	71	1	1	69816	30006	6	0	6	10000	30100	70042	70042	70054	70054	70054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	1	0	0	0	1	1	0	1	0	70063	69743	59706	25	40010	30013	10001	30010	10000	616952	3342062	1	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	0	10000	0	3	10000	1	0	0	2520	2	71	0	1	1	69810	30003	0	6	0	10000	30010	70051	70036	70048	70048	70048
40024	70047	525	1	0	0	0	0	0	1	1	0	70035	69743	59706	25	40010	30010	10001	30010	10000	616952	3342062	1	49	66955	70035	70035	64665	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	2520	1	71	0	1	2	69813	30000	0	6	9	10000	30010	70036	70036	70036	70048	70036
40024	70035	524	0	1	0	1	0	0	1	1	0	70073	69728	59706	25	40014	30010	10001	30010	10000	617068	3342062	1	49	66955	70091	70118	64655	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	10000	0	1	2	2520	1	71	0	1	2	69798	30000	0	6	0	10000	30010	70051	70051	70036	70051	70036
40024	70047	524	0	0	0	0	1	1	1	1	0	70035	69728	59695	25	40014	30013	10000	30010	10000	616952	3342062	1	49	66967	70035	70047	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	2520	1	71	0	1	1	69810	30003	9	6	6	10000	30010	70048	70036	70036	70036	70048
40024	70035	525	0	0	0	0	1	1	1	0	0	70020	69743	59706	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	70035	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	1	71	0	1	2	69813	30003	6	6	6	10000	30010	70091	70069	70048	70048	70048
40024	70047	524	0	0	0	0	0	0	6	1	0	70032	69728	59706	25	40010	30013	10001	30010	10000	616952	3341470	1	49	66955	70058	70037	64665	3	64960	40010	30020	10000	60020	20000	70050	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	1	71	0	2	1	69810	30003	6	6	0	10000	30010	70048	70048	70051	70048	70048
40024	70047	524	0	0	0	0	1	0	1	1	0	70035	69743	59709	25	40014	30013	10000	30010	10000	616982	3342062	1	49	66967	70047	70035	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	1	71	0	2	1	69810	30003	6	0	6	10000	30010	70087	70066	70048	70051	70036
40024	70047	525	0	0	1	0	0	0	7	0	0	70091	69743	59727	25	40014	30010	10001	30010	10000	616952	3345374	1	49	66955	70047	70035	64672	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	2520	1	71	0	2	1	69810	30003	6	6	6	10000	30010	70057	70048	70048	70048	70048
40024	70035	525	0	0	0	0	0	0	1	0	0	70035	69760	59706	25	40014	30013	10000	30010	10000	617068	3341470	1	49	66955	70035	70050	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	10000	1	1	0	2520	2	71	0	1	1	69810	30003	6	6	9	10000	30010	70051	70051	70048	70048	70051
40024	70047	525	0	0	0	0	0	0	1	1	0	70035	69728	59706	25	40014	30013	10000	30010	10000	616982	3342062	1	49	66967	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	0	0	2520	1	71	0	1	1	69813	30003	6	6	6	10000	30010	70048	70036	70048	70048	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	0	1	0	0	0	2	1	0	0	0	0	70035	69735	59709	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66967	70047	70050	64643	0	3	64938	40100	30200	10000	60200	20000	70076	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10016	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69813	30003	9	6	9	10000	30100	70048	70051	70048	70051	70051
40204	70050	524	0	0	0	0	0	0	0	1	0	0	0	0	70020	69764	59706	25	40104	30103	10001	30100	10000	616015	3342206	0	49	66970	70035	70050	64646	0	3	64950	40100	30200	10000	60200	20000	70070	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	3	1	10001	1	1	1	10001	1	1	1	1	0	2610	1	71	1	1	69798	30000	6	9	9	10000	30100	70051	70036	70051	70036	70052
40204	70050	525	0	0	0	0	1	0	0	1	0	0	0	0	70032	69781	59695	25	40104	30103	10002	30254	10000	616005	3342206	1	49	66955	70047	70035	64646	0	3	64958	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	2	1	10002	0	0	1	10000	1	1	1	1	0	2610	1	71	1	1	69798	30003	6	0	6	10000	30100	70048	70048	70051	70036	70036
40204	70035	525	0	0	0	0	0	0	0	0	0	0	0	0	70041	69784	59712	25	40104	30106	10002	30100	10000	616032	3342350	0	49	66961	70041	70056	64649	0	3	64944	40100	30200	10000	60200	20000	70061	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10001	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69798	30003	0	6	9	10000	30100	70036	70051	70048	70051	70051
40204	70055	525	0	0	0	0	0	0	0	1	0	1	0	0	70026	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	0	49	66976	70053	70056	64637	0	3	64956	40100	30200	10000	60200	20000	70093	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69813	30003	0	0	0	10000	30100	70036	70048	70048	70036	70036
40204	70050	524	0	0	0	0	0	0	0	1	0	1	0	0	70041	69969	59710	25	40108	30106	10002	30100	10000	616032	3341769	0	49	66976	70056	70056	64652	0	3	64944	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70051	70048	70051	70036	70051
40204	70050	524	0	0	0	0	0	0	0	0	0	0	0	0	70026	69787	59712	25	40108	30106	10001	30100	10000	616078	3342350	0	49	66973	70041	70053	64652	0	3	64956	40100	30200	10000	60200	20000	70078	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69819	30006	0	6	9	10000	30100	70054	70054	70042	70054	70042
40204	70053	525	1	1	0	1	0	0	0	2	0	0	0	0	70032	69735	59706	25	40173	30100	10001	30100	10000	616015	3342062	0	49	66970	70047	70050	64643	0	3	64953	40100	30200	10000	60200	20000	70117	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69804	30003	6	6	6	10000	30100	70057	70042	70054	70042	70054
40204	70041	525	1	0	0	0	0	0	0	2	0	0	0	0	70032	69764	59709	25	40104	30103	10000	30100	10000	616005	3342206	0	49	67340	70047	70050	64643	0	3	64938	40100	30200	10000	60200	20000	70087	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10014	0	0	0	10000	1	0	0	0	0	2610	1	71	1	1	69810	30003	6	6	9	10000	30100	70051	70051	70036	70036	70036
40204	70035	525	0	0	0	0	0	0	0	0	0	1	0	1	70026	69784	59712	25	40104	30106	10002	30100	10000	616032	3341769	0	49	66976	70056	70041	64637	0	3	64959	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	10000	0	0	1	0	0	2610	1	71	1	1	69819	30003	0	6	6	10000	30100	70054	70140	70057	70059	70057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	1	0	2	1	0	0	70131	69728	59695	25	40010	30010	10002	30163	10000	616970	3342062	0	49	66955	0	70035	70050	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10002	2	0	10002	0	1	1	10000	1	1	1	1	0	0	2520	9	71	8	6	69816	30003	6	6	6	10000	30010	70048	70036	70040	70036	70048
40024	70035	524	0	0	0	1	1	0	0	70129	69743	59709	25	40010	30010	10001	30010	10000	616982	3342206	1	49	66955	0	70035	70047	64668	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10001	1	1	4	10000	1	1	1	1	2	0	2520	7	71	9	8	69819	30003	0	6	9	10000	30010	70042	70057	70042	70042	70057
40024	70056	525	1	0	0	1	0	0	0	70120	69780	59717	25	40018	30022	10001	30010	10000	617009	3342494	0	49	66973	0	70056	70041	64671	3	64978	40010	30020	10000	60408	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	0	10003	1	0	0	10000	1	0	1	0	0	0	2520	6	71	10	10	69810	30003	0	6	6	10000	30010	70051	70048	70051	70036	70051
40024	70050	524	0	1	1	6	0	0	0	70105	69760	59709	25	40010	30013	10001	30010	10000	617068	3342206	0	49	66967	0	70035	70047	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	1	1	10000	1	1	1	1	0	0	2520	8	71	7	10	69819	30006	6	0	6	10000	30010	70054	70054	70057	70057	70062
40024	70056	525	1	0	0	1	1	0	0	70107	69760	59706	25	40010	30013	10001	30010	10000	616952	3341470	0	49	66973	0	70041	70041	64659	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10003	1	0	1	10000	0	0	1	0	0	0	2520	12	71	8	6	69813	30000	6	0	6	10000	30010	70036	70036	70036	70048	70048
40024	70047	525	1	0	0	1	1	0	0	70045	69763	59711	25	40014	30013	10001	30010	10000	617068	3342062	1	49	66967	0	70050	70050	64668	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10003	2	1	10001	0	0	0	10000	1	0	1	0	0	0	2520	6	71	6	8	69798	30003	0	6	9	10000	30010	70051	70051	70051	70048	70036
40024	70035	524	0	0	0	0	0	0	1	70108	69760	59709	25	40014	30013	10001	30010	10000	616982	3342206	1	49	66967	0	70050	70035	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10000	0	0	0	10000	0	1	0	0	0	0	2520	6	71	6	8	69813	30003	9	6	6	10000	30010	70051	70051	70051	70036	70055
40024	70050	525	0	0	0	0	0	0	0	70117	69760	59709	25	40014	30013	10001	30010	10058	617068	3342206	0	49	66967	0	70047	70047	64653	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	1	0	0	10000	1	0	0	0	0	0	2520	7	71	6	7	69813	30000	0	0	9	10000	30010	70036	70036	70051	70048	70036
40024	70035	525	0	0	0	1	0	0	0	70100	69743	59695	25	40010	30010	10001	30010	10000	616982	3342206	1	49	66967	0	70050	70050	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	8	71	9	7	69813	30003	9	6	6	10000	30010	70036	70036	70036	70048	70051
40024	70050	525	0	0	0	1	0	0	0	70059	69743	59709	25	40014	30013	10001	30010	10000	616952	3341470	1	49	66967	0	70050	70050	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2520	5	71	6	8	69813	30003	9	6	6	10000	30010	70036	70051	70051	70051	70048

Test 4: throughput

Count: 8

Code:

  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]
  ldrsh x0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	0	0	0	0	44	1	1	26712	0	12	12	0	25	80100	100	80000	100	80015	500	1167303	1	49	23651	26727	26707	16635	6	16679	80116	200	80024	200	160048	26746	77	1	1	80201	100	99	100	80000	100	80000	0	100	80130	0	43	80038	0	0	80038	6	1	39	44	1	1	1	5118	0	16	1	2	26704	10	10	4	80000	100	26728	26728	26728	26732	26728
80204	26727	200	0	0	0	0	0	0	44	0	1	26692	2	1	1	19	25	80100	100	80000	100	80014	500	1166596	0	49	23651	26707	26731	16635	6	16683	80114	200	80024	200	160048	26732	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	0	80000	0	0	0	43	1	1	1	5118	1	16	2	1	26728	14	10	7	80000	100	26732	26708	26732	26708	26732
80204	26707	200	0	0	0	0	0	0	44	0	0	26692	2	12	0	16	25	80100	100	80000	100	80015	500	1167198	0	49	23651	26707	26707	16635	6	16659	80115	200	80024	200	160048	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80038	0	38	80039	0	1	39	44	1	1	1	5118	2	16	1	2	26728	0	0	7	80000	100	26812	26708	26728	26728	26728
80204	26727	200	0	0	0	0	0	0	44	1	0	26692	2	1	12	19	25	80100	100	80000	100	80014	500	1166596	0	49	23627	26707	26731	16655	6	16701	80115	200	80024	200	160048	26730	56	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	43	80039	0	38	80000	6	0	0	0	1	1	1	5118	1	16	2	1	26704	14	10	4	80000	100	26728	26708	26708	26732	26732
80204	26731	200	0	0	0	0	0	0	44	1	1	26716	2	0	12	16	25	80100	100	80000	100	80015	500	1167459	0	49	23651	26731	26727	16659	6	16659	80114	200	80024	200	160048	26716	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	39	80000	6	1	0	44	1	1	1	5118	1	16	2	2	26704	14	0	7	80000	100	26732	26708	26732	26732	26708
80204	26731	200	0	0	0	0	0	0	44	1	0	26716	0	0	1	19	25	80100	100	80000	100	80014	500	1166596	0	49	23651	26727	26727	16659	6	16683	80114	200	80024	200	160048	26708	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	44	80038	0	0	80038	6	1	38	43	1	1	1	5118	1	16	1	2	26728	0	10	0	80000	100	26732	26728	26728	26732	26732
80204	26707	200	0	0	0	1	0	0	0	1	0	26712	0	0	0	16	25	80100	100	80000	100	80014	500	1167303	0	49	23651	26707	26731	16635	6	16659	80115	200	80024	200	160048	26740	56	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	43	80000	0	39	80038	6	1	0	43	1	1	1	5118	2	16	2	1	26724	10	0	7	80000	100	26708	26708	26728	26728	26728
80204	26731	200	0	0	0	0	0	0	0	1	1	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1166596	0	49	23647	26731	26731	16635	6	16684	80115	200	80024	200	160048	26737	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80038	0	39	80039	0	1	39	0	1	1	1	5118	1	16	1	2	26728	10	0	7	80000	100	26728	26732	26708	26732	26728
80204	26731	200	0	0	0	0	0	0	45	1	0	26712	2	0	0	19	25	80100	100	80000	100	80015	500	1167303	0	49	23627	26727	26731	16655	6	16683	80115	200	80024	200	160048	26716	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	39	80038	6	1	38	0	1	1	1	5118	2	16	2	2	26704	10	10	0	80000	100	26732	26708	26708	26732	26728
80204	26707	200	0	0	1	0	0	0	45	1	1	26692	0	1	0	19	25	80100	100	80000	100	80015	500	1167303	0	49	23647	26727	26727	16659	6	16679	80115	200	80024	200	160048	26739	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	39	80000	6	1	0	43	1	1	1	5118	2	16	2	2	26704	0	0	4	80000	100	26732	26734	26728	26732	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	0	0	0	1	1	0	0	0	0	1	26742	2	12	1	34	25	80010	10	80000	10	80000	50	1167201	1	49	23651	26708	26731	16676	3	16688	80010	20	80000	20	160000	26731	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	0	0	80038	0	41	80038	6	1	0	43	0	0	5020	11	16	6	9	26725	0	14	10	0	80000	10	26732	26732	26709	26732	26732
80024	26708	200	0	0	0	0	0	44	1	0	0	1	26769	2	12	12	19	25	80010	10	80000	10	80000	50	1166896	1	49	23628	26731	26731	16652	3	16707	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80038	0	38	80038	6	1	0	0	0	0	5020	6	16	6	9	26724	1	10	10	7	80000	10	26732	26728	26732	26728	26732
80024	26731	200	0	0	0	0	0	44	0	0	0	1	26756	0	1	12	0	25	80010	10	80000	10	80000	50	1167124	1	49	23651	26731	26731	16676	3	16711	80010	20	80000	20	160000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80039	0	0	80038	0	1	38	43	0	0	5020	7	16	9	9	26705	0	14	14	0	80000	10	26732	26709	26732	26732	26709
80024	26731	200	0	0	0	1	0	44	0	0	0	1	26774	0	1	0	16	25	80010	10	80000	10	80000	50	1167201	1	49	23651	26798	26731	16652	3	16711	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	0	38	80038	0	1	39	44	0	0	5020	9	16	9	7	26705	0	0	10	7	80000	10	26732	26729	26732	26732	26732
80024	26731	200	0	0	0	0	0	0	0	0	0	1	26716	0	1	1	19	25	80010	10	80000	10	80000	50	1167124	1	49	23647	26731	26731	16676	3	16711	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	0	0	80038	0	0	80039	6	0	0	43	0	0	5020	10	16	9	7	26728	0	14	10	0	80000	10	26719	26778	26732	26709	26732
80024	26731	201	0	0	0	0	0	44	0	0	0	1	26784	0	0	1	16	25	80010	10	80000	10	80000	50	1166886	0	49	23654	26731	26731	16676	3	16688	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80038	0	0	80000	0	0	0	0	0	0	5020	9	16	6	9	26708	0	14	0	7	80000	10	26732	26732	26732	26709	26732
80024	26731	200	0	0	0	0	0	0	1	0	0	0	26811	0	0	1	19	25	80010	10	80000	10	80000	50	1167124	0	49	23651	26731	26731	16676	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	43	0	80038	0	39	80038	6	1	38	43	0	0	5020	7	16	7	9	26728	0	10	14	0	80000	10	26732	26729	26709	26728	26728
80024	26727	200	0	0	0	0	0	0	0	0	0	1	26767	3	1	0	19	25	80010	10	80000	10	80000	50	1167501	1	49	23651	26731	26731	16676	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80000	0	0	80039	6	1	0	0	0	0	5020	9	16	9	9	26724	0	0	10	4	80000	10	26732	26709	26732	26709	26732
80024	26731	200	0	0	0	0	1	44	0	0	0	1	26776	0	12	0	19	25	80010	10	80000	10	80000	50	1167124	1	49	23651	26727	26727	16672	3	16707	80010	20	80000	20	160000	26731	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	43	0	80038	0	38	80038	6	1	39	43	0	0	5020	9	16	9	9	26705	0	10	0	7	80000	10	26709	26732	26729	26732	26732
80024	26731	201	0	0	0	0	0	44	0	0	0	0	26770	0	12	0	0	25	80010	10	80000	10	80000	50	1167124	1	49	23628	26731	26731	16676	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80038	1	38	80038	6	1	0	44	0	0	5020	7	16	6	9	26728	0	14	10	4	80000	10	26737	26712	26807	26736	26732

LDRSH (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations