Firestorm: BFXIL (64-bit) measurements

Code:

  bfxil x0, x1, #3, #7

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1036	7	47	25	1000	1000	1000	5999	0	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	0	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	0	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	7	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	0	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037
1004	1036	8	47	25	1000	1000	1000	5999	1	1036	1036	864	3	894	1000	1000	2000	1036	164	1	1	1001	1000	73	1	16	1	1	1032	1000	1000	1037	1037	1037	1037	1037

Test 2: Latency 1->1

Code:

  bfxil x0, x1, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10036	75	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8740	10100	10208	20356	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	35	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	20216	10068	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	16	10033	10000	10100	10037	10037	10069	10037	10037
10204	10036	75	9	58	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	9	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	1970	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	717	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	36	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	6	8740	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	16	10033	10000	10100	10037	10037	10037	10037	10037
10204	10036	75	0	35	25	10100	10100	10100	60499	1	49	6956	10036	10036	8721	7	8739	10100	10208	20216	10036	162	1	1	10201	100	99	100	10100	100	0	0	1	1	1	718	16	10033	10000	10100	10037	10037	10037	10037	10037

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10037	75	0	0	257	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	76	0	1	154	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	68	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	3	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	47	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	18	640	2	16	3	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	360	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	3	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	158	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	3	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	133	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	0	640	2	16	3	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	202	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	3	640	2	16	3	2	10032	10000	10010	10037	10037	10037	10037	10037
10024	10036	75	0	0	420	25	10010	10010	10010	60049	1	49	6956	10036	10036	8736	3	8766	10010	10020	20020	10036	164	1	1	10021	10	9	10	10010	10	0	3	640	2	16	2	2	10032	10000	10010	10037	10037	10037	10037	10037

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  bfxil x0, x1, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	20035	150	0	0	0	0	0	0	0	536	9951	25	20100	20100	20106	1288657	49	16955	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1	1	1	1919	1	16	2	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	0	0	0	0	0	0	61	9951	25	20100	20100	20106	1288657	49	16955	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	149	0	0	0	0	0	0	0	61	9951	25	20100	20100	20106	1288657	49	16955	20035	20035	16160	7	16236	20106	20497	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	0	0	0	0	0	0	61	9951	25	20100	20100	20106	1288657	49	16955	20035	20035	16160	7	16237	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20036	20036	20036	20036	20036
30204	20035	150	0	0	0	0	0	0	0	61	9951	25	20100	20100	20106	1288657	49	16955	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1	1	1	1919	1	16	1	1	20007	20112	30100	20216	20263	20263	20261	20262
30204	20258	152	0	0	5	5	660	88	1	1210	9914	130	20214	20234	20519	1289959	49	17045	20260	20262	16161	26	16328	20421	20679	41158	20263	57	6	1	30201	100	99	100	30100	100	0	2	2	1	0	3858	0	1	1	1	2049	2	101	2	2	20068	20111	30100	20263	20261	20265	20261	20264
30204	20262	152	0	1	6	2	672	440	0	1295	9874	108	20146	20212	20507	1289803	49	17227	20353	20124	16177	30	16317	20106	20211	40222	20081	57	1	1	30201	100	99	100	30100	100	0	0	0	0	0	0	0	1	1	1	1919	1	16	1	1	20007	20000	30100	20081	20036	20272	20036	20080
30204	20125	151	0	0	5	4	672	440	0	1322	9885	130	20212	20210	20523	1289374	49	17181	20263	20262	16179	23	16318	20590	20687	41168	20396	57	5	1	30201	100	99	100	30100	100	0	0	2	1	2	4048	2	1	1	1	2019	1	56	1	1	20211	20069	30100	20263	20127	20218	20307	20265
30204	20260	152	0	0	5	5	660	440	0	1344	9898	193	20307	20283	20497	1290236	49	16955	20035	20035	16160	7	16236	20106	20211	40222	20035	57	1	1	30201	100	99	100	30100	100	0	0	0	25	0	6485	0	1	1	1	1978	1	64	1	1	20213	20133	30100	20308	20081	20352	20308	20311
30204	20171	152	1	0	6	6	801	176	1	2029	9951	25	20100	20122	20100	1288565	49	17046	20126	20035	16153	6	16310	20511	20200	40200	20035	57	1	1	30201	100	99	100	30100	100	0	2	0	1	2	3206	2	1	1	1	2058	3	24	2	3	20203	20000	30100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	20035	150	0	0	0	0	0	0	0	0	0	103	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	5	16	0	5	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	7	16	0	6	6	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	149	0	0	0	0	0	0	0	0	0	84	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16286	20088	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	7	16	1	6	7	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	7	16	0	6	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	7	16	0	7	7	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	191	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	7	16	0	5	8	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	8	16	0	5	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	170	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	9	16	0	6	7	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	346	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	6	16	0	5	5	20003	20000	30010	20036	20036	20036	20036	20036
30024	20035	150	0	0	0	0	0	0	0	0	0	61	9951	25	20010	20010	20010	1287866	0	49	16955	20035	20035	16179	3	16265	20010	20020	40020	20035	57	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	0	0	1890	7	16	0	5	6	20003	20000	30010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  bfxil x0, x8, #3, #7
  bfxil x1, x8, #3, #7
  bfxil x2, x8, #3, #7
  bfxil x3, x8, #3, #7
  bfxil x4, x8, #3, #7
  bfxil x5, x8, #3, #7
  bfxil x6, x8, #3, #7
  bfxil x7, x8, #3, #7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80035	599	0	0	156	0	46	25	80100	80100	80100	400500	1	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	30	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	3	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	39	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	2	0	3	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	24	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80021	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	12	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	36	0	46	25	80100	80100	80100	400500	0	49	76955	80074	80035	69964	3	69993	80131	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	600	0	0	33	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	6	0	46	25	80100	80100	80100	400500	0	49	76955	80035	80035	69964	21	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036
80204	80035	599	0	0	36	0	46	25	80100	80134	80100	400500	0	49	76955	80035	80035	69964	3	69993	80100	80200	160200	80035	164	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	16	2	2	80031	80000	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	599	0	0	210	46	25	80010	80010	80010	400050	1	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	14	16	4	9	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	5	16	5	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	4	16	6	10	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	7	16	6	4	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	6	16	6	7	80032	80000	80010	80036	80036	80036	80036	80081
80024	80035	599	0	1	153	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	2	16	3	6	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	11	16	5	5	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	599	0	0	183	197	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	4	16	5	11	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	217	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	5	16	10	9	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	600	0	0	0	46	25	80010	80010	80010	400050	0	49	76955	80035	80035	69986	3	70015	80010	80020	160020	80035	164	1	1	80021	10	9	10	80010	10	0	0	0	1	5020	0	6	16	5	6	80032	80000	80010	80036	80036	80036	80036	80036

BFXIL (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations