Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PSSBB

Test 1: uops

Code:

  pssbb

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)66696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acbccfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
400427028202001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028202001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028202001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200411000100073116112700010002702927029270292702927029
4004270282030691108270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028202001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028203001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028203001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028202001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028202001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029
400427028202001000270132202510001000100050002600049239482702827028260003260101000100027028270281110010200001000100073116112700010002702927029270292702927029

Test 2: throughput

Code:

  pssbb

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 27.0135

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acbcc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
402042701872062107883107071712802701492201241010010010001100100005005000002601194926705532701352701352600993260117101022001000020027013527017611102011009910010010000200000010000100000007101171127010610000100270136270136270136270136270136
4020427013520240000241000002701202201241010010010000100100005005000002600994926705502701352701352600993260117101002001000020027013521609511102011009910010010000200000010000100000007101171127010610000100270136270136270136270136270136
402042701352023000001000002701202201241010010010000100100005005000002600994926705502701352701352600993260117101002001000020027013521609511102011009910010010000200001010000100000007101171227010610000100270136270136270136270136270136
402042701352023000001000002701202201241010010010000100100005005000002600999826705502701352701352600993260117101002001000020027013521609511102011009910010010024200001010000100000007101171127010610000100270136270136270136270136270136
402042701352023000001000002701492201241010010010000100100005005000002600994926705502701352701352600993260117101002001000020027013521609511102011009910010010000200000010000100000007101171127010610000100270136270136270136270136270136
402042701352023000001000002701202201241010010010000100100005005000002600994926705502701642701352600993260117101002001000020027013525423641102011009910010010000200000010000100000007101171127016110000100270136270136270289270136270136
402042701352023000001000002701202201241010010010000100100005005000002600994926705532701352701352600993260117101002001000020027013521609511102011009910010010000200000010000100000007101171127010610000100270136270136270136270136270136
402042701352024000001000002701202201241010010010000100100005005000002600994926705502701352701352600993260117101002001000020027013521609511102011009910010010000200000010000100000007101171027010610000100270136270136270136270136270136
402042701352023000001000002701202201241010010010000100100005005000002600994926705502701352701352600999260117101002001000020027013521609511102011009910010010000200000210000100000007101171127010610000100270136270136270136270217270136
4020427013520230000151008802701922201241010010010000100100005005000002600994926705502701352701352600993260117101002001000020027013521609521102011009910010010000200004010665100002007101261127010610000100270136270136270136270136270136

1000 unrolls and 10 iterations

Result (median cycles for code): 27.0045

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6066696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbcc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
400242700612022000001000002700302200341001210100001010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200000100001000000640317332700161000010270046270046270046270046270046
4002427004520230000481000002700302200341001010100001010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200000100001000000640317222700161000010270046270046270046270046270046
400242700452023000001000002700302200341001010100001010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200000100001000000640317222700161000010270046270046270046270046270046
40024270045202300001411000002700302200341001010100001010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200000100001000000640317222700161000010270046270046270046270046270046
4002527004520230000451000002700302200341001010100001010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200000100001000000640317332700161000010270046270046270046270046270046
400242700452092000001000002700302200341001010100001010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200001100001000000656317332700161000010270046270046270046270046270046
400242700452022000001000002700302200341001010100021010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200000100001000000640317222700161000010270046270046270046270046270046
400242700452023000001000002700302200341001010100001010000505000002600094926696527004527004526000932600271001020100002027004527004511100211091010100200000100001000000640321332700161000010270046270046270046270046270046
40024270070202300001261000002700302200341001010100001010000505000002600094926696527004527004526000932600271001020100002027004527004521100211091010100200000100001000000640317332700161000010270046270046270075270046270046
400242700452023000001000002700302200341001010100001010000505000002600094926392327004527004526000932600271001020100002027004527004511100211091010100200000100001000000640317432700161000010270046270046270046270046270046