Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stp x0, x1, [x6, #8]!
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 23 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | ldst x64 uop (b1) | bc | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 8 | 0 | 0 | 6 | 3 | 24 | 0 | 0 | 0 | 0 | 1025 | 0 | 1 | 6 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 76 | 4 | 30 | 1000 | 0 | 30 | 26 | 0 | 1027 | 125 | 0 | 85 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 3 | 20 | 0 | 0 | 6 | 0 | 1025 | 15 | 11 | 7 | 2 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1026 | 0 | 69 | 1 | 0 | 1000 | 0 | 16 | 0 | 3 | 1032 | 125 | 0 | 69 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 0 | 0 | 45 | 4 | 18 | 1 | 0 | 0 | 0 | 1025 | 9 | 1 | 5 | 0 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 0 | 60 | 0 | 21 | 1001 | 0 | 18 | 20 | 1 | 1000 | 125 | 1 | 56 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 4 | 18 | 0 | 0 | 6 | 24 | 1025 | 15 | 1 | 4 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 0 | 71 | 2 | 12 | 1001 | 0 | 14 | 6 | 0 | 1018 | 125 | 0 | 34 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 1025 | 0 | 1 | 5 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1012 | 6 | 43 | 0 | 18 | 1000 | 1 | 18 | 12 | 0 | 1016 | 125 | 0 | 60 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 6 | 3 | 14 | 1 | 0 | 8 | 0 | 1025 | 6 | 2 | 9 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1020 | 12 | 34 | 0 | 14 | 1001 | 0 | 14 | 4 | 0 | 1008 | 125 | 0 | 34 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 0 | 3 | 14 | 1 | 0 | 15 | 0 | 1025 | 10 | 1 | 8 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 60 | 0 | 0 | 1000 | 0 | 0 | 0 | 0 | 1000 | 125 | 0 | 52 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 57 | 5 | 14 | 1 | 0 | 12 | 0 | 1025 | 9 | 1 | 4 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 0 | 52 | 0 | 0 | 1000 | 0 | 0 | 0 | 0 | 1000 | 125 | 0 | 25 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 5 | 20 | 1 | 0 | 7 | 0 | 1025 | 17 | 2 | 4 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1026 | 0 | 34 | 2 | 12 | 1001 | 0 | 0 | 0 | 0 | 1000 | 125 | 0 | 51 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 3 | 10 | 1 | 0 | 10 | 0 | 1025 | 13 | 5 | 9 | 1 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50778 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1014 | 0 | 39 | 3 | 9 | 1000 | 0 | 32 | 8 | 3 | 1022 | 125 | 0 | 65 | 73 | 1 | 16 | 1 | 1 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
stp x0, x1, [x6, #8]!
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | aa | ab | ac | af | ldst x64 uop (b1) | ldst xpg uop (b2) | bc | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10209 | 10040 | 75 | 0 | 2010 | 72 | 792 | 1 | 752 | 87 | 0 | 100 | 10025 | 766 | 124 | 189 | 34 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522163 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10862 | 0 | 1336 | 382 | 0 | 665 | 10255 | 243 | 918 | 40 | 710 | 10901 | 1250 | 4 | 21 | 1199 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 59 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2031 | 53 | 792 | 1 | 736 | 83 | 2 | 112 | 10025 | 758 | 120 | 162 | 25 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522203 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10858 | 0 | 1297 | 382 | 0 | 660 | 10258 | 231 | 860 | 40 | 754 | 10903 | 1250 | 4 | 21 | 1270 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 7 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 1878 | 72 | 802 | 1 | 720 | 78 | 1 | 116 | 10025 | 761 | 103 | 168 | 23 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522203 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10886 | 0 | 1419 | 353 | 0 | 665 | 10240 | 240 | 854 | 34 | 731 | 10888 | 1250 | 4 | 20 | 1298 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 77 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 1866 | 65 | 813 | 1 | 704 | 88 | 0 | 160 | 10025 | 769 | 92 | 159 | 22 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522123 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10878 | 0 | 1419 | 365 | 0 | 631 | 10236 | 255 | 922 | 36 | 806 | 10906 | 1250 | 4 | 17 | 1196 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 18 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 1827 | 56 | 767 | 1 | 736 | 85 | 4 | 116 | 10025 | 757 | 90 | 176 | 32 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522131 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10862 | 0 | 1315 | 356 | 0 | 677 | 10260 | 233 | 874 | 32 | 689 | 10907 | 1250 | 4 | 19 | 1194 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 7 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 1911 | 78 | 768 | 1 | 728 | 87 | 2 | 88 | 10025 | 770 | 114 | 185 | 37 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522123 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10892 | 0 | 1324 | 357 | 0 | 645 | 10256 | 235 | 894 | 36 | 769 | 10895 | 1250 | 4 | 17 | 1161 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 17 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 1839 | 58 | 763 | 1 | 720 | 75 | 0 | 108 | 10025 | 774 | 108 | 164 | 27 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522179 | 468824 | 1 | 49 | 6960 | 10093 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10912 | 0 | 1383 | 360 | 0 | 632 | 10251 | 224 | 898 | 32 | 736 | 10894 | 1250 | 4 | 26 | 1300 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 54 | 1 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2049 | 74 | 797 | 1 | 752 | 70 | 0 | 160 | 10025 | 763 | 109 | 167 | 32 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522155 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10906 | 0 | 1377 | 380 | 0 | 645 | 10231 | 234 | 862 | 36 | 717 | 10919 | 1250 | 4 | 22 | 1224 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 72 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 1926 | 67 | 813 | 1 | 664 | 75 | 4 | 144 | 10025 | 794 | 113 | 157 | 34 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522133 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10874 | 0 | 1403 | 380 | 0 | 673 | 10230 | 257 | 876 | 32 | 745 | 10884 | 1250 | 4 | 22 | 1254 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 7 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 1953 | 64 | 819 | 1 | 664 | 98 | 0 | 108 | 10025 | 769 | 111 | 142 | 26 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522133 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10900 | 0 | 1329 | 367 | 0 | 653 | 10257 | 256 | 867 | 98 | 786 | 10936 | 1250 | 4 | 22 | 1240 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 81 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 61 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | ldst x64 uop (b1) | ldst xpg uop (b2) | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10029 | 10040 | 75 | 1 | 1 | 0 | 0 | 2223 | 68 | 817 | 1 | 736 | 65 | 0 | 108 | 10025 | 790 | 120 | 204 | 40 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521049 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10893 | 14 | 1421 | 360 | 630 | 10278 | 242 | 0 | 890 | 114 | 735 | 10904 | 1250 | 4 | 34 | 1205 | 14 | 2 | 640 | 0 | 0 | 3 | 16 | 3 | 3 | 10037 | 10000 | 93 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 0 | 0 | 0 | 2121 | 76 | 809 | 1 | 744 | 85 | 3 | 144 | 10025 | 774 | 141 | 201 | 39 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521065 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10934 | 18 | 1401 | 366 | 667 | 10283 | 231 | 0 | 889 | 64 | 767 | 10948 | 1250 | 4 | 34 | 1299 | 14 | 0 | 640 | 0 | 0 | 2 | 16 | 3 | 3 | 10037 | 10000 | 11 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 2 | 0 | 0 | 2076 | 79 | 834 | 1 | 752 | 72 | 1 | 100 | 10025 | 754 | 125 | 183 | 27 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521009 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8769 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10900 | 14 | 1434 | 350 | 670 | 10284 | 293 | 0 | 913 | 58 | 825 | 10901 | 1250 | 4 | 36 | 1353 | 14 | 0 | 640 | 0 | 0 | 3 | 16 | 3 | 2 | 10037 | 10000 | 6 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 0 | 0 | 0 | 2016 | 82 | 815 | 1 | 776 | 81 | 0 | 284 | 10025 | 767 | 121 | 200 | 44 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521033 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10927 | 16 | 1463 | 392 | 639 | 10276 | 269 | 0 | 868 | 46 | 805 | 10926 | 1250 | 4 | 37 | 1229 | 14 | 2 | 640 | 0 | 0 | 3 | 16 | 2 | 2 | 10037 | 10000 | 77 | 1 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 2 | 0 | 2 | 0 | 2091 | 75 | 771 | 1 | 696 | 73 | 2 | 116 | 10025 | 782 | 138 | 185 | 41 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521025 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10928 | 7 | 1424 | 376 | 650 | 10275 | 282 | 0 | 937 | 38 | 792 | 10894 | 1250 | 4 | 26 | 1381 | 7 | 0 | 640 | 0 | 0 | 3 | 16 | 3 | 3 | 10037 | 10000 | 86 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 1 | 0 | 0 | 0 | 1983 | 63 | 808 | 1 | 728 | 79 | 0 | 112 | 10025 | 793 | 102 | 144 | 31 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521065 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10927 | 7 | 1294 | 409 | 643 | 10270 | 272 | 0 | 858 | 64 | 767 | 10905 | 1250 | 4 | 32 | 1327 | 7 | 2 | 640 | 0 | 0 | 3 | 16 | 3 | 3 | 10037 | 10000 | 87 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 1 | 0 | 2169 | 75 | 797 | 1 | 712 | 72 | 2 | 112 | 10025 | 788 | 161 | 204 | 28 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10913 | 7 | 1365 | 370 | 690 | 10290 | 277 | 0 | 879 | 52 | 808 | 10900 | 1250 | 4 | 32 | 1107 | 7 | 0 | 640 | 0 | 0 | 2 | 16 | 3 | 3 | 10037 | 10000 | 18 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 2076 | 78 | 853 | 1 | 728 | 75 | 1 | 136 | 10025 | 779 | 147 | 184 | 31 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521081 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10929 | 7 | 1294 | 380 | 698 | 10258 | 248 | 2 | 867 | 38 | 813 | 10921 | 1250 | 4 | 31 | 1235 | 7 | 4 | 640 | 0 | 0 | 3 | 16 | 3 | 3 | 10037 | 10000 | 100 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 0 | 0 | 0 | 2067 | 84 | 809 | 1 | 768 | 83 | 0 | 144 | 10025 | 776 | 137 | 197 | 29 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521097 | 468824 | 1 | 5 | 49 | 6960 | 10040 | 10040 | 8696 | 6 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10918 | 9 | 1401 | 381 | 655 | 10273 | 239 | 1 | 916 | 46 | 1568 | 10903 | 1250 | 4 | 29 | 1310 | 7 | 2 | 640 | 0 | 0 | 3 | 16 | 3 | 3 | 10037 | 10000 | 6 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 1 | 1 | 0 | 0 | 2241 | 80 | 812 | 1 | 760 | 81 | 1 | 100 | 10025 | 794 | 118 | 220 | 36 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521073 | 468824 | 1 | 5 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10918 | 7 | 1434 | 382 | 658 | 10264 | 262 | 1 | 903 | 44 | 846 | 10950 | 1250 | 4 | 27 | 1292 | 7 | 0 | 640 | 5 | 4 | 3 | 16 | 3 | 3 | 10037 | 10000 | 15 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
stp x0, x1, [x6, #8]! stp x0, x1, [x7, #8]! stp x0, x1, [x8, #8]! stp x0, x1, [x9, #8]! stp x0, x1, [x10, #8]! stp x0, x1, [x11, #8]! stp x0, x1, [x12, #8]! stp x0, x1, [x13, #8]!
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5237
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 20 | 22 | 23 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 67 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | ldst x64 uop (b1) | ldst xpg uop (b2) | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80209 | 41928 | 313 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1731 | 833 | 798 | 1 | 0 | 712 | 135 | 96 | 41861 | 760 | 2062 | 2908 | 1305 | 25 | 161812 | 80807 | 80000 | 80100 | 80000 | 403540 | 1928056 | 265 | 49 | 38882 | 0 | 42001 | 41916 | 31826 | 3 | 31845 | 160100 | 200 | 80000 | 200 | 240000 | 41898 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80955 | 0 | 4956 | 480 | 873 | 854 | 80578 | 250 | 0 | 902 | 76 | 1497 | 81447 | 10000 | 32 | 662 | 5201 | 12 | 1 | 0 | 5110 | 1 | 16 | 1 | 1 | 41966 | 82971 | 80000 | 80100 | 41960 | 41931 | 41879 | 41900 | 41893 |
| 80204 | 41833 | 314 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1680 | 810 | 778 | 1 | 0 | 704 | 135 | 120 | 41908 | 794 | 1716 | 2536 | 1325 | 25 | 163364 | 82220 | 80000 | 80100 | 80000 | 401872 | 1927240 | 226 | 49 | 38759 | 0 | 41860 | 41790 | 31797 | 3 | 31911 | 160100 | 200 | 80000 | 200 | 240000 | 41998 | 82 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80933 | 13 | 5373 | 475 | 869 | 885 | 80568 | 262 | 0 | 911 | 44 | 1513 | 81545 | 10000 | 32 | 636 | 5720 | 13 | 2 | 0 | 5110 | 1 | 17 | 1 | 1 | 41865 | 80597 | 80000 | 80100 | 41910 | 41898 | 41930 | 41938 | 41961 |
| 80204 | 41897 | 314 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1845 | 780 | 803 | 1 | 0 | 768 | 123 | 144 | 41883 | 776 | 1642 | 2511 | 1329 | 25 | 161513 | 83451 | 80000 | 80100 | 80000 | 406610 | 1926184 | 421 | 49 | 38899 | 0 | 41967 | 41960 | 31819 | 3 | 31850 | 160100 | 200 | 80000 | 200 | 240000 | 41847 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80951 | 13 | 5798 | 451 | 869 | 862 | 80574 | 266 | 2 | 904 | 46 | 1637 | 81451 | 10000 | 32 | 587 | 4536 | 13 | 2 | 0 | 5110 | 1 | 17 | 1 | 1 | 41905 | 81843 | 80000 | 80100 | 41965 | 41816 | 41852 | 41853 | 41916 |
| 80204 | 41783 | 314 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1845 | 820 | 764 | 1 | 0 | 680 | 146 | 144 | 41817 | 798 | 2100 | 2520 | 1330 | 25 | 161453 | 82621 | 80015 | 80100 | 80000 | 402302 | 1928296 | 342 | 49 | 38745 | 0 | 41861 | 42012 | 31793 | 3 | 31939 | 160100 | 200 | 80000 | 200 | 240000 | 41956 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80942 | 0 | 5320 | 488 | 862 | 900 | 80634 | 250 | 0 | 924 | 46 | 1539 | 81485 | 10000 | 32 | 606 | 5002 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 41875 | 80443 | 80000 | 80100 | 41886 | 41893 | 41853 | 41952 | 41928 |
| 80204 | 41874 | 314 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1575 | 821 | 776 | 1 | 0 | 672 | 143 | 172 | 41929 | 844 | 1942 | 2596 | 1372 | 25 | 160878 | 80636 | 80000 | 80100 | 80000 | 404015 | 1931656 | 343 | 49 | 38874 | 0 | 41822 | 41890 | 31741 | 3 | 31866 | 160100 | 200 | 80000 | 200 | 240000 | 41848 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80973 | 14 | 4572 | 449 | 859 | 898 | 80545 | 273 | 0 | 917 | 32 | 1579 | 81499 | 10000 | 32 | 635 | 4572 | 13 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 41862 | 82297 | 80000 | 80100 | 41891 | 41857 | 41876 | 41950 | 41968 |
| 80204 | 41899 | 313 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1836 | 731 | 801 | 1 | 0 | 680 | 135 | 100 | 41949 | 815 | 1619 | 2237 | 1303 | 25 | 160827 | 83804 | 80000 | 80100 | 80000 | 402480 | 1926712 | 333 | 49 | 38855 | 0 | 41880 | 41850 | 31817 | 3 | 31897 | 160100 | 200 | 80000 | 200 | 240000 | 41981 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80928 | 8 | 5446 | 470 | 878 | 900 | 80744 | 296 | 0 | 856 | 38 | 1622 | 81469 | 10000 | 32 | 650 | 5076 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 41822 | 84081 | 80000 | 80100 | 41921 | 41952 | 41927 | 41822 | 41920 |
| 80204 | 41930 | 314 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1698 | 840 | 811 | 1 | 0 | 736 | 116 | 132 | 42075 | 831 | 2015 | 2697 | 1307 | 25 | 160856 | 81084 | 80000 | 80100 | 80000 | 402133 | 1926928 | 284 | 49 | 38860 | 0 | 41856 | 41888 | 31854 | 3 | 31783 | 160320 | 200 | 80000 | 200 | 240000 | 41951 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80970 | 0 | 5276 | 465 | 863 | 892 | 80672 | 289 | 2 | 923 | 44 | 1596 | 81516 | 10000 | 32 | 594 | 4845 | 0 | 0 | 0 | 5110 | 1 | 17 | 1 | 1 | 42037 | 82288 | 80000 | 80100 | 41907 | 41866 | 41899 | 41905 | 41873 |
| 80204 | 41815 | 315 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1851 | 920 | 791 | 1 | 0 | 680 | 123 | 104 | 41834 | 771 | 2051 | 2415 | 1324 | 25 | 162194 | 82911 | 80000 | 80100 | 80000 | 404172 | 1927751 | 281 | 49 | 38821 | 0 | 41820 | 41927 | 31853 | 3 | 31940 | 160100 | 200 | 80000 | 200 | 240000 | 41943 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80947 | 0 | 5011 | 487 | 857 | 886 | 80656 | 276 | 0 | 933 | 88 | 1572 | 81477 | 10000 | 32 | 583 | 5060 | 14 | 1 | 0 | 5110 | 1 | 17 | 1 | 1 | 41846 | 80759 | 80000 | 80100 | 41996 | 41892 | 41955 | 41902 | 42022 |
| 80204 | 41905 | 315 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1749 | 759 | 773 | 1 | 0 | 632 | 114 | 104 | 41868 | 777 | 1848 | 2676 | 1273 | 25 | 160858 | 82344 | 80000 | 80100 | 80000 | 402354 | 1928896 | 203 | 49 | 38851 | 0 | 41862 | 41935 | 31801 | 3 | 31869 | 160100 | 200 | 80000 | 200 | 240000 | 41845 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80921 | 0 | 4915 | 426 | 853 | 890 | 80569 | 241 | 0 | 864 | 46 | 1554 | 81518 | 10000 | 32 | 612 | 5533 | 13 | 1 | 0 | 5110 | 1 | 17 | 1 | 1 | 41911 | 80390 | 80000 | 80100 | 41879 | 41825 | 41914 | 41983 | 41855 |
| 80204 | 41965 | 314 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1803 | 832 | 823 | 1 | 0 | 736 | 119 | 88 | 41910 | 781 | 1758 | 2399 | 1261 | 25 | 160768 | 83341 | 80000 | 80100 | 80000 | 402139 | 1926664 | 812 | 49 | 38813 | 0 | 41962 | 41954 | 31857 | 3 | 32022 | 160100 | 200 | 80000 | 200 | 240000 | 41978 | 82 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80952 | 0 | 5371 | 481 | 887 | 906 | 80582 | 241 | 0 | 892 | 36 | 1489 | 81493 | 10000 | 32 | 537 | 5588 | 0 | 0 | 0 | 5110 | 1 | 16 | 1 | 1 | 41986 | 81173 | 80000 | 80100 | 42064 | 41880 | 41931 | 41875 | 41893 |
Result (median cycles for code divided by count): 0.5258
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5f | 60 | 67 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | ldst x64 uop (b1) | ldst xpg uop (b2) | bc | l1d cache miss st nonspec (c0) | cd | cf | d5 | map dispatch bubble (d6) | d9 | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80029 | 42178 | 315 | 3 | 0 | 1632 | 914 | 819 | 1 | 688 | 149 | 120 | 42141 | 791 | 1758 | 2640 | 1413 | 25 | 163562 | 80408 | 80000 | 80010 | 80000 | 404213 | 1937156 | 1 | 0 | 327 | 49 | 38936 | 0 | 42045 | 42063 | 32063 | 3 | 32135 | 160010 | 20 | 80360 | 20 | 240000 | 42047 | 76 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80981 | 0 | 5412 | 486 | 905 | 850 | 80686 | 275 | 0 | 886 | 70 | 1674 | 81618 | 10000 | 32 | 600 | 5293 | 0 | 5020 | 9 | 16 | 0 | 4 | 2 | 42037 | 80693 | 80000 | 80010 | 42155 | 42184 | 42097 | 42095 | 42062 |
| 80024 | 42061 | 315 | 3 | 0 | 1842 | 851 | 857 | 1 | 752 | 162 | 152 | 42097 | 778 | 1995 | 2764 | 1444 | 25 | 162376 | 81064 | 80000 | 80010 | 80000 | 412210 | 1938668 | 0 | 0 | 1352 | 49 | 38962 | 0 | 42033 | 42015 | 31934 | 3 | 32081 | 160010 | 20 | 80000 | 20 | 240000 | 42146 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80975 | 0 | 6224 | 463 | 913 | 852 | 80573 | 268 | 0 | 902 | 34 | 1659 | 81666 | 10000 | 32 | 608 | 4887 | 0 | 5020 | 4 | 16 | 0 | 2 | 4 | 42083 | 81151 | 80000 | 80010 | 42083 | 41998 | 42084 | 42030 | 42135 |
| 80024 | 42152 | 316 | 2 | 0 | 1662 | 819 | 830 | 1 | 704 | 139 | 220 | 42117 | 801 | 1815 | 2450 | 1412 | 25 | 163447 | 81049 | 80000 | 80010 | 80000 | 402832 | 1935187 | 0 | 0 | 812 | 49 | 39063 | 0 | 42015 | 42053 | 31995 | 3 | 32078 | 160010 | 20 | 80000 | 20 | 240000 | 42077 | 76 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80929 | 0 | 5899 | 510 | 915 | 867 | 80643 | 249 | 0 | 885 | 30 | 1638 | 81600 | 10000 | 32 | 635 | 4737 | 0 | 5020 | 5 | 16 | 0 | 2 | 4 | 42009 | 81451 | 80000 | 80010 | 42045 | 42089 | 42083 | 42014 | 42125 |
| 80024 | 42052 | 315 | 2 | 0 | 1779 | 844 | 804 | 1 | 656 | 149 | 124 | 42013 | 784 | 1683 | 2797 | 1468 | 25 | 160555 | 80391 | 80242 | 80010 | 80000 | 401670 | 1941485 | 0 | 0 | 629 | 49 | 39019 | 0 | 42101 | 42065 | 32030 | 21 | 31986 | 160010 | 20 | 80000 | 20 | 240000 | 42089 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80995 | 0 | 5758 | 481 | 911 | 837 | 80611 | 266 | 0 | 877 | 82 | 1682 | 81588 | 10000 | 32 | 605 | 5212 | 0 | 5020 | 4 | 15 | 0 | 4 | 2 | 42064 | 81088 | 80000 | 80010 | 42085 | 42066 | 42158 | 41955 | 41999 |
| 80024 | 42026 | 314 | 2 | 0 | 1668 | 812 | 814 | 1 | 632 | 138 | 144 | 42029 | 773 | 1847 | 2749 | 1408 | 25 | 160746 | 80753 | 80000 | 80010 | 80000 | 401515 | 1936096 | 1 | 0 | 391 | 49 | 38952 | 0 | 42083 | 42213 | 32117 | 3 | 32177 | 160010 | 20 | 80000 | 20 | 240000 | 42116 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80965 | 0 | 5868 | 517 | 882 | 910 | 80592 | 260 | 0 | 891 | 68 | 1538 | 81593 | 10000 | 32 | 644 | 5044 | 0 | 5020 | 4 | 16 | 0 | 4 | 2 | 42077 | 81305 | 80000 | 80010 | 41955 | 41984 | 42044 | 42118 | 42029 |
| 80024 | 42103 | 315 | 2 | 0 | 1935 | 871 | 807 | 1 | 688 | 122 | 192 | 42188 | 802 | 1901 | 3118 | 1389 | 25 | 160985 | 84259 | 80002 | 80010 | 80000 | 402230 | 1932232 | 0 | 1 | 350 | 49 | 38983 | 0 | 41995 | 42116 | 31957 | 3 | 32109 | 160010 | 20 | 80000 | 20 | 240000 | 42047 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80981 | 0 | 5373 | 489 | 900 | 926 | 80688 | 261 | 0 | 904 | 54 | 1563 | 81606 | 10000 | 32 | 589 | 4303 | 0 | 5020 | 2 | 15 | 0 | 4 | 2 | 42159 | 80645 | 80000 | 80010 | 42129 | 42117 | 42117 | 42052 | 42189 |
| 80024 | 42044 | 315 | 2 | 0 | 1767 | 893 | 800 | 1 | 520 | 140 | 100 | 41996 | 788 | 1791 | 2720 | 1424 | 25 | 160496 | 81331 | 80000 | 80010 | 80000 | 402697 | 1940060 | 0 | 0 | 374 | 49 | 39062 | 0 | 42061 | 42160 | 32056 | 3 | 32031 | 160010 | 20 | 80000 | 20 | 240000 | 42075 | 76 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80941 | 0 | 5403 | 473 | 884 | 898 | 80629 | 253 | 2 | 878 | 32 | 1717 | 81515 | 10000 | 32 | 664 | 5524 | 0 | 5020 | 4 | 48 | 0 | 4 | 2 | 42069 | 82228 | 80000 | 80010 | 41998 | 42566 | 42157 | 42052 | 42178 |
| 80024 | 42190 | 315 | 2 | 0 | 1881 | 829 | 792 | 1 | 760 | 127 | 152 | 42286 | 801 | 1859 | 2348 | 1424 | 25 | 161198 | 80639 | 80018 | 80010 | 80000 | 402936 | 1937104 | 0 | 0 | 542 | 49 | 38924 | 0 | 42118 | 42006 | 32032 | 3 | 32157 | 160010 | 20 | 80000 | 20 | 240000 | 41981 | 75 | 2 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80951 | 0 | 5491 | 443 | 916 | 901 | 80670 | 231 | 0 | 883 | 32 | 1619 | 81578 | 10000 | 32 | 695 | 5521 | 0 | 5020 | 4 | 18 | 0 | 6 | 3 | 42498 | 82932 | 80000 | 80010 | 42188 | 42039 | 42205 | 42044 | 42137 |
| 80024 | 42055 | 316 | 1 | 0 | 1752 | 1219 | 806 | 1 | 688 | 135 | 140 | 42284 | 800 | 2153 | 2290 | 1404 | 25 | 162095 | 83825 | 80000 | 80010 | 80000 | 403246 | 1937968 | 0 | 0 | 268 | 49 | 39058 | 0 | 42047 | 42011 | 32033 | 3 | 32109 | 160010 | 20 | 80000 | 20 | 240000 | 41931 | 76 | 1 | 1 | 80022 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80982 | 0 | 5670 | 499 | 880 | 913 | 80619 | 272 | 0 | 902 | 38 | 1640 | 81575 | 10000 | 32 | 656 | 5463 | 0 | 5020 | 2 | 16 | 0 | 2 | 4 | 42046 | 80537 | 80000 | 80010 | 42102 | 41992 | 42106 | 42009 | 42031 |
| 80024 | 42113 | 315 | 2 | 0 | 1866 | 816 | 801 | 1 | 736 | 136 | 164 | 42063 | 779 | 1873 | 2801 | 1381 | 25 | 160771 | 80482 | 80000 | 80010 | 80000 | 401804 | 1934848 | 0 | 0 | 327 | 49 | 38957 | 0 | 42113 | 42047 | 32047 | 3 | 32042 | 160010 | 20 | 80000 | 20 | 240000 | 41966 | 75 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80943 | 0 | 5289 | 469 | 901 | 946 | 80632 | 268 | 0 | 920 | 36 | 1631 | 81571 | 10000 | 32 | 616 | 5112 | 0 | 5020 | 4 | 16 | 0 | 2 | 4 | 42138 | 81149 | 80000 | 80010 | 42089 | 42027 | 42053 | 42075 | 42008 |