Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (uxtb, 64-bit)

Test 1: uops

Code:

  cmp x0, w1, uxtb
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb miss (a1)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
10047095061100030425200020001000408770709709498253561100010002000709781110011000073222226842000710710710710710
10047095061100030425200020001000408770709709498213561100010002000709781110011000073222226842000710710710710710
10047095061100030425200020001000408771709709498253561100010002000709781110011000073222226842000710710710710710
10047096061100030425200020001000408770709709498213561100010002000709781110011000073222226842000710710710710710
10047096061100030425200020001000408770709709498253561100010002000709781110011000073222226842000710710710710710
10047096061100030425200020001000408771709709498213561100010002000709781110011000473222226842000710710710710710
10047095061100030425200020001000408770709709498213561100010002000709781110011000073222226842000710710710710710
10047095061100030425200020001000408771709709498213561100010002000709781110011000073222226842000710710710710710
10047096061100030425200020001000408770709709498253561100010002000709781110011000073222226842000710710710710710
10047095061100030425200020001000408771709709498213561100010002000709781110011000073222226842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp x0, w1, uxtb
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035224061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804927135300353003527369327478201002020030367300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804927059300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035224061100002989325301003010020100195619804926955300353003527369327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522501566110000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000127053305132995830000100103003630036300363003630036
2002430035225066110000298912530010300102001019562890492695530035300352739119274982001020020300203003514511200211091020010100100012701333011132995830000100103003630036300363003630036
200243003522506611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100012701333013132995830000100103003630036300363003630036
200243003522509611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100012701133013112995830000100103003630036300363003630036
200243003522406611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100012701133012112995830000100103003630036300363003630036
200243003522506611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100012701433013112995830000100103003630036300363003630036
200243003522506611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100012701333013112995830000100103003630036300363003630036
2002430035225018611000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100012701133013112995830000100103003630036300363003630036
2002430035225090611000029891253001030010200101956289049269553003530035273913274982001020020300203003529111200211091020010100100012701233014142995830000100103003630036300363003630036
200243003522506611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100012701333010132995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp x0, w1, uxtb
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250297410000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522406110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522406110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225156110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000113101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010006013101231222995430000101003003630036300363003630036
202043003522506110000298932530132301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035145112002110910200101001000001270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000001270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010007501270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000001270133112995830000100103003630036300363006730036
20024300352250568310000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000001270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000001270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000041270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530066300352739132749820010200203002030035145112002110910200101001010001270133112995830000100103003630036300363003630036
200243003522406110000298912530010300102001019562890492695530035300352739132749820010200203002030035145112002110910200101001000001270133112995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmp x0, w1, uxtb
  cmp x0, w1, uxtb
  cmp x0, w1, uxtb
  cmp x0, w1, uxtb
  cmp x0, w1, uxtb
  cmp x0, w1, uxtb
  cmp x0, w1, uxtb
  cmp x0, w1, uxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03181e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020453433400000618000048741251601001601008010034400051495033053410534104329820633433608010080200160200534107811802011009910080100100024000511022411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005049503305341053410432982050343360801008020016020053410781180201100991008010010006000511012411533921600001005341153411534115341153411
8020453410400000232800004874125160100160100801003440005049503305341053410432982060343360801008020016020053410781180201100991008010010019000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005149503305341053410432982060343360801008020016020053410781180201100991008010010009000511012411533921600001005341153411534115341153411
80204534104000006180000487412516010016010080100344392214950330534105341043298206034336080100802001602005341078118020110099100801001000201000511012411533921600001005341153411534115341153411
80204534104000006180000487412516010016010080100344000514950330534105341043298205034336080100802001602005341078118020110099100801001000129000514012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005149503305341053410432982063343360801008020016020053410781180201100991008010010006001511012411533921600001005341153411534115341153411
8020453410400012061800004874125160100160100801003440005149503305341053410432982060343360801008020016020053410781180201100991008010010000000511012421533921600001005341153411534115341153411
80204534104000006180000487412516010016010080100344000504950330534105341043298206334336080100802001602005341078118020110099100801001000183000511012411533921600001005341153411534115341153411
80204534104000006180000487412516010016010080100344143514950330534105341043298206034336080100802001602005341078118020110099100801001000183000511012421533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800245340239900618000047946251600101600108001034381300049503000533805338043290256234335280010800201600205338078118002110910800101000023100050201124141453359160000105338153381533815338153381
8002453380400006180000479462516001016001080010343813000495030005338053380432902562343352800108002016002053380781180021109108001010000000050201224141253359160000105338153381533815338153381
8002453380400006180000479462516001016001080010343813000495030005338053380432902707343352800108002016002053380781180021109108001010000000050201124141453359160000105338153381533815338153381
800245338040000828000047946251600101600108018034381300049503000533805338043290256234335280010800201600205338078118002110910800101000024600050201424141253359160000105338153381533815338153381
8002453380399006180000479462516001016001080010343813000495030005338053380432902707343352800108002016002053380781180021109108001010000000050201124121153359160000105338153381533815338153381
8002453380399036180000479462516001016001080010343813000495030005338053380432902562343352800108002016002053380781180021109108001010000000050201324121453359160000105338153381533815338153381
8002453380400007268000047946251600101600108001034381300049503000533805338043290256234335280010800201600205338078118002110910800101001018600050201424141453359160000105338153381533815338153381
8002453380399006180000479462516001016001080010343813000495030005338053380432902562343352800108002016002053380781180021109108001010000000050201424121253359160000105338153381533815338153381
800245338040000618000047946251600101600108001034381300149503000533805338043290256234335280010800201600205338078118002110910800101000022800050201524121353359160000105338153381533815338153381
8002453380400006180000479462516001016012780010343813000495030005338053380432902562343352800108002016002053380781180021109108001010000000050201424131453359160000105338153381533815338153381