Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BICS (register, lsr, 64-bit)

Test 1: uops

Code:

  bics x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035156611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235120352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035160611000186225200020001000126235020352035172931866100010002000203541111001100010731431119202000100020362036203620362036
100420351545611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036
10042035150611000186225200020001000126235020352035172931866100010002000203541111001100000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  bics x0, x0, x1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000039061100001986225201002010010100130512104916955200352003518581318720101001020020200200354111102011009910010100100200710139111996020000101002003620082200832008220036
1020420035150101088324100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000000459100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000000234100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
102042003514900060440100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100600710139111992220000101002003620036200362003620036
102042003515000000378100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500101718861100001986225201002010010100130512114916955200352003518581318720101001020020200200354121102011009910010100100000710139111992220000101002003620036200362003620036
102042003515000000593100001986225201002013810100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
1020420035150000210149100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100060710139111992220000101002003620036200362003620036
102042003515000000124100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500030611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640441551993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640641661993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640641651993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640541661993020000100102003620036200362003620036
100242003515000270611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640541651993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640641651993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640541661993020000100102003620036200362003620036
10024200351500000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640641651993020000100102003620036200362003620036
1002420035150002610611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640541551993020000100102003620036200362003620036
100242003515000270611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010640541661993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  bics x0, x1, x0, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515006110000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139211992220000101002003620036200362008120082
1020420035149051610000198622520100201001010013058524916955020035200351858191874610185102902020020035411110201100991001010010000710139111995520033101002003620036200362003620036
1020420035150031910000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515033103100001986225201002010010100130512149169550200352003518581318720101001020020200200354111102011009910010100100015710139111992220000101002003620036200362003620036
1020420035150017010000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150010310000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150126110000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515096110000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
1020420035150016610000198622520100201001010013051214916955020035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351506306110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640341221993020000100102003620036200362003620036
1002420035150006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010013640241221993020000100102003620036200362003620036
10024200351502106110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010200640241321993020000100102003620036200362003620036
10024200351502706110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
10024200351501206110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010010640241221993020000100102003620036200362003620036
10024200351503606110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036
100242003515024053610000198782520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010003640241221993020000100102003620036200362003620036
10024200351502106110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010010640245321993020000100102003620083200822008220036
100242003515021045410000198622520032200101001013060000491695520082200351860331874010010100202002020035411110021109101001010010640241221993020000100102003620036200362003620036
1002420035150006110000198622520010200101001013052290491695520035200351860331874010010100202002020035411110021109101001010000640241221993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  bics x0, x1, x2, lsr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522540516110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001111321316132998330000201003003630036300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001111321116332998330000201003003630036300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739182748520107202243023630035851120201100991002010010100001111322016132998230000201003003630036300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739182748520107202243023630035851120201100991002010010100001111322116132998330000201003003630036300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001111321316332998230000201003003630068300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001111321316312998230000201003003630036300683003630036
20204300352240006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001111321116302998230000201003003630036300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001111322316312998330000201003003630036300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739182748620107202243023630035851120201100991002010010100001111321116302998330000201003003630036300363003630036
20204300352250006110000298992530100301002010719562401492695530035300352739172748620107202243023630035851120201100991002010010100001111321316332998330000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522500611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270533552995930000200103003630036300363003630036
200243003522410611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270533552995930000200103003630036300363003630036
200243003522500611000029891253001030010200101956289492695530035300352739132749820010200203002030035852120021109102001010010001270533552995930000200103003630036300363003630036
200243003522500611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270533552995930000200103003630036300363003630036
200243003522400611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270533552995930000200103003630036300363003630036
200243003522400611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270533552995930000200103003630036300363003630036
200243003522500611000029891253001030010200101956289492695530035300802739132749820010200203002030035851120021109102001010010001270533542995930000200103003630036300363003630036
200243003522400611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270433652995930000200103003630036300363003630036
200243003522500611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270533542995930000200103003630036300363003630036
200243003522500611000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010001270533562995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  bics x0, x1, x2, lsr #17
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250000000611000029899253018830100201071956240149269553003530035273918274852010720224302363003585112020110099100201001010000000111131901602998330000201003003630036300363003630036
20204300352250000000611000029899253010030100201071956240149269553006730035273918274852010720224302363017285112020110099100201001010000000111131901602998230000201003003630036300363003630173
202043003522500000006110000298992530100301002010719562401492695530035300352739110274862010720224302363008185112020110099100201001010000000111132001602998230000201003003630036300363003630036
20204300352250000000611000029899253010030100201071956240149269553003530035273918274852010720224302363003585112020110099100201001010000200111131901602998330000201003003630036301723003630036
20204300352240000000611000029899253010030100201071956240149269553003530035273918274862010720224302363003585112020110099100201001010000000111132001602998230000201003003630036300363003630036
20204300352250000000611000029899253010030100201071956240149269553003530035273918274852010720224302363003585112020110099100201001010000000111131901602998230000201003003630036300363003630036
20204300352250000000841000029899253010030100201071956240149269553021530035273917274862010720224302363003585112020110099100201001010000000111131901602998230000201003003630036300363003630036
20204300352250000000611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010000000111131901602998330000201003003630036300363003630036
20204300352240000000611002429899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010000000111131901602998230000201003003630036300363003630036
20204300352240010000611000029899253019230100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010000000111132001602998330000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522500611000029891253001030010200101956289149269553003530035273913274982001020020300203003585112002110910200101001000151270233222995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904926955300353003527391327522200102002030020300358511200211091020010100100001270233222995930000200103003630036300363003630036
20024300352250061100002989133300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270233222995930000200103003630036300363003630036
20024300352250161100002989125300103001020010195628904926955300353003527403327498200102002030020300358511200211091020010100100001270233232995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270233222995930000200103003630036300363003630036
200243003522400611000029891253001030010200101956289049269553003530035273913274982001020020300203003585112002110910200101001000271270233232995930000200103003630036300363003630036
20024300352250061100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100031270233222999330000200103003630036300363003630036
20024300352250061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100100001270233222995930000200103003630036300363003630036
20024300352250161100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270233232995930000200103003630036300363003630036
200243003522500441100002989125300103001020010195628904926955300353003527391327498200102002030020300358511200211091020010100100001270233242995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  bics x0, x8, x9, lsr #17
  bics x1, x8, x9, lsr #17
  bics x2, x8, x9, lsr #17
  bics x3, x8, x9, lsr #17
  bics x4, x8, x9, lsr #17
  bics x5, x8, x9, lsr #17
  bics x6, x8, x9, lsr #17
  bics x7, x8, x9, lsr #17
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045344840100000218800134879128160137160137801763441890149503345341453414433453024843355801768028816037653414391180201100991008010010000000011151241161153411160037801005345753415534155341553415
8020453413400000002880013487912816013716013780176344189014950334534145341443345302484335580176802881603765341439118020110099100801001000000198011151231161153411160037801005341553415534155341553415
80204534144000000069380013487912916013716013780176344189004950334534145341443345302484335580176802881603765341439118020110099100801001000000222011151241161153411160037801005341553415534145341553414
8020453414400000002880013487912916013716013780176344189014950334534145341343345290984335580176802881603765341439118020110099100801001000000222011151421161153411160037801005341553415534155341553415
80204534144000000028800134879129160137160137801763441890149503305341053410432982909343360801008020016020053410391180201100991008010010000006000051102242253390160000801005341153411534115341153411
8020453410400000006180000487412516010016010080100344000514950330534105341043298302434336080100802001602005341039118020110099100801001000000216000051102242253390160000801005341153411534115341153411
8020453410400000006180000487412516010016010080100344000514950330534105341043298290934336080100802001602005341039118020110099100801001000000240000051102242253390160000801005341153411534115341153411
802055341040000000618000048741251601001601008010034400051495033053410534104329830243433608010080200160200534103911802011009910080100100000015000051102242253390160000801005341153411534115341153411
8020453410400000006180000487412516010016010080100344000514950330534105341043298290934336080100802001602005341039118020110099100801001000000192000051102242253390160000801005341153411534115341153411
8020453410400000006180000487412516010016010080100344000514950330534105341043298290934336080100802001602005341039118020110099100801001000000231000051102242253390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acl1d cache miss ld nonspec (bf)branch mispred nonspec (cb)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? int retires (ef)f5f6f7f8fd
8002453400400000618000047946251600101601028011034381301495030053380533804329032513433528001080020160020533803911800211091080010100006005020072435533601600000800105338153381533815338153381
8002453380400001261800004794625160010160010800103438130149503005338053380432902936343352800108002016002053380391180021109108001010010147005020052453533601600000800105338153381533815338153381
800245338039900061800004794625160010160010800103438130149503005338053380432902749343352800108002016002053380391180021109108001010000204005020032435533601600000800105338153381533815338153381
8002453380399000618000047946251600101600108001034381301495030053380533804329029363433528001080020160020533803911800211091080010100000005020132435533601600000800105338153381533815338153381
800245338040000061800004794625160010160010800103438130149503005338053380432902936343376800108002016002053380391180021109108001010000195005020052453534061600000800105338153381533815338153381
8002453380400000618000047946251600101600108001034381301495030053380534374329032513433528001080020160020533803911800211091080010100009005020032435533601600000800105338153381533815338153381
800245338040000061800004794625160010160010801123438130149509845372753380432902840364377981125812451629265338039118002110910800101000421969805020044053533601600000800105338153381533815338153381
800245338040000061800004794625160010160010800103438130149503005338053380432902936343352800108002016002053380391180021109108001010000210005020032435533601600000800105338153381533815338153381
800245338040000126180000479462516001016001080010343813014950300533805338043290325134335280010800201600205338039118002110910800101000069015020033135533601600000800105338153381533815338153381
800245338040010061800004794625160010160010800103438130149503005338053380432902749343352800108002016002053380391180021109108001010000231005020052454533601600000800105338153381533815338153381