Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (shifted immediate, 32-bit)

Test 1: uops

Code:

  sub w0, w0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103570618622510001000100016916110351035728386810001000100010354111100110000073141219371000100010361036103610361036
10041035733298622510001000100016916110351035728386810001000100010354111100110000073241129371000100010361036103610361036
1004103570618622510001000100016916010351035728386810001000100010354111100110000073241229371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073241129371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000100010354111100110000073241129371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073141229371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000100010354111100110000073241119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000100010354111100110000073241129371000100010361036103610361036
1004103580908622510001000100016916010351035728386810001000100010354111100110000073241129371000100010361036103610361036
1004103580618622510001000100016916110351035728386810001000100010354111100110000073241229371000100010361036103610361036

Test 2: Latency 1->2

Code:

  sub w0, w0, #3, lsl #12
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357606198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000671013711994110000101001003610036100361003610036
10204100357506198772510100101001010090723496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575061987725101001010010100886644969551003510035858038722101001020010200100354111102011009910010100100026071013711994110000101001003610036100361003610036
10204100357606198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000371013711994110000101001003610036100361003610036
102041003575061987725101001010010100886644969551003510035858038722101001020010200100354111102011009910010100100027071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664497095100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
10204100357506198772510100101001010088664496955100351003585803872210100102001020010035411110201100991001010010000071013711994110000101001003610036100361003610036
102041003575061987725101001010010100886644969551003510035858038722101001020010200100354111102011009910010100100009371013711994110000101001003610036100361003610036
1020410035755161987725101001010010100886644969551003510035858038722101001020010200100354111102011009910010100100006371013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035750001000849863251001010010100108878449695501003510035860238740100101002010020100354121100211091010010100000000064064122994010000100101003610036100361003610036
100241003575000003606198632510010100101001088784496955010035100358602188740100101036710020100354111100211091010010100000000064024122997510022100101003610036100361003610082
100241003575000023007559863251001010032101638878449695501003510035860238740100101002010020100354111100211091010010100000100064024122994010000100101003610036100361008110036
100241003575000000108619863251001010010100108878449695501003510035860238740100101002010020100354111100211091010010104200000064024122994010000100101003610036100361003610036
1002410035750000015601039863251001010010100108878449695501003510035860238740100101002010020100354111100211091010010100000000064024122994010000100101003610036100361003610036
10024100357500000120619863251001010010100108878449695501003510035860238740100101002010020100354111100211091010010100000000064024122994010000100101003610036100361003610036
1002410035750000000829863251001010010100108878449695501003510035860238740100101002010020100354111100211091010010100000000064024122994010000100101003610036100361003610081
1002410035750000060619863251001010010100108878449695501003510035860238740100101002010020100354111100211091010010100000000064024122994010000100101003610036100361003610036
1002410035750000000619863251001010010100108878449695501003510035860238740100101002010020100354111100211091010010100000000064024122994010000100101003610036100361003610036
1002410035750000000619863251001010010100108878449695501003510035860238740100101002010020100354111100211091010010104000000064024122994010000100101003610036100361007910036

Test 3: throughput

Count: 8

Code:

  sub w0, w8, #3, lsl #12
  sub w1, w8, #3, lsl #12
  sub w2, w8, #3, lsl #12
  sub w3, w8, #3, lsl #12
  sub w4, w8, #3, lsl #12
  sub w5, w8, #3, lsl #12
  sub w6, w8, #3, lsl #12
  sub w7, w8, #3, lsl #12
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413413100102827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100000111511911601338780036801001339113391133911339113391
8020413390100002827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100000111511901601338780036801001339113391133911339113391
8020413390100032827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100009111511901601338780036801001339113391133911339113391
8020413390100002827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100000111511901601338780036801001339113391133911339113391
8020413390100002827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100000111511901601338780036801001339113391133911339113391
8020413390100002827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100003111511901601338780036801001339113391133911339113391
8020413390101002827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100010111511901601338780036801001339113391133911339113391
80204133901000028278013680136801484007100491031013390133903326633368014880264802641339039118020110099100801001000012111512001601338780036801001339113391133911339113391
80204133901010028278013680136801484007100491031013390133903326633368014880264802641339039118020110099100801001000021111511901601338780036801001339113391133911339113391
8020413390100002827801368013680148400710049103101339013390332663336801488026480264133903911802011009910080100100000111511901601338780036801001339113391133911339113391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800241337610000035258001080010800104000500491029101337113371333033348800108002080020133713911800211091080010100155021819661336880000800101337213372133721337213372
800241337110000935258001080010800104000500491029101337113371333033348800108002080020133713911800211091080010100665021519531336880000800101337213372133721337213372
8002413371100000352580010800108001040005004910291013371133713330243348800108002080020133713911800211091080010100305022319651336880000800101337213372133721337213372
800241337110000916125800108001080010400050049102910133711337133303334880010800208002013371391180021109108001010005022519561336880000800101337213372133721337213372
80024133711000007725800108001080010400050049102910133711337133303334880010800208002013371391180021109108001010035022519531336880126800101337213372133721337213372
80024133711000003525800108001080010400050049102910133711337133303334880146800208002013371391180021109108001010005020619531336880000800101337213372133721337213372
80024133711010003525800108001080010400050049102910133711337133303334880010800208002013371391180021109108001010005022519351336880000800101337213372133721337213372
80024133711000003525800108001080010400050049102910133711337133303334880010800208002013371391180021109108001010005021319451336880000800101337213372133721337213372
800241337110100035258001080010800104000500491029101337113371333033348801458002080020133713911800211091080010100665022519531336880000800101337213372133721337213372
80024133711000003525800108001080010400050049102910133711337133303334880010800208002013371391180021109108001010005021519631336880000800101337213372133721337213372