Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (sxth, 32-bit)

Test 1: uops

Code:

  adds w0, w0, w1, sxth
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035156606110001862252000200010001262350203520351729318661000100020002035411110011000004731431119202000100020362036203620362036
1004203515006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203516006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203516006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036
1004203515006110001862252000200010001262350203520351729318661000100020002035411110011000000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  adds w0, w0, w1, sxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150006611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035150000611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035150000611000019862252010020100101001305121491695520035200841858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035150000611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035150000611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035150010611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035150000611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111999620000101002003620036200362003620036
1020420035150000611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000727139111992220000101002003620036200362003620036
1020420035150000611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035149000611000019862252010020100101001305121491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010103640241221993020000100102003620036200362003620036
100242003515006311000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351490611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351500611000019862252001020010100101305229149169553200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036
10024200351503611000019862252001020010100101305229149169550200352003518603318740100101002020020200354111100211091010010100640241221993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  adds w0, w1, w0, sxth
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03091e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150006110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000147710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351490061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500961100001986225201002010010100130512114916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036
10204200351500061100001986225201002010010100130512104916955200352003518581318720101001020020200200354111102011009910010100100000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515000000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
1002420035150000000000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000048000640241221993020000100102003620036200362003620036
100242003515000000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
100242003514900000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
100242003515000000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
1002420035150000000000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000093000640241221993020000100102003620036200362003620036
100242003515000000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
100242003515000000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
100242003515010000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036
100242003515000000000061100001986225200102001010010130522949169552003520035186033187401001010020200202003541111002110910100101000000000640241221993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  adds w0, w1, w2, sxth
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000311113191162998330000201003003630068300363003630036
202043003522512611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010002111113200162998330000201003003630036300363003630036
20204300352250611000029899253010030100201071956240149269553003530035273918274852010720224302363003585112020110099100201001010003611113190162998330000201003003630036300363003630036
20204300352250611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010001811113200162998330000201003003630036300363003630036
2020430035225061100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000311113190162998230000201003003630036300363003630036
20204300352250611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010007811113200162998330000201003003630036300363003630036
2020430035225061100002989925301003010020107195624014926955300353003527391727486201072022430368300358511202011009910020100101000611113200162998330000201003003630036300363003630036
20204300352250611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010004211113190162998330000201003003630036300363003630036
20204300352250611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010007211113190162998230000201003003630036300363003630036
20204300352250611000029899253010030100201071956240149269553003530035273917274862010720224302363003585112020110099100201001010003611113190162998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522510100001671000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010005012711133872995930000200103003630036300363003630036
2002430035225101000011091000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010424108612716338102995930000200103003630036300363003630036
2002430035224101000016710000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100024312711133862995930000200103003630036300363003630036
2002430035225101000016710000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100041591271733862995930000200103003630036300363003630036
20024300352251010000167100002989125300103001020010195628949269553003530035273913274982001020020300203003585112002110910200101001000166127110339102995930000200103003630036300363003630036
2002430035225111000016710000298912530010300102001019562894926955300353008027391327498200102002030020300358511200211091020010100100007812711033682995930000200103008130036300363003630036
2002430035225101110611531000029891473001030010200861956289492695530081300352739132749820010201083002030035851120021109102001010010001961271113310102995930000200103003630036300363003630036
200243003522510100001671000029891253001030010200101956289492695530035300352739132749820010200203002030035851120021109102001010010000751271933592995930000200103003630036300363003630036
20024300352251010000167100002989125300103001020010195628949269553003530035273913274982001020020300203003585112002110910200101001000460127193310112995930000200103003630036300363003630036
200243003522510100033167100002989125300103001020010195628949269553003530035273913274982001020020300203003585112002110910200101001000189127193311102995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  adds w0, w1, w2, sxth
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250000000061100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101000200111131901602998230000201003003630036300363003630036
20204300352250000000061100002989925301003010020107195624014926955300353003527391827485201072022430236300358511202011009910020100101000203111131912402998330000201003012630128300823008230036
202043003522500001100611001229903473014630100201071956836049269553003530035273917274852010720224302363003585112020110099100201001010001084111132001602998230000201003003630036300363003630036
202043003522400000000611000029899253010030100201071956240149269553003530035273918274852010720224302363003585112020110099100201001010002709111132001602998230000201003003630036300363003630036
202043003522500000000611000029899253010030100201071956240049269553003530035273918274852010720224302363003585112020110099100201001010003003111131901602998330000201003003630036300363003630036
20204300352250000000061100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000140126111132001602998330000201003003630036300363003630036
202043012622500000000611000029899253010030100201071956240049269553003530035273918274852010720224302363003585112020110099100201001010002603111131901602998330000201003003630036300363003630036
202043003522500000000611000029899253010030100201071956240049269553003530035273917274862010720224302363003585112020110099100201001010005703111131901602998230000201003003630036300363003630036
202043003522500000000611000029899253010030100201071956240049269553003530035273918274852010720224302363003585112020110099100201001010002709111131901602998330000201003003630036300363003630036
202043003522500000000611000029899253010030100201071956240049269553003530035273917274862010720224302363003585112020110099100201001010003403111132001602998330000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010313001270533342995930000200103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955300353003527391327498200102002030020300358511200211091020010100103115001270533442995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562890492700130081300352739132749820010200203002030035851120021109102001010010260001270433442995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010303001270433442995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010266001270433542995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562891492695530035300352742432749820010200203002030035851120021109102001010010090001270433442995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010263001270433442995930000200103003630036300363003630036
200243012622506110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010243001270433442995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132752820010200203002030035851120021109102001010010306001270433442995930000200103003630036300363003630036
200243003522506110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010289001270433442995930000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  adds w0, w8, w9, sxth
  adds w1, w8, w9, sxth
  adds w2, w8, w9, sxth
  adds w3, w8, w9, sxth
  adds w4, w8, w9, sxth
  adds w5, w8, w9, sxth
  adds w6, w8, w9, sxth
  adds w7, w8, w9, sxth
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045344940002880013487912916013716013780176344189004950334534145341443345290984335580176802881603765341439118020110099100801001000011151240160053411160037801005341553415534155341553415
802045341440002880051487912916013716013780176344189004947310534145341343345302484335580176802881603765341439118020110099100801001000011151240160053411160037801005341553415534155341553415
802045341440002880013487912916013716013780176344189004950334534145341443345302484335580176802881603765341439118020110099100801001000011151240160053411160037801005341553415534155341553415
802045341440002880013487912916013716013780176344189014950334534145341443345302484335580176802881603765341439118020110099100801001000011151240160053411160037801005341453415534155364353415
802045341440002880013487912916013716013780176344189014950334534145341443345290984335580176802881603765341439118020110099100801001000000051101241153390160000801005341153411534115341153411
802045341040006180000487412516010016010080100344000514947312534105341043298302434336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411
802045341040006180000487412516010016010080100344000514950330534105341043298302434336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411
802045341040006180000487412516010016010080100344000504950330534105341043298302434336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411
802045341040006180000487412516010016010080100344000514950330534105341043298290934336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115363853411
802045341040006180000487412516010016010080100344000514950330534105341043298302434336080100802001602005341039118020110099100801001000000051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)031e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024534013990006180000479463016001016001080010343813004950300533805338043290293634335280010800201600205338039118002110910800101003502002244253360160000800105363253381533815338153381
80024534374000006180000479462516001016001080010343813004950300533805338043290325134335280010800201600205338039118002110910800101000502004244253360160000800105338153381533815338153381
80024533804000006180000479462516001016001080010343813014950300533805338043290325134335280010800201600205338039118002110910800101000502002244253360160000800105338153381533815338153381
80024533804000006180000479462516001016001080010343813004950300533805338043290293634335280010800201600205338039118002110910800101000502002244353360160000800105338153381533815338153381
80024533803990006180000479462516001016001080010343813004950300533805338443290325134335280010800201600205338039118002110910800101000502004244453360160000800105338153381533815338153381
80024533804000006180000479462516001016001080010343813014950300533805338043290274934335280010800201600205338039118002110910800101000502004244453360160000800105338153381533815338153381
800245338040000072680000479462516001016001080010343813004950300533805338043290325134335280010800201600205338039118002110910800101000502002244253360160000800105338153381533815338153381
80024533804000006180000479462516001016001080010343813004950300533805338043290293634335280010800201600205338039118002110910800101000502004244253360160000800105338153381533815338153381
800245338040000061800004794644160010160010800103438130149503005338053380432902749343352800108002016002053380391180022109108001010323502004244253360160000800105338153381533815338153381
80024533804000006180000479462516001016001080010343813004950300533805338043290274934335280010800201600205338039118002110910800101000502004242453360160000800105338153381533815338153381