Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BICS (register, lsl, 32-bit)

Test 1: uops

Code:

  bics w0, w0, w1, lsl #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150976100018622520002000100012623502035203517293186610001000200020354111100110000731431119202000100020362036203620362036
1004203515016261100018622520002000100012623502035203517293186610001000200020354111100110000731431119202000100020362036203620362036
1004203515011761100018622520002000100012623512035203517293186610001000200020354111100110000731431119202000100020362036203620362036
10042035150061100018622520002000100012623502035203517293186610001000200020354111100110000731431119202000100020362036203620362036
100420351509061100018622520002000100012623502035203517293186610001000200020354111100110000731431119522000100020362036203620362036
10042035150061100018622520002000100012623502035203517293186610001000200020354111100110000731431119202000100020362036203620362036
10042035150061100018622520002000100012623502035203517293189910001000200020354111100110000731431119202000100020362036203620362036
10042035150061100018622520002000100012623502035203517293186610001000200020354111100110000731431119202000100020362036203620362036
10042035150061100018622520002000100012623502035203517293186610001000200020354111100110000731431119202000100020362036203620362036
10042035150061100018622520002000100012623502035203517293186610001000200020354111100110000731431119202000100020362036203620362036

Test 2: Latency 1->2

Code:

  bics w0, w0, w1, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515006110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006110000198623420100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000710139111999420000101002003620036200362003620036
1020420035150034110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010060710139111992220000101002003620036200362003620036
1020420035150063110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515008210000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036
102042003515006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640741331993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640341331993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202019820035411110021109101001010000640341331993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640341331993020000100102003620036200362003620036
10024200351500001031000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640317331993020000100102003620036200362003620036
10024200351500002511000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640341331993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640341331993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640341331993020000100102003620036200362003620036
10024200351500001891000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640341331993020000100102003620036200362003620036
1002420035150000611000019862252001020010100101305229491695520035200351860331874010010100202002020035411110021109101001010000640341331993020000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  bics w0, w1, w0, lsl #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035150003906110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620072200362003620036
1020420035150002706110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
1020420035150001206110000198622520100201001010013051211491695520035200351858131872010100102002020020126411110201100991001010010000000710139111992220000101002003620036200362003620036
102042003515000306110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010003000710139111992220000101002003620036200362003620036
1020420035150002406110000198622520126201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051211491704620035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000000710139111992220000101002003620036200362003620036
102042003515000006110000198622520100201001010013051211491695520035200351858131872010100102002020020035411110201100991001010010000030710139111992220000101002003620036200362003620036
1020420035149001206110000198622520100201001010013051210491695520035200351858131872010100102002020020035411110201100991001010010000002710139111992220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351500000000000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000000640441651993020000100102003620036200362003620036
10024200351500000000000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000000640641651993020000100102003620036200362003620036
100242003515000000000001661000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000000640541551993020000100102003620036200362003620036
100242003515000000000001031000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000000000640541541993020000100102003620036200362003620036
100242003515000000000005361000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000000000640641661993020000100102003620036200362003620036
10024200351500000000000611000019862252001020010100101305229149169552003520035186033187401001010020200202003541111002110910100101000000000640541441993020000100102003620036200362003620036
10024200351500000000000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000000640641561993020000100102003620036200362003620036
10024200351500000000000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000000640441541993020000100102003620036200362003620036
10024200351500000000000611000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000000640541551993020000100102003620036200362003620036
100242003515000000000002931000019862252001020010100101305229049169552003520035186033187401001010020200202003541111002110910100101000000000640541551993020000100102003620036200362003620036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  bics w0, w1, w2, lsl #17
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522533961100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101000011113201162998230000201003003630036300363003630036
202043003522532761100002989925301003010020107195624014926955300353003527391827486201072022430236300358511202011009910020100101000011113190162998330000201003003630036300363003630036
202043003522513261100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101000011113200162998230000201003003630036300363003630036
202043003522534561100002989925301003010020107195624004926955300353003527391827485201072022430236300358511202011009910020100101000011113200162998230000201003003630036300363003630036
202043003522533361100002989925301003010020107195624014926955300353003527391727485201072022430236300358511202011009910020100101000011113200162998230000201003003630036300363003630036
2020430035224061100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101001311113200162998230000201003003630036300363003630036
202043003522532461100002989925301003010020107195624004926955300353003527391827486201072022430236300358511202011009910020100101000011113200162998230000201003003630036300363003630036
202043003522438161100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000011113190162998330000201003003630036300363003630036
202043003522542961100002989925301003010020107195624004926955300353003527391727486201072022430236300358511202011009910020100101000011113190162998230000201003003630036300363003630036
202043003522540261100002989925301003010020107195624014926955300353003527391727486201072022430236300358511202011009910020100101000011113200162998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352240000813018010000298912530010300102008619562890492695530035300352739132749820010200203002030035851120021109102001010010000000001270233112995930000200103003630036300363003630036
2002430035224000032706110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036
20024300352250000008410000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000000001270133122995930000200103003630036300363003630036
2002430035225000037806110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036
2002430035225000038706110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036
20024300352250000366061100002989125300103001020010195628904926955300353003527391122749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036
2002430035225000042906110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036
2002430035225000056106110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036
2002430035225000045906110000298912530010300102001019562891492695530035300352739132749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036
2002430035225000040506110000298912530010300102001019562890492695530035300352739132749820010200203002030035851120021109102001010010000000001270133112995930000200103003630036300363003630036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  bics w0, w1, w2, lsl #17
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)09191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250004206110000298992530100301002010719562401549269553003530035273918274852010720224302363003585112020110099100201001010000011113195111602998230000201003003630036300363017230036
2020430035225000645012410000298992530100301002010719562401049269553003530035273918275392010720224302363003585112020110099100201001010000011113190001602998230000201003003630036300363003630036
202043003522500042906110000298992530100301002010719562401049269553003530035273917274862010720224302363003585112020110099100201001010000011113195101603006830000201003003630036300363003630036
202043003522501033061100002989925301003010020107195624015492695530035300352739110275382010720224302363003585112020110099100201001010001301611113535001602998330000201003003630036300363003630036
20204300352250005106110000298992530100301002010719562400549269553003530035273918274852010720224302363003585112020110099100201001010000311113190001602998230000201003012630036300363003630036
2020430035225001171021010000298992530100301002010719562401049269553003530218273917274852010720224302363003585112020110099100201001010000011113205101602998330000201003003630036300363003630036
20204300352240006006110000298992530100301002010719562400549269553003530035273918274852010720320302363003585112020110099100201001010000011113190001602998230000201003003630036300363003630036
202043003522400054033910000298992530100301002010719562401549269553003530035273918274852010720224302363003585112020110099100201001010000011113195101602998330000201003003630036300363003630036
20204300352250003606110000298992530100301002010719562400549269553003530035273918274852010720224302363003585112020110099100201001010000011113195101602998230000201003003630036300363003630036
20204300352240004808210000298992530100301002010719562401049269553003530035274267274862010720224302363003585112020110099100201001010000011113195101602998230000201003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522500546110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001272733942995930000200103003630036300363003630036
200243003522500156110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001272633952995930000200103003630036300363003630036
200243003522500486110000298912530010300102001019562894926955300353003527391327498200102002030020300358521200211091020010100100001272933882995930000200103003630036300363003630036
200243003522500126110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001272733852995930000200103003630036300363003630036
200243003522500156110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001270933952995930000200103003630036300363003630036
200243003522500276110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001272933992995930000200103003630036300363003630036
200243003522500156110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001272933592995930000200103003630036300363003630036
200243003522500306110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001270933962995930000200103003630036300363003630036
2002430035225001561100002989125300103001020010195628949269553003530035273913274982001020020300203003585112002110910200101001000012725331052995930000200103003630036300363003630036
200243003522500216110000298912530010300102001019562894926955300353003527391327498200102002030020300358511200211091020010100100001272933873002530000200103003630036300363003630036

Test 6: throughput

Count: 8

Code:

  bics w0, w8, w9, lsl #17
  bics w1, w8, w9, lsl #17
  bics w2, w8, w9, lsl #17
  bics w3, w8, w9, lsl #17
  bics w4, w8, w9, lsl #17
  bics w5, w8, w9, lsl #17
  bics w6, w8, w9, lsl #17
  bics w7, w8, w9, lsl #17
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03l1i tlb fill (04)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045344940010618000048741251601001601008010034400051495033053410534104329829093433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601008010034400051495033053410534104329830243433608010080200160200534108411802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601008010034400050495033053410534104329830243433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601008010034400050495033053410534104329829093433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040009618000048741251601001601008020234400050495033053410534104329829093433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601008010034425851495033053410534104329830243433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601008010034400050495033053410534104329830243433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601008010034400051495033053410534104329829093433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601008010034400051495033053410534104329830243433608010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411
802045341040000618000048741251601001601898010034400050495033053410534104329830243433848010080200160200534103911802011009910080100100051101241153390160000801005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024534014000104261800004794625160010160097800103438130149503005338053380432903251343352800108002016002053380391180021109108001010000000050200112410753360160000800105338153381533815338153381
8002453380399000061800004794625160010160010800103438130149503005338053380432902936343352800108002016002053380391180021109108001010000000050200102481053360160000800105338153381533815338153381
80024533804000000726800004794625160010160010800103438130049503005338053380432903251343352800108002016002053380391180021109108001010000000050200102471053360160000800105338153381533815338153381
800245338040000006180000479462516001016001080010343813014950300533805338043290293634335280010800201600205338039118002110910800101000000005020072481053360160000800105338153381533815338153381
800245338039900006180000479462516001016001080010343813014950300533805338043290274934335280010800201600205338039118002110910800101000000005020072410753360160000800105338153381533815338153381
800245338040000206180000479462516001016001080010343813014950300533805338043290274934335280010800201600205338039118002110910800101000003005020072410753360160000800105338153381533815338153381
800245338040000006180000479462516001016001080010343813014950300533805338043290293634335280010800201600205338039118002110910800101000020005020072471053360160000800105338153381533815338153381
80024533803990000618000047946251600101600108001034381301495030053380533804329027493433528001080020160020533803911800211091080010100000000502001024101053360160000800105338153381533815338153381
800245338040000006180000479462516001016001080010343813014950300533805338043290274934335280010800201600205338039118002110910800101000000005020072471053360160000800105338153381533815338153381
80024533804000000618000047946251600101600108001034381301495030053380533804329032513433528001080020160020533803911800211091080010100000000502001024101053360160000800105338153381533815338153381