Firestorm: MRS (FPSR) measurements

Code:

  mrs x0, fpsr

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	10027	77	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028
1004	10027	78	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028
1004	10027	78	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	0	75	2	134	2	2	10024	1000	1000	10028	10028	10100	10064	10028
1004	10027	78	1	0	1	0	12	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028
1004	10027	78	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	3	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028
1004	10027	78	1	0	1	0	12	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028
1004	10027	78	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028
1004	10027	78	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	1	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10102
1004	10027	77	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	0	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028
1004	10027	78	1	0	1	0	0	0	1	10012	26	1000	1000	49	6947	10027	10027	9672	3	9767	10027	1393	1	1	1001	0	1	0	75	2	134	2	2	10024	1000	1000	10028	10028	10028	10028	10028

Count: 8

Code:

  mrs x0, fpsr
  mrs x1, fpsr
  mrs x2, fpsr
  mrs x3, fpsr
  mrs x4, fpsr
  mrs x5, fpsr
  mrs x6, fpsr
  mrs x7, fpsr

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 10.0003

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	ec	? int retires (ef)	f5	f6	f7	f8	fd
80204	800027	6202	0	0	0	0	800012	38	80100	80100	100	500	0	49	796947	0	800027	800027	789782	3	789877	100	200	200	800027	1393	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	0	0	0	5110	2	124	2	2	800024	80002	0	0	80100	800028	800028	800028	800028	800029
80204	800027	6202	0	0	0	0	800012	26	80100	80100	100	500	0	49	808107	0	800063	800027	789782	3	789877	100	200	200	800027	1393	2	1	80201	100	99	100	100	100	4	4	0	0	4	0	28887	0	0	0	0	0	5122	2	124	1	3	800047	80000	0	0	80100	800028	800028	800028	800028	800028
80204	800027	5993	0	0	0	0	800012	26	80100	80100	100	500	0	49	796947	0	800027	800027	789782	3	789877	100	200	202	800027	1393	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	0	0	0	5110	2	124	2	2	800024	80000	0	0	80100	800028	800051	800028	800028	800028
80204	800027	5992	0	0	0	0	800012	26	80100	80100	100	500	0	49	796948	0	800073	800027	789782	3	789877	100	200	200	800027	1393	1	1	80201	100	99	100	100	100	0	0	0	0	1	0	0	0	0	0	0	0	5110	2	124	2	2	800024	80000	0	0	80100	800028	800028	800028	800028	800028
80204	800173	5995	1	0	12	0	800012	26	80100	80100	109	500	0	49	796947	0	800027	800027	789782	3	789877	100	200	200	800027	1393	2	1	80202	100	99	100	100	100	0	0	0	0	0	0	0	0	0	0	0	0	5110	2	124	2	2	800024	80000	0	0	80100	800028	800028	800028	800028	800028
80204	800027	5993	0	0	0	0	800012	26	80100	80100	100	500	0	49	796947	0	800027	800027	789782	3	789877	101	200	200	800027	1393	1	1	80201	100	99	100	100	100	0	2	3	0	0	2	0	0	2	0	0	0	5875	2	124	2	2	800025	80004	0	0	80100	800028	800028	800028	800028	800049
80204	800027	5992	0	0	0	0	800036	26	80100	80100	100	650	0	98	796947	0	800028	800027	789782	3	789877	100	200	200	800027	1393	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	3	0	0	0	0	0	5110	2	124	2	2	800024	80000	0	0	80100	800028	800028	800028	800028	800028
80205	800027	5992	0	0	0	0	800012	26	80100	80100	100	500	1	49	796947	0	800027	800027	789782	3	789877	100	200	200	800027	1393	1	1	80201	100	99	100	100	100	0	0	0	0	1	0	0	0	0	0	0	0	5110	2	124	2	2	800024	80000	0	0	80100	800028	800029	800028	800028	800028
80204	800176	5993	0	0	177	0	800012	38	80100	80100	100	500	0	98	796947	0	800027	800027	789782	3	789877	100	200	200	800027	1393	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	0	0	0	5110	0	124	0	2	800024	80000	0	0	80100	800028	800028	800028	800028	800028
80204	800027	5992	0	0	0	0	800012	26	80100	80100	100	500	0	49	796947	0	800027	800027	789783	3	789877	100	200	200	800027	1393	1	1	80201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	0	1	0	5110	2	124	2	0	800024	80000	0	0	80100	800028	800028	800028	800028	800029

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 10.0003

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	800027	6295	0	0	0	0	0	12	0	0	800012	26	80010	80010	10	50	1	49	796947	0	800027	800027	789804	3	789899	10	20	20	800027	1393	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	0	5020	0	0	0	16	124	0	0	9	7	800024	80000	0	0	0	80010	800028	800028	800028	800028	800028
80024	800027	6201	0	0	0	0	0	0	0	0	800012	26	80011	80010	10	50	1	49	796947	0	800027	800027	789804	3	789899	10	20	20	800434	1393	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	1	0	0	5020	0	1	0	8	124	0	0	10	7	800024	80000	0	0	0	80010	800029	800028	800028	800028	800028
80024	800027	6201	0	0	0	2	6	396	968	0	800012	26	80010	80010	10	50	0	49	796947	3	800027	800027	789804	3	789899	10	20	20	800027	1393	1	1	80021	10	9	10	10	10	0	0	0	1	0	0	0	0	0	5020	0	0	0	9	124	0	0	6	9	800024	80000	0	0	0	80010	800028	800028	800028	800028	800028
80024	800027	6202	0	0	0	0	0	0	0	0	800012	26	80011	80010	10	50	0	49	796947	0	800027	800027	789804	3	789899	10	20	20	800027	1393	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	2	0	0	5020	0	0	0	8	124	0	0	6	8	800024	80000	0	0	0	80010	800028	800028	800028	800028	800028
80024	800027	6202	0	0	0	0	0	0	0	0	800012	26	80010	80010	10	50	1	49	796947	0	800027	800027	789804	3	789899	10	20	20	800027	1393	1	1	80021	10	9	10	10	10	0	0	0	0	57	0	0	0	0	5020	0	0	0	5	124	0	0	6	10	800024	80000	0	3	1	80010	800028	800028	800028	800052	800028
80024	800027	6201	0	0	0	0	0	0	0	1	800012	26	80010	80010	10	50	1	49	796947	0	800027	800027	789804	3	789899	10	20	20	800027	1393	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	0	5020	0	0	0	7	124	0	0	9	6	800024	80000	0	0	0	80010	800028	800028	800028	800028	800028
80024	800027	6202	0	0	0	0	0	0	0	0	800012	26	80010	80010	10	50	1	49	796947	0	800027	800027	789804	3	789899	10	20	20	800027	2786	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	1	1	0	5020	0	0	0	10	124	0	0	9	10	800024	80000	0	0	0	80010	800028	800028	800028	800028	800028
80024	800027	5993	0	0	0	0	0	0	0	0	800012	26	80010	80010	10	50	0	49	796947	3	800027	800027	789804	3	789899	10	20	20	800027	1393	1	1	80022	10	9	10	10	10	0	0	0	0	0	0	0	0	0	5020	0	0	0	10	124	0	0	7	10	800024	80000	0	0	0	80010	800028	800028	800028	800028	800028
80024	800027	5993	0	0	0	0	0	0	0	0	800012	26	80010	80012	10	56	1	49	796947	0	800027	800027	789804	3	789899	10	20	20	800027	1393	1	1	80021	10	9	10	10	10	0	2	0	3	0	0	0	0	0	5020	0	0	0	5	180	0	0	10	9	800024	80000	0	0	0	80010	800028	800028	800028	800051	800028
80024	800027	5992	0	0	0	0	0	1062	88	0	800049	26	80011	80010	10	50	1	49	796983	0	800100	800027	789839	8	789899	10	20	20	800027	1393	2	1	80021	10	9	10	10	10	2	0	0	0	0	0	0	0	0	5020	0	0	0	8	124	0	0	9	9	800024	80000	0	0	0	80010	800028	800028	800028	800028	800028

MRS (FPSR)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations