Firestorm: LDR (register, lsl, 32-bit) measurements

Code:

  ldr w0, [x6, x7, lsl #2]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	1	66	0	0	1	383	2	1	7	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	10	7	1000	395	399	399	399	399
1004	398	3	0	44	0	0	1	383	2	1	7	19	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	2000	399	79	1	1	1001	1000	1000	1000	43	1038	0	39	1038	6	1	39	44	73	2	16	1	1	486	14	14	7	1000	404	399	401	399	395
1004	398	3	0	44	1	0	1	383	2	1	7	19	25	1000	1000	1000	15274	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1039	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	395	399	401	399
1004	402	3	0	44	0	0	1	379	2	1	7	19	25	1000	1000	1000	15267	0	398	398	217	3	257	1000	1000	2000	399	79	1	1	1001	1000	1000	1000	43	1038	0	39	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	401	400	396	399
1004	398	3	0	45	0	0	1	383	2	1	7	19	25	1000	1000	1000	15274	1	398	400	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	44	1038	0	39	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	44	0	0	1	383	2	1	9	19	25	1000	1000	1000	15274	0	398	398	221	3	256	1000	1000	2000	394	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	2	2	396	14	14	7	1000	400	402	395	399	399
1004	398	3	0	53	0	0	1	383	2	1	7	19	25	1000	1000	1000	15274	0	398	399	221	3	252	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	10	14	7	1000	399	399	399	399	399
1004	398	3	0	44	0	0	1	383	2	1	7	19	25	1000	1000	1000	15274	1	398	399	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	44	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	395	399	399
1004	394	3	0	44	0	0	1	379	2	1	7	19	25	1000	1000	1000	15274	0	399	398	221	3	255	1000	1000	2000	398	77	1	1	1001	1000	1000	1000	44	1038	0	38	1038	6	1	39	44	75	1	16	1	1	395	10	10	7	1000	399	405	399	412	399
1004	401	2	0	44	1	0	1	383	2	1	7	16	25	1000	1000	1000	15187	0	398	398	221	3	252	1000	1000	2000	399	79	1	1	1001	1000	1000	1000	44	1038	0	38	1038	6	1	38	43	73	1	16	1	1	395	14	14	7	1000	399	400	400	399	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	0	0	1	0	0	0	70035	69735	59706	25	40104	30103	10001	30100	10000	616005	3342062	0	49	66970	0	70050	70050	64646	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	2	71	2	2	69813	30000	9	6	9	10000	30100	70051	70048	70048	70051	70051
40204	70050	525	0	0	1	0	0	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616005	3342062	0	49	66970	0	70050	70050	64649	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	2	71	2	3	70130	30003	0	6	9	10000	30100	70048	70048	70036	70051	70051
40204	70050	525	0	0	1	0	0	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616005	3342062	0	49	66955	0	70050	70050	64646	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	2	71	2	2	69810	30003	9	9	9	10000	30100	70051	70051	70051	70051	70048
40204	70050	525	0	0	1	0	0	0	70032	69781	59709	25	40104	30100	10001	30100	10000	616015	3342062	0	49	66970	0	70050	70047	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	26	0	30	10000	1	1	0	2610	2	71	2	2	69813	30003	6	0	0	10000	30100	70036	70051	70048	70048	70051
40204	70050	524	0	0	1	0	0	0	70032	69781	59706	25	40104	30103	10001	30100	10000	616005	3342062	0	49	66967	0	70047	70050	64631	3	64950	40100	30200	10000	60200	20000	70090	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	1	0	2610	2	71	2	2	69813	30003	6	6	9	10000	30100	70051	70048	70056	70051	70051
40204	70047	525	0	0	1	0	0	0	70032	69743	59695	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66970	0	70035	70047	64643	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	2	71	2	2	69810	30003	6	0	6	10000	30100	70048	70048	70048	70051	70036
40204	70035	525	1	0	1	0	0	0	70020	69764	59706	25	40104	30103	10001	30100	10000	616005	3342062	0	49	66970	0	70047	70047	64643	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	2	71	2	2	69810	30000	9	9	9	10000	30100	70048	70048	70048	70051	70051
40204	70035	524	1	0	1	0	0	0	70020	69781	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66955	0	70047	70047	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	2610	2	71	2	2	69810	30003	6	6	9	10000	30100	70051	70048	70036	70048	70048
40204	70050	524	0	0	1	0	1	0	70032	69735	59709	25	40104	30103	10001	30100	10000	616175	3342062	0	49	66967	0	70050	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	2610	2	71	2	2	69810	30003	9	6	6	10000	30100	70051	70048	70048	70048	70048
40204	70047	525	1	1	1	0	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	0	49	66967	0	70047	70047	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	2	71	2	2	69813	30003	6	6	9	10000	30100	70048	70051	70051	70051	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	1	1	0	1	1	0	2	1	0	1	70026	69777	59701	25	40018	30013	10002	30010	10000	617036	3342494	1	49	66961	0	70056	70041	64674	0	3	64966	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	3	1	10003	0	0	1	10000	1	1	1	1	0	0	0	2520	4	71	2	4	69804	30003	0	0	9	10000	30010	70057	70057	70042	70042	70057
40024	70041	525	1	1	1	0	1	0	2	1	0	1	70041	69702	59712	25	40018	30016	10002	30161	10000	617009	3342494	0	49	66961	0	70056	70056	64671	0	3	64978	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	1	1	10000	1	1	1	1	1	0	0	2520	2	71	3	4	69804	30006	0	0	0	10000	30010	70057	70115	70042	70062	70057
40024	70053	524	1	0	1	0	0	0	2	0	0	0	70041	69780	59701	25	40014	30013	10002	30010	10000	617036	3341769	1	49	66973	0	70056	70053	64674	0	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10001	0	1	1	10000	0	1	1	1	1	0	0	2520	2	71	4	2	69816	30006	6	6	0	10000	30010	70057	70042	70057	70057	70057
40024	70053	525	1	1	1	0	0	0	2	0	0	0	70026	69702	59702	25	40014	30016	10002	30010	10000	617036	3342350	0	49	66976	0	70056	70056	64674	0	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10003	0	2	1	10000	1	1	0	1	2	0	0	2520	3	71	2	2	69819	30006	9	9	0	10000	30010	70057	70057	70042	70057	70057
40024	70041	525	1	0	1	0	0	0	2	0	0	0	70041	69780	59715	25	40018	30016	10002	30010	10000	617036	3341769	1	49	66961	0	70056	70056	64730	0	3	64978	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10002	0	0	1	10000	1	1	0	1	0	0	0	2520	2	71	4	2	69804	30006	9	6	9	10000	30010	70140	70057	70057	70057	70057
40024	70056	524	1	1	0	0	0	0	2	1	0	0	70026	69780	59701	25	40018	30016	10002	30010	10000	617036	3342350	0	49	66976	0	70056	70053	64659	0	3	64978	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10001	0	1	1	10000	1	1	1	1	1	0	0	2520	2	71	3	4	69816	30006	0	0	9	10000	30010	70057	70057	70042	70057	70057
40024	70056	525	1	1	1	0	1	0	1	0	0	0	70041	69780	59701	25	40018	30016	10002	30010	10000	617036	3341769	0	49	66961	0	70056	70053	64674	0	3	64981	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	0	10002	0	0	1	10000	1	1	1	1	1	0	0	2520	3	71	5	3	69819	30006	9	6	9	10000	30010	70042	70054	70042	70054	70057
40024	70056	525	1	1	1	0	0	0	2	1	0	1	70026	69702	59747	25	40018	30016	10002	30010	10000	617036	3341769	0	49	66976	0	70056	70056	64674	0	3	64966	40010	30020	10000	60020	20000	70056	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	2	1	10000	0	1	1	1	0	0	0	2520	4	71	2	2	69804	30003	6	0	9	10000	30010	70057	70057	70057	70042	70042
40024	70053	525	1	1	0	1	1	0	2	0	0	0	70026	69702	59715	25	40018	30016	10001	30010	10000	617009	3342494	0	49	66976	0	70056	70041	64674	0	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10003	0	3	1	10000	0	1	1	1	0	0	0	2520	3	71	2	2	69804	30006	0	9	0	10000	30010	70042	70042	70054	70042	70054
40024	70056	525	1	1	1	0	1	0	1	1	0	0	70041	69702	59712	25	40014	30016	10002	30010	10000	617036	3342494	1	49	66976	0	70053	70053	64674	0	3	64981	40010	30020	10000	60020	20000	70058	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	1	1	10000	1	1	1	1	1	0	0	2555	2	71	2	2	69819	30006	9	0	9	10000	30010	70057	70042	70057	70057	70042

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr w0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	1	1	1	1	1	2	0	0	1	70038	69784	59701	25	40108	30106	10004	30124	10000	616032	3342350	1	49	66973	70053	70041	64649	3	64944	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	83	2	1	10000	1	1	1	1	1	2611	3	71	3	2	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70138
40204	70053	525	1	1	1	0	0	2	1	0	1	70038	69784	59715	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	77	1	1	10000	1	1	0	1	1	2611	2	71	3	3	69816	30006	6	6	6	10000	30100	70054	70057	70054	70054	70149
40204	70053	525	1	1	1	0	0	1	1	0	0	70038	69787	59712	25	40108	30103	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	3	1	10002	86	2	4	10000	1	1	0	1	1	2611	2	71	5	2	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70130
40204	70060	525	1	0	0	0	0	2	1	0	1	70038	69784	59712	25	40108	30106	10002	30100	10000	616078	3342350	1	49	66973	70053	70053	64649	21	65018	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10001	82	2	1	10000	0	1	1	1	0	2611	2	71	2	3	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70143
40204	70041	525	1	0	0	0	0	2	1	0	0	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	89	1	1	10000	1	1	1	1	0	2611	3	71	3	3	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70147
40204	70053	525	1	0	0	0	0	2	1	0	1	70038	69784	59712	25	40108	30103	10002	30100	10000	616032	3342350	1	49	66976	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10010	4	1	10003	0	1	4	10000	1	1	1	1	1	2611	3	94	3	4	70082	30056	6	6	6	10000	30100	70362	70456	70479	70479	70650
40204	70057	524	1	1	2	0	0	2	0	0	1	70038	69787	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64649	3	64956	41097	30358	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	0	19	10000	1	1	1	1	0	2611	3	71	2	3	69819	30006	6	6	6	10000	30100	70057	70054	70054	70042	70118
40204	70053	524	1	0	0	0	0	1	1	0	1	70038	69784	59712	25	40108	30103	10002	30100	10000	616032	3341769	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	81	0	7	10000	1	1	1	1	1	2611	3	71	3	2	69819	30006	6	6	0	10000	30100	70054	70054	70054	70054	70123
40204	70053	525	1	0	1	0	0	2	1	0	1	70038	69702	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70041	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	94	1	1	10000	1	1	0	1	0	2611	2	71	2	3	69816	30006	6	0	6	10000	30100	70054	70144	70055	70054	70099
40204	70053	524	1	1	1	0	0	2	1	0	1	70038	69702	59712	25	40108	30106	10002	30100	10000	616032	3342350	0	49	66973	70056	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	56	2	1	10000	1	1	0	1	1	2611	2	71	3	3	69804	30006	6	6	6	10000	30100	70054	70054	70054	70054	70133

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	0	0	0	1	0	0	70035	69702	59701	25	40014	30010	10001	30010	10000	617068	3342206	1	49	66970	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	0	0	2520	6	71	3	5	69813	30003	9	6	0	10000	30010	70036	70036	70054	70135	70049
40024	70047	525	0	0	0	0	6	0	0	70020	69777	59709	25	40010	30013	10004	30010	10000	617104	3342110	1	49	66970	70050	70050	64668	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	0	0	2520	5	71	4	6	69813	30003	6	6	6	10000	30010	70048	70048	70048	70169	70036
40024	70050	524	0	0	0	0	1	0	0	70020	69777	59732	25	40014	30010	10000	30010	10000	616982	3342206	1	49	66955	70050	70055	64668	3	64960	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	0	0	2520	5	71	5	5	69810	30000	9	9	9	10000	30010	70051	70036	70128	70054	70052
40024	70050	524	0	0	0	0	190	0	0	70032	69777	59726	25	40010	30013	10001	30010	10000	616952	3342206	1	49	66955	70035	70050	64665	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	0	1	0	2520	6	88	5	3	69798	30000	6	6	0	10000	30010	70048	70048	70042	70120	70051
40024	70037	524	0	0	0	0	1	1	0	70038	69777	59775	25	40010	30010	10001	30010	10000	616952	3342206	1	49	66955	70050	70035	64665	3	64980	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	2520	6	71	5	3	69810	30003	0	0	6	10000	30010	70036	70048	70054	70141	70036
40024	70047	524	0	0	0	0	1	0	0	70020	69777	59741	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66970	70035	70050	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	0	0	2520	3	71	5	4	69813	30003	9	0	0	10000	30010	70036	70051	70054	70144	70048
40024	70035	524	0	0	0	0	1	0	0	70035	69777	59767	25	40010	30013	10000	30010	10000	616982	3341470	1	49	66955	70035	70047	64665	3	64960	40010	30020	10000	60020	20000	70050	77	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	0	2520	5	71	5	5	69813	30003	9	6	0	10000	30010	70036	70036	70048	70079	70051
40024	70047	525	0	0	0	0	10	1	0	70020	69777	59760	25	40014	30013	10001	30010	10000	616952	3342206	1	49	66955	70035	70047	64668	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	0	2520	3	71	4	7	69798	30000	6	6	9	10000	30010	70048	70051	70054	70152	70054
40024	70050	524	0	0	0	0	177	1	0	70035	69777	59714	25	40014	30010	10001	30010	10000	617068	3341470	1	49	66959	70050	70035	64668	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10001	1	1	0	2520	5	71	6	5	69813	30000	9	0	9	10000	30010	70051	70048	70042	70100	70048
40024	70035	525	0	0	1	0	1	1	0	70032	69777	59738	25	40014	30013	10001	30010	10000	616982	3341470	1	49	66955	70050	70050	64668	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	2520	5	71	6	4	69810	30003	0	0	9	10000	30010	70036	70036	70054	70133	70036

Test 4: throughput

Count: 8

Code:

  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]
  ldr w0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26734	200	1	0	1	0	0	65	0	0	3	26718	2	21	18	16	25	80100	100	80000	100	80015	500	1166596	0	49	23627	26728	26728	16656	6	16659	80114	200	80024	200	160048	26728	56	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	80042	0	1	0	46	80000	3	1	59	42	19	1	1	1	1	5118	0	16	0	0	26725	11	0	4	80000	100	26712	26734	26733	26725	26725
80204	26728	200	0	0	0	1	0	41	1	0	0	26713	2	18	0	18	25	80100	100	80000	100	80016	500	1167224	0	49	23653	26714	26733	16661	6	16667	80115	200	80024	200	160048	26714	63	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	0	80061	0	0	0	62	80041	3	1	19	0	19	1	1	1	1	5118	0	16	0	0	26711	10	10	3	80000	100	26734	26745	26734	26735	26734
80204	26714	200	1	0	0	1	0	65	1	0	0	26699	2	21	0	17	25	80100	100	80000	100	80015	500	1169611	0	49	23654	26714	26733	16661	6	16666	80116	200	80024	200	160048	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80060	1	0	0	62	80042	3	1	60	0	19	0	1	1	1	5118	0	16	0	0	26730	10	10	3	80000	100	26740	26735	26734	26734	26734
80204	26734	200	1	1	1	0	1	65	1	0	3	26719	0	0	18	0	25	80100	100	80000	100	80016	500	1169611	0	49	23634	26719	26714	16661	6	16685	80116	200	80024	200	160048	26714	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	42	80019	1	1	1	62	80041	0	1	60	0	19	0	1	1	1	5118	0	16	0	0	26731	10	0	3	80000	100	26736	26715	26740	26734	26716
80204	26733	200	1	0	0	0	0	65	0	0	3	26718	2	0	18	16	25	80100	100	80000	100	80016	500	1166836	0	49	23634	26733	26734	16661	6	16686	80116	200	80024	200	160048	26733	64	1	1	80201	100	99	100	80000	100	80000	0	100	80021	21	0	80061	0	0	1	61	80000	3	1	62	0	19	0	1	1	1	5118	0	16	0	0	26731	0	10	0	80000	100	26731	26734	26715	26715	26734
80204	26733	200	1	1	0	0	0	65	0	0	3	26718	2	0	18	0	25	80100	100	80000	100	80016	500	1169805	1	49	23653	26715	26714	16661	6	16685	80116	200	80024	200	160048	26714	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	80060	2	0	1	62	80041	3	1	60	42	19	1	1	1	1	5118	0	16	0	0	26730	10	10	3	80000	100	26739	26741	26715	26735	26734
80204	26714	200	1	0	0	0	0	65	0	0	2	26718	2	18	18	0	25	80100	100	80000	100	80016	500	1169805	0	49	23653	26733	26733	16642	6	16666	80115	200	80024	200	160048	26734	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	21	42	80060	0	0	2	62	80041	0	0	60	0	19	0	1	1	1	5118	0	16	0	0	26730	10	10	3	80000	100	26744	26803	26736	26743	26734
80204	26734	200	1	1	1	0	0	65	0	0	2	26718	2	18	0	17	25	80100	100	80000	100	80016	500	1169805	0	49	23653	26736	26715	16661	6	16685	80115	200	80024	200	160048	26734	82	1	1	80201	100	99	100	80000	100	80000	1	100	80020	19	42	80060	0	0	0	63	80041	0	1	19	0	19	0	2	2	2	5128	1	23	1	1	26730	0	0	3	80000	100	26737	26721	26734	26734	26734
80204	26714	201	1	0	1	0	0	66	1	0	3	26718	2	18	18	16	25	80100	100	80000	100	80021	500	1158923	0	49	23634	26714	26733	16651	9	16654	80120	200	80030	200	160060	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	80190	0	0	3	62	80041	3	1	60	0	19	1	2	2	2	5129	1	23	1	1	26712	10	0	3	80000	100	26739	26789	26737	26745	26734
80204	26733	200	1	0	2	1	0	65	0	0	3	26718	2	18	18	17	25	80100	100	80000	100	80020	500	1166730	0	49	23635	26733	26733	16651	9	16673	80121	200	80030	200	160060	26733	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	21	0	80062	2	0	0	21	80000	3	1	60	42	19	1	2	2	2	5128	1	23	1	1	26711	0	10	3	80000	100	26745	26734	26715	26716	26734

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26734	200	1	1	1	0	0	0	65	0	1	0	3	26719	2	18	18	81	25	80010	10	80000	10	80000	50	1167872	1	49	23653	26733	26715	16678	3	16714	80010	20	80000	20	160000	26733	82	1	1	80021	10	9	10	80000	10	80000	1	10	80019	20	42	0	80060	1	0	0	62	80041	3	1	60	42	19	1	0	5020	5	16	2	4	26711	10	10	3	80000	10	26830	26739	26847	26724	26735
80024	26733	201	1	0	1	1	0	0	65	0	0	0	3	26718	3	18	18	23	25	80010	10	80000	10	80000	50	1167708	1	49	23653	26733	26733	16679	3	16714	80010	20	80000	20	160000	26733	82	1	1	80021	10	9	10	80000	10	80000	0	10	80021	20	43	0	80060	1	0	0	62	80040	3	1	60	42	19	1	0	5020	2	16	2	4	26730	10	10	3	80000	10	26842	26746	26781	26728	26734
80024	26733	200	1	1	1	0	0	0	64	0	1	0	3	26719	2	18	21	26	25	80010	10	80000	10	80000	50	1168249	1	49	23653	26715	26734	16678	3	16713	80010	20	80000	20	160000	26734	82	1	1	80021	10	9	10	80000	10	80000	0	10	80022	20	42	0	80060	0	0	0	62	80041	3	1	60	42	19	1	0	5020	4	16	4	4	26730	10	10	3	80000	10	26831	26745	26842	26746	26734
80024	26715	200	1	0	0	0	0	0	65	0	1	0	3	26699	2	18	18	19	25	80010	10	80000	10	80000	50	1167347	1	49	23654	26733	26733	16679	3	16714	80010	20	80000	20	160000	26733	82	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	42	0	80060	1	0	0	65	80041	0	1	60	42	19	0	0	5020	2	16	2	4	26730	10	10	3	80000	10	26830	26748	26734	27185	26741
80024	26739	200	1	0	1	0	0	0	65	0	1	0	3	26718	0	18	18	28	25	80010	10	80000	10	80000	50	1170252	1	49	23653	26733	26733	16678	3	16713	80010	20	80000	20	160000	26734	83	1	1	80021	10	9	10	80000	10	80000	0	10	80021	19	42	0	80060	1	0	1	62	80041	3	1	60	42	19	0	0	5020	2	16	4	4	26730	10	10	3	80000	10	26835	26743	26794	26742	26734
80024	26733	200	1	1	0	0	0	0	65	0	1	0	3	26718	2	0	21	22	25	80010	10	80000	10	80000	50	1166311	1	49	23653	26715	26715	16678	3	16713	80010	20	80000	20	160000	26734	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	0	80060	0	1	2	62	80041	3	0	19	42	19	1	0	5020	2	16	6	6	26730	10	10	3	80000	10	26843	26740	26737	26742	26734
80024	26733	200	1	1	0	0	0	0	545	0	1	0	3	26718	2	18	18	24	25	80010	10	80000	10	80000	50	1166960	1	49	23654	26733	26733	16679	3	16695	80010	20	80000	20	160000	26733	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	42	0	80060	0	2	0	65	80041	3	1	63	42	19	1	0	5020	4	16	4	2	26730	10	10	3	80000	10	26734	26743	26738	26734	26738
80024	26734	200	1	0	1	0	0	0	65	0	1	0	3	26719	2	18	18	20	25	80010	10	80000	10	80000	50	1167708	1	49	23653	26733	26733	16678	3	16713	80010	20	80000	20	160000	26733	82	1	1	80021	10	9	10	80000	10	80000	0	10	80020	20	42	0	80060	0	0	1	62	80041	3	1	60	42	19	2	0	5020	4	16	6	6	26730	10	10	3	80000	10	26843	26738	26737	26824	26734
80024	26733	200	1	1	1	0	0	0	65	0	1	0	2	26719	2	18	18	19	25	80010	10	80000	10	80000	50	1167708	1	49	23653	26734	26734	16678	3	16713	80010	20	80000	20	160000	26714	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	0	80061	1	0	1	62	80042	3	0	60	42	19	0	0	5020	2	16	2	4	26730	10	10	3	80000	10	26840	26740	26737	26737	26734
80024	26735	200	1	1	1	0	0	0	65	0	1	0	3	26718	2	18	18	101	25	80010	10	80000	10	80000	50	1170252	1	49	23653	26734	26733	16678	3	16713	80010	20	80000	20	160000	26734	82	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	42	0	80063	1	0	1	62	80041	3	1	60	42	19	1	0	5020	2	16	2	4	26731	10	10	3	80000	10	26828	26740	26736	26740	26734

LDR (register, lsl, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations