Firestorm: DMB (ISHST) measurements

Code:

  dmb ishst

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst barrier (9c)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	3027	23	0	0	0	0	0	0	0	0	3012	2001	1000	1000	1000	6000	1	42	0	3035	3027	3	2893	1000	1000	3035	3027	1	1	1001	1000	0	0	0	1000	0	0	0	0	74	2	16	2	2	3023	1000	3028	3036	3028	3036	3026
1004	3035	22	0	0	0	0	0	0	0	1	3020	2001	1000	1000	1000	6000	1	33	0	3026	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	0	0	0	1000	1	0	0	0	74	2	16	2	2	3032	1000	3027	3036	3027	3036	3027
1004	3026	23	0	0	0	0	0	0	0	1	3012	2000	1000	1000	1000	6000	1	42	0	3035	3027	3	2884	1000	1000	3027	3035	1	1	1001	1000	0	0	0	1000	0	0	0	0	74	2	16	2	2	3032	1000	3027	3036	3026	3036	3028
1004	3027	23	0	0	0	0	0	0	0	1	3020	2009	1000	1000	1000	6000	1	33	0	3027	3035	3	2893	1000	1000	3035	3027	1	1	1001	1000	0	0	0	1000	0	0	0	0	74	2	16	2	2	3024	1000	3036	3028	3036	3028	3036
1004	3035	22	0	0	0	0	0	0	0	1	3020	2009	1000	1000	1000	6000	1	42	0	3035	3027	3	2885	1000	1000	3027	3035	1	1	1001	1000	0	0	0	1000	0	0	0	0	74	2	16	2	2	3023	1000	3027	3036	3028	3036	3027
1004	3026	23	0	0	0	0	0	0	0	1	3134	2000	1008	1008	1008	6144	1	49	75	3136	3026	6	3017	1008	1008	3026	3139	2	1	1001	1000	0	0	0	1008	1	0	220	2	86	2	24	2	2	3108	1000	3123	3127	3123	3036	3140
1004	3070	24	1	0	0	1	1	12	88	2	3012	2088	1008	1000	1000	6000	1	49	0	3114	3142	6	3004	1008	1008	3126	3162	2	1	1001	1000	4	2	3	1009	1	4	873	4	86	2	24	2	2	3059	1000	3027	3159	3131	3144	3174
1004	3069	23	1	0	0	1	1	12	88	1	3047	2009	1008	1000	1008	6048	1	49	0	3151	3055	6	2884	1000	1000	3053	3149	1	1	1001	1000	4	2	0	1008	0	0	635	0	74	2	24	2	2	3123	1000	3159	3160	3036	3162	3164
1004	3072	23	1	1	1	1	0	12	0	1	3135	2009	1008	1008	1008	6048	1	49	42	3142	3027	6	2973	1000	1008	3167	3153	2	1	1001	1000	0	2	2	1008	1	0	3	0	87	2	24	2	2	3110	1000	3123	3136	3150	3036	3159
1004	3121	23	0	1	1	0	0	12	0	1	3012	2001	1000	1000	1000	6000	1	33	0	3027	3035	3	2893	1000	1000	3035	3026	1	1	1001	1000	0	0	0	1000	0	0	3	0	74	2	16	2	2	3024	1000	3036	3026	3036	3027	3036

Code:

  dmb ishst

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.9135

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	29007	217	0	0	0	0	0	0	29027	18917	10100	100	10000	100	10000	500	59800	1	49	25955	29135	29028	3	27843	10100	200	10000	200	29135	23210	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29132	0	10000	100	29028	29136	29037	29136	29026
10204	29025	218	0	0	0	0	0	0	29028	18908	10100	100	10000	100	10000	500	59800	1	49	26055	29035	29135	3	27843	10100	200	10000	200	29135	23215	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29040	0	10000	100	29136	29035	29136	29026	29136
10204	29135	218	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	1	49	25945	29135	29035	3	27750	10100	200	10000	200	29043	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29132	0	10000	100	29136	29036	29136	29029	29136
10204	29135	217	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	25947	29135	29036	3	27751	10100	200	10000	200	29044	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29132	0	10000	100	29044	29136	29044	29136	29043
10204	29042	218	0	0	0	0	0	0	29021	18909	10100	100	10000	100	10000	500	59800	1	49	26055	29044	29135	3	27843	10100	200	10000	200	29135	23215	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	18	0	710	1	16	1	1	29132	0	10000	100	29045	29136	29044	29136	29044
10204	29043	218	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	0	49	26055	29035	29135	3	27843	10100	200	10000	200	29135	23221	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29032	0	10000	100	29136	29044	29136	29036	29136
10204	29135	218	0	0	0	0	0	0	29120	18908	10100	100	10000	100	10000	500	59800	1	49	26055	29042	29135	3	27843	10100	200	10000	200	29135	23216	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29031	0	10000	100	29136	29036	29136	29173	29136
10204	29135	218	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	1	49	25947	29135	29036	3	27751	10100	200	10000	200	29044	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29117	0	10000	100	29136	29028	29136	29037	29136
10204	29135	217	0	0	0	0	0	0	29010	19008	10100	100	10000	100	10000	500	59800	1	49	25954	29135	29025	3	27744	10100	200	10000	200	29034	23295	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29132	0	10000	100	29136	29036	29136	29028	29136
10204	29135	217	0	0	0	0	0	0	29120	19008	10100	100	10000	100	10000	500	59800	1	49	25964	29135	29063	3	27843	10100	200	10000	200	29135	23223	1	1	10201	100	99	100	100	10000	100	0	0	10000	0	0	0	0	710	1	16	1	1	29132	0	10000	100	29036	29136	29029	29136	29036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.9867

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst barrier (9c)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	29865	224	0	29936	19915	10010	10	10000	10	10000	50	59982	1	6	49	26871	29867	29951	3	28596	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	6	5	16	2	2	29863	10000	10	29868	29952	29868	29952	29866
10024	29865	224	0	29849	19831	10010	10	10000	10	10000	50	59982	1	6	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29867	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	6	3	16	3	3	29948	10000	10	29952	29868	29952	29868	29952
10024	29951	223	0	29851	19829	10010	10	10000	10	10000	50	59982	1	6	49	26871	29866	29951	3	28681	10010	20	10000	20	29951	29866	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	6	2	16	3	3	29948	10000	10	29952	29868	29952	29866	29952
10024	29951	223	0	29936	19915	10010	10	10000	10	10000	50	59982	1	6	49	26785	29951	29866	3	28597	10010	20	10000	20	29867	29951	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	6	3	16	3	3	29863	10000	10	29867	29952	29867	29952	29867
10024	29866	224	0	29936	19830	10010	10	10000	10	10000	50	59982	1	6	49	26871	29867	29951	3	28681	10010	20	10000	20	29951	29865	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	0	3	16	3	3	29948	10000	10	29952	29866	29952	29867	29952
10024	29951	224	0	29936	19915	10010	10	10000	10	10000	50	59982	0	6	49	26784	29951	29866	3	28596	10010	20	10000	20	29867	29951	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	0	3	16	3	3	29948	10000	10	29952	29896	29867	29952	29868
10024	29867	224	0	29936	19915	10010	10	10000	10	10000	50	59982	0	0	49	26787	29951	29867	3	28597	10010	20	10000	20	29866	29951	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	0	3	16	3	3	29948	10000	10	29952	29867	29952	29868	29952
10024	29951	223	0	29936	19830	10010	10	10000	10	10000	50	59982	0	0	49	26871	29865	29951	3	28681	10010	20	10000	20	29951	29866	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	0	3	16	3	3	29864	10000	10	29868	29952	29867	29952	29868
10024	29867	224	0	29936	19915	10010	10	10000	10	10000	50	59982	0	0	49	26785	29951	29866	3	28597	10010	20	10000	20	29867	29951	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	0	2	16	2	2	29863	10000	10	29868	29952	29868	29952	29867
10024	29951	224	0	29851	19915	10010	10	10000	10	10000	50	59982	0	0	49	26871	29864	29951	3	28681	10010	20	10000	20	29866	29951	1	1	10021	10	9	10	10	10000	10	10000	0	0	640	0	3	16	3	3	29864	10000	10	29867	29952	29868	29952	29868

DMB (ISHST)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations