Firestorm: LDRSW (literal) measurements

Code:

  ldrsw x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	20	22	23	3a	3e	3f	40	43	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	400	2	0	1	32	0	0	0	0	0	388	4	16	11	25	1000	1000	1000	14636	1	394	387	209	3	245	1000	1000	394	64	1	1	1001	1000	1000	0	1012	4	0	32	1027	10	0	0	0	37	1052	24	2	26	48	73	1	16	1	1	384	9	9	4	1000	405	404	388	388	403
1004	394	3	0	0	48	10	1	0	0	0	379	12	16	7	25	1000	1000	1000	14632	0	393	394	210	3	253	1000	1000	395	71	1	1	1001	1000	1000	1	1000	0	0	32	1050	13	0	8	0	26	1049	12	1	26	16	73	2	16	1	1	384	8	7	4	1000	388	388	388	388	388
1004	387	3	0	0	32	10	0	0	0	0	372	0	16	9	25	1000	1000	1000	14663	1	387	395	209	3	245	1000	1000	387	64	1	1	1001	1000	1000	0	1005	0	0	16	1026	5	0	7	0	27	1032	6	1	26	16	73	2	16	1	1	391	8	7	7	1000	388	388	388	388	396
1004	387	3	0	0	32	0	0	0	0	0	372	6	17	9	25	1000	1000	1000	14716	0	387	387	209	3	245	1000	1000	387	64	1	1	1001	1000	1000	0	1000	0	0	16	1036	5	0	10	0	26	1026	6	2	26	16	73	2	16	1	1	384	8	7	4	1000	388	388	388	388	388
1004	386	2	1	1	32	0	0	0	0	0	372	0	16	7	25	1000	1000	1000	14636	0	387	386	213	3	245	1000	1000	393	64	1	1	1001	1000	1000	0	1000	0	0	16	1026	0	0	0	0	26	1026	6	1	26	16	73	2	16	1	1	384	8	7	4	1000	388	388	388	388	388
1004	387	3	1	0	32	0	0	0	0	0	372	4	16	8	25	1000	1000	1000	14684	1	387	387	210	3	245	1000	1000	387	64	1	1	1001	1000	1000	0	1007	0	0	16	1026	5	0	5	6	26	1026	6	1	27	16	73	2	16	1	1	384	8	7	4	1000	388	388	388	388	387
1004	387	2	0	0	32	7	1	0	0	0	372	0	16	8	25	1000	1000	1000	14636	0	387	387	210	3	245	1000	1000	386	64	1	1	1001	1000	1000	0	1005	0	1	16	1026	0	0	12	0	26	1034	6	1	26	16	73	2	16	1	1	384	8	7	4	1000	388	388	388	388	388
1004	387	3	0	0	33	0	0	0	0	0	377	6	16	6	25	1000	1000	1000	14716	0	387	387	209	3	245	1000	1000	393	64	1	1	1001	1000	1000	0	1005	0	0	16	1027	10	0	0	6	26	1026	6	1	26	16	73	1	16	1	1	384	8	7	4	1000	388	397	388	397	388
1004	387	3	0	0	32	5	1	0	0	0	372	0	16	8	25	1000	1000	1000	14632	1	396	387	210	3	245	1000	1000	387	64	1	1	1001	1000	1000	0	1000	0	0	16	1036	0	0	5	0	27	1026	6	1	27	16	73	2	16	1	1	392	8	7	2	1000	395	388	388	389	388
1004	386	3	0	0	48	7	0	0	0	0	372	0	16	8	25	1000	1000	1000	14632	0	387	387	210	3	245	1000	1000	387	73	1	1	1001	1000	1000	0	1000	0	0	16	1026	0	0	0	0	26	1036	6	1	26	16	73	2	16	1	1	384	8	7	4	1000	397	387	388	388	388

Count: 8

Code:

  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4
  ldrsw x0, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3339

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	3a	3e	3f	40	43	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26729	200	0	0	0	0	0	16	5	1	8	0	26709	11	1	3	25	80100	100	80130	100	80000	500	1166627	0	49	23635	26868	26719	16649	3	16678	80100	200	80000	200	26719	62	1	1	80201	100	99	100	80000	100	80000	0	100	80275	133	2	32	80010	288	0	390	0	11	80127	18	3	11	32	79	454	5110	3	16	3	3	26710	0	7	11	2	80000	100	26721	26713	26714	26713	26720
80204	26713	200	3	0	43	0	0	38	5	1	1	0	26697	9	1	15	25	80100	100	80000	100	80000	500	1166269	0	49	23635	26713	26715	16642	3	16671	80100	200	80000	200	26713	62	1	1	80201	100	99	100	80000	100	80000	0	100	80040	68	2	48	80011	102	0	39	0	23	80021	12	1	22	32	354	121	5110	3	16	3	3	26712	0	4	3	2	80000	100	26714	26729	26714	26714	26714
80204	26718	200	0	0	56	0	0	16	5	1	233	0	26698	10	1	3	25	80100	100	80000	100	80000	500	1166599	0	49	23633	26713	26713	16643	3	16671	80100	200	80000	200	26713	62	1	1	80201	100	99	100	80000	100	80000	0	100	80286	41	3	16	80012	548	0	83	0	11	80219	6	1	11	16	46	256	5110	3	16	3	3	26710	0	4	4	2	80000	100	26721	26717	26715	26714	26713
80204	26713	200	3	0	47	0	1	17	0	1	322	0	26700	9	1	10	25	80100	100	80000	100	80000	500	1166240	0	49	23635	26713	26713	16636	3	16671	80100	200	80000	200	26713	62	1	1	80201	100	99	100	80000	100	80000	0	100	80479	93	1	16	80011	287	0	375	6	11	80207	6	1	10	16	153	400	5110	3	16	3	3	26710	0	4	4	2	80000	100	26848	26724	26723	26714	26715
80204	26720	200	43	0	22	0	0	23	5	0	112	0	26698	3	0	3	25	80100	100	80000	100	80000	500	1166632	0	49	23635	26713	26713	16637	3	16671	80100	200	80000	200	26714	62	1	1	80201	100	99	100	80000	100	80000	0	100	80501	0	0	16	80011	366	1	500	0	10	80198	6	1	10	16	235	292	5110	3	16	3	3	26720	0	4	4	2	80000	100	26714	26714	26714	26715	26714
80204	26713	200	48	0	57	0	0	17	0	0	70	0	26707	4	3	3	25	80100	100	80000	100	80000	500	1166746	0	49	23633	26723	26714	16637	3	16678	80100	200	80000	200	26713	62	1	1	80201	100	99	100	80000	100	80000	0	100	80103	4	3	16	80011	212	0	454	0	14	80242	12	1	11	16	332	284	5110	3	16	3	3	26710	0	8	5	2	80000	100	26714	26714	26714	26713	26724
80204	26721	201	41	0	20	0	0	24	0	0	168	0	26697	10	0	3	25	80100	100	80000	100	80000	500	1175833	0	49	23633	26712	27015	16728	3	16671	80100	200	80000	200	26713	62	1	1	80201	100	99	100	80000	100	80000	0	100	80270	0	0	0	80011	387	0	489	0	11	80136	6	1	10	16	636	124	5110	3	16	3	3	26890	0	4	3	2	80000	100	26714	26714	26714	26714	26717
80204	26716	200	4	0	29	0	0	16	0	0	3	16	26698	0	1	3	25	80100	100	80000	100	80000	500	1166327	0	49	23632	26713	26713	16637	3	16673	80100	200	80000	200	26713	62	1	1	80201	100	99	100	80000	100	80000	0	100	80396	0	0	16	80011	72	0	142	8	20	80195	12	1	11	16	155	220	5110	3	16	3	3	26721	0	4	4	2	80000	100	26719	26714	26714	26714	26722
80204	26711	200	15	0	5	0	0	32	5	0	0	0	26712	0	1	3	25	80100	100	80000	100	80000	500	1166530	0	49	23633	26713	26712	16636	3	16671	80100	200	80000	200	26714	69	1	1	80201	100	99	100	80000	100	80000	0	100	80074	31	3	48	80011	236	0	154	8	20	80117	6	1	10	16	317	133	5110	3	16	3	3	26716	0	4	3	2	80000	100	26714	26714	26721	26714	26714
80204	26715	200	67	0	19	0	0	39	5	1	255	0	26714	4	0	3	25	80100	100	80000	100	80000	500	1166843	0	49	23633	26718	26713	16636	3	16670	80100	200	80000	200	26715	62	1	1	80201	100	99	100	80000	100	80000	0	100	80336	0	1	32	80021	80	0	240	0	10	80226	18	1	11	16	582	184	5110	3	16	3	3	26718	0	4	3	2	80000	100	26719	26720	26719	26721	26714

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3357

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80024	26969	202	0	0	0	0	0	0	441	97	1	0	0	17	100	26896	131	12	36	76	117	25	80010	10	80000	10	80000	50	1172233	0	1	49	23729	26837	26826	16829	3	16836	80010	20	80000	20	26864	71	1	1	80021	10	9	0	10	80000	10	80000	0	10	80179	5	19	556	80268	231	2	199	32	335	80461	142	21	261	351	0	50	114	0	5020	0	1	16	1	1	26840	37	30	10	80000	10	26849	26859	26879	26844	26863
80024	26864	201	0	3	0	0	1	0	379	81	0	0	0	8	72	26893	132	9	50	83	85	25	80010	10	80000	10	80000	50	1172142	0	0	49	23793	26873	26888	16902	3	16841	80010	20	80000	20	26892	71	1	1	80021	10	9	0	10	80000	10	80000	0	10	80054	4	9	283	80232	93	2	92	28	253	80336	96	18	207	256	0	122	99	0	5020	0	1	16	1	1	26832	23	29	8	80000	10	26843	26848	26867	26855	26855
80024	26897	202	0	0	1	2	0	0	422	99	1	0	1	9	72	26869	94	6	25	81	90	25	80010	10	80000	10	80000	50	1173255	0	1	49	23809	26862	26900	16851	3	16860	80010	20	80000	20	26893	71	1	1	80021	10	9	0	10	80000	10	80000	0	10	80152	19	16	390	80285	197	0	193	72	400	80362	99	17	302	348	19	53	63	0	5020	0	1	16	1	1	26918	21	36	23	80000	10	26870	26874	26878	26906	26854
80024	26876	202	1	3	1	2	0	0	389	101	0	0	0	12	80	26935	119	9	24	24	103	25	80010	10	80000	10	80000	50	1170700	0	1	49	23759	26861	26897	16877	3	16814	80010	20	80000	20	26843	71	1	1	80021	10	9	0	10	80000	10	80000	0	10	80201	25	10	367	80348	172	2	140	34	337	80483	121	18	291	315	19	6	145	0	5020	0	1	16	1	1	26872	16	37	19	80000	10	26872	26858	26824	26856	26830
80024	26849	201	1	1	4	2	0	0	365	88	0	0	0	7	72	26910	95	9	33	22	110	25	80010	10	80000	10	80000	50	1176242	0	0	49	23851	26907	26909	16800	3	16859	80010	20	80000	20	26867	83	1	1	80021	10	9	0	10	80000	10	80000	0	10	80171	20	21	365	80315	208	3	205	40	286	80451	134	22	310	344	19	77	191	0	5020	0	1	16	1	1	26895	22	24	11	80000	10	26840	26848	26845	26867	26865
80024	26849	200	1	0	1	1	0	0	282	105	1	0	0	17	88	26891	122	14	49	42	83	25	80010	10	80000	10	80000	50	1173102	0	0	49	23726	26833	26823	16760	3	16837	80010	20	80000	20	26856	71	1	1	80021	10	9	0	10	80000	10	80000	0	10	80139	22	7	504	80342	187	2	178	36	374	80365	115	15	273	436	19	60	739	0	5020	0	1	16	1	1	26904	29	19	15	80000	10	26861	26844	26875	26883	26815
80024	26850	201	1	2	1	2	0	0	300	28	1	0	0	11	44	26897	119	5	68	78	98	25	80010	10	80000	10	80000	50	1173891	0	0	49	23777	26849	26940	16800	3	16821	80010	20	80000	20	26869	83	1	1	80021	10	9	0	10	80000	10	80000	0	10	80212	27	21	353	80286	179	3	146	14	342	80374	88	20	259	300	19	54	283	0	5020	0	1	16	1	1	26870	32	22	8	80000	10	26880	26829	26832	26844	26904
80024	26933	201	1	2	2	1	0	0	475	118	0	0	0	10	56	26926	73	13	26	45	87	25	80010	10	80000	10	80000	50	1172875	0	1	49	23784	26846	26837	16796	3	16843	80010	20	80000	20	26857	71	1	1	80021	10	9	0	10	80000	10	80000	1	10	80151	21	14	471	80274	155	4	100	24	282	80431	99	14	246	303	19	20	658	0	5020	0	1	16	1	1	26894	22	19	7	80000	10	26851	26863	26858	26904	26851
80024	26855	201	1	1	0	1	0	1	394	81	1	0	0	8	60	26931	116	6	2	36	84	25	80010	10	80000	10	80000	50	1178838	0	0	49	23763	26834	26811	16783	3	16853	80010	20	80000	20	26868	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80090	5	9	369	80251	78	2	174	42	304	80420	83	14	223	448	0	81	30	1	5020	0	1	16	1	1	26908	25	31	17	80000	10	26841	26827	26847	26833	26822
80024	26853	201	0	0	0	0	0	0	342	104	1	0	0	10	80	26864	123	8	59	35	108	25	80010	10	80000	10	80000	50	1173849	0	1	49	23768	26831	26827	16770	3	16820	80010	20	80000	20	26830	71	1	1	80021	10	9	0	10	80000	10	80000	0	10	80129	0	0	358	80302	40	3	75	26	311	80415	123	18	268	365	0	8	94	0	5020	0	1	16	1	1	26851	21	25	17	80000	10	26861	26865	26838	26841	26836

LDRSW (literal)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations