Firestorm: ORR (register, 64-bit) measurements

Code:

  orr x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	862	25	1000	1000	1000	16916	1	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1083
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	0	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	862	25	1000	1000	1000	16916	0	1035	1035	728	3	868	1000	1000	2000	1035	41	1	1	1001	1000	53	0	73	1	41	1	1	937	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  orr x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	39	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	103	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	1	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	187	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	82	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	12	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	120	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	3	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	79	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	84	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  orr x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10082
10204	10035	75	0	0	160	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	114	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	82	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	82	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	54	0	61	9877	25	10100	10100	10100	88664	0	49	6955	10035	10035	8580	3	8722	10100	10200	20200	10035	41	1	1	10201	100	99	100	10100	100	0	710	2	37	2	2	9941	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	103	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	84	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	82	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	20	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	25	10010	10010	10010	88784	1	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	61	9863	47	10010	10010	10010	88784	0	49	6955	10035	10035	8602	3	8740	10010	10020	20020	10035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	9940	10000	10010	10036	10036	10036	10036	10036

Test 4: throughput

Count: 8

Code:

  orr x0, x8, x9
  orr x1, x8, x9
  orr x2, x8, x9
  orr x3, x8, x9
  orr x4, x8, x9
  orr x5, x8, x9
  orr x6, x8, x9
  orr x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	13390	100	12	0	35	25	80100	80100	80100	400500	1	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	2	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	101	0	0	35	25	80100	80100	80100	400500	1	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	12	0	35	25	80100	80100	80100	400500	1	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	35	25	80100	80100	80100	400500	1	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	35	25	80100	80100	80100	400500	1	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	75	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	3	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	56	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387
80204	13386	100	0	0	35	25	80100	80100	80100	400500	0	49	10306	13386	13386	3323	3	3341	80100	80200	160200	13386	39	1	1	80201	100	99	100	80100	100	5110	1	19	1	1	13383	80000	80100	13387	13387	13387	13387	13387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	13387	100	0	0	58	25	80010	80010	80010	400050	1	0	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	0	0	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	101	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	3	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	5	1128	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371
80024	13370	100	0	0	35	25	80010	80010	80010	400050	1	5	49	10290	13370	13370	3323	3	3341	80010	80020	160020	13370	39	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	5	4	1	18	1	1	13367	80000	80010	13371	13371	13371	13371	13371

ORR (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations