Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (register, 64-bit)

Test 1: uops

Code:

  orr x0, x0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916110351035728386810001000200010354111100110000073141119371000100010361036103610361083
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103580618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
1004103570618622510001000100016916010351035728386810001000200010354111100110000073141119371000100010361036103610361036
10041035806186225100010001000169160103510357283868100010002000103541111001100053073141119371000100010361036103610361036

Test 2: Latency 1->2

Code:

  orr x0, x0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410035753961987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
1020410035750103987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886641496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
1020410035750187987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575061987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
102041003575082987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036
1020410035751261987725101001010010100886640496955100351003585803872210100102002020010035411110201100991001010010000071023722994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575012098632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357606198632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357536198632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357506198632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357507998632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036
10024100357508498632510010100101001088784049695510035100358602387401001010020200201003541111002110910100101064024122994010000100101003610036100361003610036

Test 3: Latency 1->3

Code:

  orr x0, x1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357500619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610082
102041003575001609877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
1020410035751140619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
10204100357500829877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
10204100357500829877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036
102041003575540619877251010010100101008866404969551003510035858038722101001020020200100354111102011009910010100100071023722994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)033f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100241003575829863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036
1002410035751039863251001010010100108878414969551003510035860238740100101002020020100358411100211091010010100000064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036
1002410035758298632510010100101001088784149695510035100358602387401001010020200201003541111002110910100101000200064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878404969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036
100241003575619863251001010010100108878414969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036
100241003575619863471001010010100108878404969551003510035860238740100101002020020100354111100211091010010100000064024122994010000100101003610036100361003610036

Test 4: throughput

Count: 8

Code:

  orr x0, x8, x9
  orr x1, x8, x9
  orr x2, x8, x9
  orr x3, x8, x9
  orr x4, x8, x9
  orr x5, x8, x9
  orr x6, x8, x9
  orr x7, x8, x9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1673

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413390100120352580100801008010040050014910306133861338633233334180100802001602001338639118020110099100801001005110219111338380000801001338713387133871338713387
802041338610100352580100801008010040050014910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
8020413386100120352580100801008010040050014910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
802041338610000352580100801008010040050014910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
802041338610000352580100801008010040050014910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
802041338610000352580100801008010040050004910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
8020413386100750352580100801008010040050004910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
802041338610030352580100801008010040050004910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
802041338610000562580100801008010040050004910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387
802041338610000352580100801008010040050004910306133861338633233334180100802001602001338639118020110099100801001005110119111338380000801001338713387133871338713387

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800241338710000582580010800108001040005010491029013370133703323333418001080020160020133703911800211091080010100000502000118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100000502054118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100000502054118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100000502054118111336780000800101337113371133711337113371
800241337010100352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100000502054118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100030502054118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100000502054118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100511280502054118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100000502054118111336780000800101337113371133711337113371
800241337010000352580010800108001040005015491029013370133703323333418001080020160020133703911800211091080010100000502054118111336780000800101337113371133711337113371