Firestorm: AUTDZA measurements

Code:

  autdza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	65	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	2	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	12	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	27	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	67	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	306	61	5824	25	1003	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	321	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	57	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	1	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	61	5824	25	1000	1003	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	66	0	536	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6656	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	73	3	85	3	3	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autdza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	617	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	3	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	618	0	0	0	0	0	0	726	59815	46	10222	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	3	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	1	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70070	70030
10204	70029	620	0	0	0	0	0	0	113	59824	25	10200	10200	10200	1808330	0	49	66949	0	70068	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	1745	0	0	0	0	710	1	87	1	1	69796	10104	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	126	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	2	0	0	0	0	0	0	0	0	710	1	79	1	1	69820	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	1	0	12	0	0	61	59815	47	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	87	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	620	0	0	0	0	0	0	89	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10228	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030
10204	70029	674	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	0	0	0	0	0	0	710	1	79	1	1	69796	10100	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	619	0	0	0	12	0	103	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	649	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70054	870	1	1	10021	10	9	10010	0	0	1	0	3	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	623	0	0	0	12	0	103	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	640	2	79	2	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	12	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	640	2	79	3	2	69805	10010	10010	70030	70030	70055	70030	70030
10024	70029	622	0	0	0	12	0	103	59824	25	10020	10020	10020	1807531	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	640	2	79	3	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	103	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	623	0	0	0	12	0	103	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	654	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	624	0	0	0	12	0	103	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	8	68721	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	640	3	79	2	2	69805	10010	10010	70030	70068	70030	70030	70030
10024	70029	623	0	0	0	12	0	104	59815	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68722	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	3	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	12	0	104	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70068	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  autdza x0
  autdza x1
  autdza x2
  autdza x3
  autdza x4
  autdza x5
  autdza x6
  autdza x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	80062	700	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	698	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	3	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	703	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	2	0	0	0	0	0	5110	2	25	5	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80080	699	0	0	0	0	72	0	0	77	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	3	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	3	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	27	0	0	203	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	80100	80036	80036	80036	80036	80036
80204	80035	701	0	0	0	0	0	0	0	510	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	0	80025	80100	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	80085	699	0	0	0	0	0	0	144	0	0	258	25	80041	80020	80020	400100	1	49	77001	80080	80080	69988	3	70006	80020	80020	80054	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5020	0	5	25	3	4	80024	80010	59	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	0	1	35	25	80020	80020	80020	400207	1	49	76955	80035	80035	69988	3	70006	80042	80020	80020	80035	164	1	1	80021	10	9	80010	0	2	0	0	0	2	475	0	5033	0	3	25	3	4	80059	80010	29	80010	80081	80036	80036	80036	80036
80024	80081	699	0	0	0	0	0	0	0	0	0	119	25	80020	80020	80020	400207	0	49	76955	80080	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	2	0	0	5020	0	3	25	3	4	80024	80010	26	80010	80036	80081	80036	80036	80082
80024	80035	700	0	0	0	0	1	0	0	88	0	35	25	80020	80062	80020	400100	1	49	76955	80035	80035	69988	3	70006	80020	80052	80020	80035	164	1	1	80021	10	9	80010	0	4	0	0	0	0	0	0	5020	3	3	25	3	4	80024	80010	0	80010	80082	80036	80036	80036	80080
80024	80035	748	0	0	0	0	0	0	0	0	0	732	25	80020	80020	80020	400100	0	49	76955	80035	80035	70007	3	70040	80042	80020	80053	80091	164	1	1	80021	10	9	80010	0	0	0	0	1	0	505	0	5020	0	3	25	4	4	80024	80010	0	80010	80036	80036	80082	80082	80036
80024	80035	751	0	0	0	0	0	0	0	88	0	57	25	80020	80020	80020	400100	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80081	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	5033	0	4	25	4	3	80024	80010	0	80010	80036	80036	80036	80081	80081
80024	80035	699	0	0	0	0	0	0	132	0	0	67	46	80041	80020	80020	400100	0	49	76955	80035	80172	69988	6	70006	80020	80053	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	1	0	0	2	5020	0	4	33	4	3	80024	80010	0	80010	80082	80036	80036	80036	80036
80024	80081	700	0	1	1	0	0	0	132	0	0	100	47	80068	80041	80020	400314	0	49	76955	80080	80035	69988	3	70040	80042	80020	80052	80081	164	1	1	80021	10	9	80010	0	0	0	0	0	0	9	0	5020	0	3	25	3	5	80024	80010	0	80010	80036	80081	80036	80081	80036
80024	80035	697	0	0	0	0	0	0	0	0	0	1577	25	80041	80020	80020	400100	0	49	76955	80035	80080	70006	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	2	1	1	0	0	0	5020	0	4	25	3	4	80024	80010	0	80010	80082	80081	80082	80036	80036
80024	80035	699	0	0	0	0	0	0	132	0	0	231	25	80020	80020	80042	400100	0	49	76955	80035	80035	70007	8	70006	80020	80020	80020	80035	164	2	1	80021	10	9	80010	0	0	0	0	0	0	510	0	5033	0	5	25	4	3	80059	80010	0	80010	80080	80036	80036	80126	80036

AUTDZA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations