Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (OSHLD)

Test 1: uops

Code:

  dsb oshld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
100417032128917017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128017017158011000100010006000049139521487117032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128017017158011000100010006000049139521485917032316921100010001703217032111001100010000073116111683810001703317033170331703317033
100417032127917017158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128317017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128017017158011000100010006000149139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128017017158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128017017158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321282417017158011000100010006000049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128017017158011000100010006000049139521485917032316890101510001703217032111001100010000073116111683810001703317033170331703317033

Test 2: throughput

Code:

  dsb oshld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4b51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10204170032127300000001700170159700101001001000010010000500598001491669521510351700323168740101002001000020017003213591911102011009910010010000100000100001200071021622169838010000100170033170033170033170033170033
102041700321274000000017001701597001010010010000100100005005980004916695215099417003231687401010020010000200170032135919111020110099100100100001000001000000450071021622169838010000100170033170033170033170033170033
10204170032127300000001700170159700101001001000010010016500598000491669521509351700323168740101002001000020017003213591911102011009910010010000100000100000000071021622169838010000100170033170033170033170033170033
102041701841273000065735801700170159700101001001000010010000500598001491669521509391700323168740101002001000020017003213591911102011009910010010000100000100000000071021622169838010000100170033170033170033170033170033
102041700321274000012001700170159700101001001000010010000500598001491669521509831700323168745101002001000020017003215482551102011009910010010000100000100341415210071021622169838010000100170033170033170033170033170033
10204170032127400000001700170159700101001001000010010000500598001491669521509351700323168740101002001000020017003213591911102011009910010010000100000100000000071021621169838010000100170033170033170033170033170033
102041700321273000000017001701597001010010010000100100005005980014916695215093517003231687401010020010000200170032135919111020110099100100100001000001000012000071021622169838010000100170033170033170033170033170033
10204170032127400000001700170159700101001001000010010000500598001491669521509351700323168740101302001000020017003213591911102011009910010010000100000100000000071021622169838010000100170033170033170033170033170033
10204170032127300000001700170159700101001001000010010000500598001491669521510041700323168740101002001000020017003213591911102011009910010010000100000100000000071021622169838010000100170033170033170033170033170049
10204170032127400000001700170159700101001001000010010000500598001491669521509351700323168740101002001000020017003213591911102011009910010010000100000100000000071021622169838010000100170033170033170033170033170033

1000 unrolls and 10 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)031e3f4151schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1002417003212740170017015978610010101000010100005059980491669521499571700323168762100102010000201700321700321110021109101010000100100000000640316321698431000010170033170033170033170033170033
1002417003212740170017015978610010101000010100005559980491669521499571700323168762100102010000201700321700321110021109101010000100100000000640316331698431000010170033170033170033170033170033
1002417003212740170017015978610010101000010100005059980491669521500321700323168762100102010000201700321700321110021109101010000100100090000640316331698431000010170033170033170033170033170033
1002417003212730170017015978610010101000010100005059980491669521499571700323168762100272010000201700321700321110021109101010000100100000000640216231698431000010170033170033170033170033170033
1002417003212740170017015978610010101000010100005059980491669521499571700323168762100102010000201700321700321110021109101010000100100000000640316331698431000010170033170033170033170033170033
1002417003212740170017015978610010101000010100005059980491669521499571700323168762100102010000201700321700321110021109101010000100100000000640316331698431000010170033170033170033170033170033
1002417003212730170017015978610010101000010100005059980491669521499571700323168762100102010000201700321700321110021109101010000100100000000640316331698431000010170033170033170033170033170033
1002417003212740170017015981410010101000010100005059980491669521499571700323168762100102010000201700321700321110021109101010000100100000000640316221698431000010170033170033170033170033170033
1002417003212730170017015978610010101000010100005059980491638971499571700323168762100102010000201700321700321110021109101010000100100001300640316221698431000010170033170033170033170033170033
1002417003212740170017015978610010101000010100005059980491669521499571700323168762100102010000201700321700321110021109101010000100100000000640316231698431000010170033170033170052170033170033