Firestorm: LDURSB (32-bit) measurements

Code:

  ldursb w0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	0	0	3	0	0	1	383	0	12	1	19	25	1000	1000	1000	15274	1	399	374	197	3	256	1000	1000	1000	374	77	1	1	1001	1000	1000	1	1000	43	1000	0	38	1039	6	1	39	44	73	1	16	1	1	371	14	10	7	1000	375	375	399	399	375
1004	374	2	1	1	51	1	0	1	383	0	1	12	19	25	1000	1000	1000	15037	1	374	394	221	3	256	1000	1000	1000	378	77	1	1	1001	1000	1000	0	1000	43	1038	0	0	1038	6	1	39	44	73	1	16	1	1	395	10	10	7	1000	399	399	399	375	395
1004	374	3	0	0	0	0	0	1	383	0	1	1	19	25	1000	1000	1000	15274	1	374	398	197	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	43	1039	0	38	1038	6	1	38	44	73	1	16	1	1	391	14	14	7	1000	375	399	399	395	399
1004	398	3	0	0	44	0	0	0	359	2	0	1	0	25	1000	1000	1000	15208	1	377	398	221	3	256	1000	1000	1000	394	56	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	0	0	0	43	73	1	16	1	1	371	0	14	7	1000	399	375	399	375	399
1004	398	3	1	1	45	1	0	1	383	2	12	12	0	25	1000	1000	1000	15208	1	403	374	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	1000	0	38	1000	6	1	0	0	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	375
1004	398	3	0	0	44	1	0	1	383	2	0	1	0	25	1000	1000	1000	15037	1	398	394	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1039	0	1	39	44	73	1	16	1	1	392	14	14	4	1000	375	399	395	395	375
1004	398	2	0	0	0	1	0	1	387	2	0	12	19	25	1000	1000	1000	14060	1	374	398	221	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1038	1	0	1038	0	0	39	43	73	1	16	1	1	395	14	14	7	1000	399	375	399	375	399
1004	398	2	0	0	45	1	0	0	383	2	1	0	19	25	1000	1000	1000	15018	1	398	394	221	3	252	1000	1000	1000	394	57	1	1	1001	1000	1000	0	1000	43	1038	1	41	1000	0	0	0	44	73	1	16	1	1	395	14	10	7	1000	375	399	399	399	375
1004	398	3	0	0	44	0	0	1	359	0	12	0	0	25	1000	1000	1000	15274	1	398	398	221	3	252	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	371	14	10	7	1000	375	399	375	399	399
1004	374	3	0	0	44	0	0	1	383	2	1	0	19	25	1000	1000	1000	14989	1	398	374	197	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	0	1038	0	38	1000	0	1	39	44	73	1	16	1	1	395	14	0	4	1000	375	399	399	375	399

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursb w0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0089

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	524	0	0	1	1	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616365	3343022	0	49	66974	70051	70051	64631	0	3	64954	40100	30200	10000	60200	10000	70051	80	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	6	10000	1	1	0	2610	2	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70055	70052
40204	70088	525	0	0	1	0	0	70036	69785	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70051	70051	64650	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	3	10000	0	1	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70092	524	0	0	6	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616041	3342254	1	49	66971	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	135	10000	1	1	0	2610	1	71	1	1	69820	30003	10	10	10	10000	30100	70052	70036	70052	70052	70052
40204	70051	524	0	0	1	0	0	70036	69782	59713	25	40104	30103	10001	30100	10204	616041	3342350	1	49	66974	70054	70051	64647	0	3	64938	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	6	10000	1	1	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70036	70052	70055
40204	70057	524	1	0	1	0	0	70036	69782	59713	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66975	70051	70051	64647	0	3	64954	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	141	10000	1	1	0	2610	1	71	1	1	69814	30003	10	10	0	10000	30100	70052	70052	70052	70052	70052
40204	70116	525	0	0	1	0	0	70039	69782	59710	25	40104	30103	10001	30100	10000	616068	3342254	1	49	66974	70051	70051	64631	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	102	10000	1	1	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70080	525	0	0	1	0	0	70039	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70054	70051	64631	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	111	10000	1	1	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70036	70052	70052	70087
40204	70062	525	0	0	1	0	0	70039	69785	59710	25	40100	30103	10001	30100	10000	616014	3342398	1	49	66971	70051	70054	64647	0	3	64954	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	144	10000	1	1	0	2610	1	71	1	1	69814	30003	0	10	10	10000	30100	70055	70055	70054	70052	70052
40204	70098	525	0	0	1	0	0	70086	69785	59710	25	40104	30103	10001	30100	10204	616023	3344126	1	49	66971	70051	70051	64650	0	3	64954	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	111	10000	1	1	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70055	70052	70052
40204	70117	525	0	0	1	0	0	70036	69782	59710	25	40100	30103	10001	30100	10000	616023	3342254	1	49	66971	70054	70035	64647	0	3	64954	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	126	10000	0	1	0	2610	1	71	1	1	69814	30003	13	13	10	10000	30100	70055	70052	70052	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	1	1	1	0	70032	69743	59709	25	40014	30013	10001	30010	10000	617068	3342206	0	49	66955	70050	70050	64653	3	64975	40010	30020	10000	60020	10000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	2520	2	71	3	3	69813	30000	0	0	9	10000	30010	70048	70051	70051	70036	70048
40024	70050	525	0	1	0	0	0	70035	69728	59706	25	40010	30010	10000	30010	10000	617068	3341470	1	49	66967	70050	70035	64668	3	64975	40010	30020	10000	60020	10000	70059	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	1	0	0	2520	2	71	3	3	69813	30003	0	0	9	10000	30010	70036	70051	70048	70051	70051
40024	70035	525	0	0	58	0	0	70032	69743	59709	25	40014	30010	10001	30010	10000	616982	3341470	0	49	66967	70050	70047	64668	3	64972	40010	30020	10000	60020	10000	70087	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	0	0	0	2520	1	71	3	5	69810	30003	9	6	0	10000	30010	70048	70048	70048	70048	70051
40024	70047	524	0	0	0	0	0	70020	69728	59706	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66955	70050	70035	64665	3	64972	40010	30020	10000	60020	10000	70076	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	2520	1	71	5	5	69798	30003	9	0	6	10000	30010	70036	70051	70036	70051	70036
40024	70047	525	0	0	1	0	0	70035	69760	59709	25	40014	30010	10000	30010	10000	616982	3342062	0	49	66967	70050	70050	64668	3	64975	40010	30020	10000	60020	10000	70092	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	6	10000	1	1	0	0	2520	2	71	3	2	69814	30000	9	0	0	10000	30010	70048	70051	70036	70048	70037
40024	70047	525	0	1	9	0	0	70035	69760	59695	25	40010	30013	10000	30010	10000	617068	3342062	0	49	66967	70035	70047	64653	3	64972	40010	30020	10000	60020	10000	70112	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	0	2520	1	71	3	3	69810	30003	0	0	0	10000	30010	70051	70036	70036	70051	70051
40024	70050	525	0	0	0	0	0	70020	69760	59695	25	40014	30013	10001	30010	10000	616982	3342206	0	49	66970	70035	70050	64668	3	64960	40010	30020	10000	60020	10000	70065	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	0	0	2520	2	71	3	3	69798	30012	9	9	9	10000	30010	70036	70051	70051	70036	70036
40024	70047	524	0	0	1	0	0	70035	69760	59706	25	40010	30013	10001	30010	10000	616952	3341470	0	49	66955	70050	70035	64653	3	64960	40010	30020	10066	60020	10000	70042	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	0	0	0	2520	1	71	6	5	69813	30003	6	9	9	10000	30010	70048	70048	70036	70048	70048
40024	70047	524	0	0	1	0	0	70020	69760	59695	25	40014	30010	10000	30010	10000	616952	3342206	0	49	66967	70050	70050	64668	3	64972	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	3	10000	1	1	0	0	2520	2	71	2	4	69810	30003	6	6	9	10000	30010	70036	70036	70051	70036	70048
40024	70035	524	0	0	1	0	0	70035	69760	59706	25	40014	30013	10001	30010	10000	617068	3341470	0	49	66970	70050	70050	64668	3	64960	40010	30020	10000	60020	10000	70072	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	10000	0	1	0	0	2520	1	71	3	7	69813	30003	0	6	9	10000	30010	70051	70048	70051	70051	70048

Test 3: throughput

Count: 8

Code:

  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]
  ldursb w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	1	1	0	0	0	45	0	0	0	1	26712	3	12	12	16	25	80100	100	80000	100	80000	500	1167231	49	23647	26727	26727	16650	3	16680	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	35	80000	6	1	35	43	5110	2	16	3	2	26709	6	6	4	80000	100	26728	26728	26728	26708	26708
80204	26707	200	0	0	0	0	0	0	45	0	0	0	0	26712	0	12	18	16	25	80100	100	80000	100	80000	500	1167808	49	23627	26731	26731	16649	3	16689	80100	200	80000	200	80000	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	39	80039	6	1	35	43	5110	2	16	2	2	26736	10	10	0	80000	100	26708	26708	26728	26728	26730
80204	26727	200	0	0	0	1	0	0	12	0	0	0	2	26722	0	12	18	102	48	80230	100	80000	100	80178	500	1159747	49	23647	26707	26727	16650	3	16665	80100	200	80000	200	80000	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	0	80039	6	1	35	0	5110	2	16	2	2	26724	6	6	2	80000	100	26728	26708	26728	26708	26723
80204	26732	200	1	0	0	0	0	1	45	0	0	0	2	26692	2	0	0	16	25	80100	100	80000	100	80000	500	1177231	49	23647	26725	26728	16650	3	16685	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	35	80000	6	1	0	0	5110	2	16	2	2	26730	10	0	2	80000	100	26728	26723	26728	26728	26708
80204	26707	200	0	0	0	0	0	0	45	0	0	0	2	26712	2	0	12	18	25	80100	100	80000	100	80000	500	1166525	49	23647	26727	26727	16630	3	16665	80100	200	80000	200	80000	26711	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	39	36	80000	0	795	80035	6	1	35	39	5110	3	16	2	2	26726	6	10	4	80000	100	26727	26731	26727	26712	26728
80204	26707	200	0	0	0	0	0	1	360	192	1	0	2	26697	0	12	12	0	33	80100	100	80000	100	80000	500	1177038	49	23642	26707	26713	16653	3	16685	80100	200	80000	200	80000	26937	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	39	80000	6	0	35	43	5110	2	16	2	2	26727	10	10	2	80000	100	26728	26728	26708	26728	26709
80204	26727	200	0	0	0	0	0	0	42	0	0	0	1	26692	0	12	0	16	25	80100	100	80000	100	80000	500	1159747	49	23627	26731	26732	16649	3	16669	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80039	0	0	80039	6	1	39	0	5110	2	16	2	2	26773	10	10	0	80000	100	26732	26712	26728	26708	26728
80204	26707	200	0	0	0	0	0	0	45	0	1	0	2	26712	2	12	12	16	25	80100	100	80000	100	80000	500	1165789	49	23627	26707	26727	16650	3	16685	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80000	0	39	80000	6	0	0	0	5110	2	16	2	2	26719	6	6	2	80000	100	26734	26736	26726	26731	26739
80204	26726	200	0	0	0	0	0	0	0	0	0	0	2	26712	0	12	12	16	25	80100	100	80000	100	80000	500	1166525	49	23627	26727	26727	16630	3	16685	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	39	0	80035	0	39	80039	6	1	39	43	5110	2	16	2	2	26704	0	0	4	80000	100	26728	26723	26708	26728	26708
80204	26722	201	0	0	0	0	0	0	0	0	0	0	2	26712	0	0	18	0	25	80100	100	80000	100	80000	500	1166525	49	23642	26722	26707	16630	3	16685	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	39	80039	6	0	35	43	5110	2	16	2	2	26719	6	6	4	80000	100	26728	26723	26728	26728	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	0	1	1	0	41	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1166750	1	49	23628	26722	26708	16667	3	16798	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80035	0	35	80035	6	1	35	0	0	5020	3	16	2	3	26729	0	9	9	2	80000	10	26733	26733	26734	26723	26723
80024	26708	200	0	0	0	0	41	1	0	2	26693	0	0	18	12	25	80010	10	80000	10	80000	50	1167605	1	49	23628	26722	26722	16652	3	16774	80010	20	80000	20	80000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	80035	6	1	35	39	0	5020	3	16	2	4	26729	0	0	0	2	80000	10	26709	26709	26723	26723	26723
80024	26722	200	0	0	0	0	41	0	0	1	26693	0	18	0	12	25	80010	10	80000	10	80000	50	1172240	1	49	23642	26708	26722	16667	3	16794	80010	20	80000	20	80000	26722	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	0	80035	6	1	0	39	0	5020	3	16	3	2	26712	0	9	9	0	80000	10	26723	26723	26709	26709	26723
80024	26708	200	0	0	0	0	41	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26708	26722	16667	3	16784	80010	20	80000	20	80000	26722	72	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	80035	6	1	0	0	0	5020	4	16	3	3	26712	0	0	9	0	80000	10	26723	26723	26709	26723	26723
80024	26722	200	0	0	0	0	45	0	0	0	26707	0	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26708	26708	16667	3	16715	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80036	0	35	80039	6	1	35	39	0	5020	3	16	3	2	26711	0	0	0	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	0	41	1	0	0	26707	0	18	18	13	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26722	26708	16667	3	16702	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	35	80000	6	1	35	0	0	5020	3	16	3	3	26712	0	0	0	2	80000	10	26739	26723	26726	26709	26709
80024	26708	200	0	0	0	0	41	1	0	0	26707	2	18	18	0	48	80010	10	80000	10	80000	50	1167605	1	49	23642	26722	26722	16667	3	16806	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	1	35	80035	6	1	0	39	0	5020	3	16	3	3	26730	0	9	9	2	80000	10	26733	26733	26723	26709	26709
80024	26708	200	0	0	1	0	41	1	0	1	26693	2	18	0	12	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26722	26722	16667	3	16792	80010	20	80000	20	80000	26722	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	35	80035	6	1	35	0	0	5020	2	16	2	4	26729	0	9	9	2	80000	10	26723	26723	26709	26709	26723
80024	26722	200	0	0	0	0	42	1	0	0	26707	2	18	18	0	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26722	26722	16667	3	16800	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	35	80035	6	1	35	39	0	5020	3	16	2	3	26729	0	9	9	2	80000	10	26820	26723	26709	26709	26709
80024	26722	201	0	0	0	0	0	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1172240	1	49	23642	26722	26722	16667	3	16789	80010	20	80000	20	80000	26722	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	80035	0	35	80035	6	1	35	39	0	5020	2	16	4	2	26729	0	0	9	2	80000	10	26733	26723	26723	26723	26723

LDURSB (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations