Firestorm: MRS (TPIDRRO_EL0) measurements

Code:

  mrs x0, tpidrro_el0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1034	8	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	3	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	8	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	8	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	8	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	8	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	8	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	3	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	7	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	1	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	8	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	8	24	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035
1004	1034	7	0	1019	26	1000	1000	0	1034	1034	865	3	882	1034	164	1	1	1001	0	0	73	2	26	2	2	1031	1000	1000	1035	1035	1035	1035	1035

Count: 8

Code:

  mrs x0, tpidrro_el0
  mrs x1, tpidrro_el0
  mrs x2, tpidrro_el0
  mrs x3, tpidrro_el0
  mrs x4, tpidrro_el0
  mrs x5, tpidrro_el0
  mrs x6, tpidrro_el0
  mrs x7, tpidrro_el0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd store (99)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80204	80039	621	0	0	0	12	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	621	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	621	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	2	0	0	0	0	0	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80069	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	1	0	0	0	0	0	5110	3	25	3	3	80075	80000	0	80100	80036	80036	80080	80036	80036
80204	80035	621	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	12	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	1	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	69984	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80032	80000	0	80100	80036	80036	80036	80036	80036
80204	80035	620	0	0	0	0	0	80020	26	80100	80100	100	500	0	49	76955	80035	80035	69966	3	70015	100	200	200	80035	164	1	1	80201	100	99	100	100	0	100	0	0	0	0	0	0	0	0	0	5110	3	25	3	3	80032	80000	1	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	80050	621	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	0	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	3	25	3	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	620	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	0	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	2	25	2	3	80032	80000	80010	80036	80043	80036	80036	80036
80024	80035	621	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	1	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	3	25	3	2	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	620	1	1	0	0	12	0	1	80020	26	80010	80010	10	50	0	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	3	25	2	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	621	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	0	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	2	25	3	2	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	623	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	1	49	76955	0	80035	80035	69988	3	70038	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	3	25	3	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	620	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	0	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	1	0	0	0	0	5022	3	25	3	3	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	621	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	0	49	76955	0	80035	80035	69992	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	3	25	3	2	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	621	1	1	0	0	12	0	1	80020	26	80010	80010	10	50	1	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	2	25	3	2	80032	80000	80010	80036	80036	80036	80036	80036
80024	80035	620	1	1	0	0	0	0	1	80020	26	80010	80010	10	50	0	49	76955	0	80035	80035	69988	3	70006	10	20	20	80035	164	1	1	80021	10	9	10	10	10	0	0	0	0	0	0	0	0	5022	2	25	3	3	80032	80000	80010	80036	80036	80036	80036	80036

MRS (TPIDRRO_EL0)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations