Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ISB (SY)

Test 1: uops

Code:

  isb sy

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f5160696a6d6emap rewind (75)map stall (76)8283flush restart other nonspec (84)85inst all (8c)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0f5f6f7f8fd
40042802621000280112702414924946280262802630039010280262802610011001100100600631801322280232802728027280272802728027
40042802621000280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728027
40042802621000280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728027
40042802621000280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728048
40042802620900280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728027
40042802620900280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728027
40042802621000280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728027
40042802621000280112702414924946280262802630039010280262802610021001100100600621801322280232802728027280272802728027
40042802621000280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728027
40042802621000280112702414924946280262802630039010280262802610011001100100600621801322280232802728027280272802728027

Test 2: throughput

Code:

  isb sy

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 28.0134

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
402042801602099006361924951040284012273847100100100500049281150284151284206301269119610020220028013428013410001100011020110099100100100000000000601051421800154244280131100280135280135280135280135280135
40204280160209900000016280119269727100100100500049277054280134280134300039001810020020028013428013410001100011020110099100100100000000000601051441800154244280131100280135280135280135280135280135
40204280134209900000016280119269753100100100500049277054280134280134300039001810020020028013428013410001100011020110099100100100000000000601051441800154244280131100280135280135280135280135280159
40204280134209800000016280119269727100100100500049277054280134280134300039001810020020028013428013410001100011020110099100100100000000000601051441800154244280131100280135280135280135280135280135
40204280134209900000016280119269727100100100500049277054280134280134300039001810020020028013428013410001100011020110099100100100000003000601051441800154244280131100280135280135280135280135280135
40204280134209800000016280119269727100100100500049277054280134280134300099001810020020028013428013410001100011020110099100100100000000000601051381800154345280131100280135280135280135280135280135
40204280134209800000016280119269727100100100500149277054280134280134300039001810020020028013428013410001100011020110099100100100000000020601051451800154345280131100280135280135280135280135280135
402042801342099000012016280119269727100100100500049277054280135280134300039001810020020028013428013410001100011020110099100100100000000000601051451800154345280131100280135280135280135280135280135
402042801342099000039016280119269727100100100500098277054280134280134300039001810020020028013428013410001100011020110099100100100000000000601051451800154345280131100280135280135280135280135280135
40204280134209800000016280119269727100100100500049277054280134280134300039001810020020028013428013410001100011020110099100100100000000000601051441800153744280131100280135280135280135280135280135

1000 unrolls and 10 iterations

Result (median cycles for code): 28.0044

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int retires (ef)f5f6f7f8fd
4002428005920971000000002800292699971010105004927696402800442800443000390018102020280044280044100011000110021109101010000000106001540180015414128004110280045280045280045280045280045
4002428004420980000000002800292699971010105004927696402800442800443000390018102020280044280044100011000110021109101010001002006003542180544424128085310280045280629280295280045280045
400242800442098100000035202800292699971010105004927696402800442800443000390018102020280044280044100011000110021109101010000000006002542180015474228004110280045280045280045280045280045
400242800442098000000000280029269997101010500982769640280044280070300039001810202028004428004410001100011002110910101000000000600154118001540428004110280045280045280045280045280045
4002428004420980000000002800292699971010105004927696402800442800443000390018102020280044280044100011000110021109101010000000006001543180015444328004110280045280045280045280045280045
4002428004420981010000002800292699971010105004927696402800442800443000390018102020280044280044100011000110021109101010002000006001542180015404128004110280045280045280045280045280045
4002428004421611000000002800292699971010105004927696402800442800443000390032102020280044280044100011000110021109101010000000006001542180015424228004110280045280045280045280045280045
4002428004420980010000002800292699971010105004927696402800442800443000390018102020280044280044100011000110021109101010000000006001540180015424128004110280045280045280045280045280045
400242800442098000000000280029269997101010500492769640280044280044300039001810202028004428006610001100011002110910101000002010006001542180015424228004110280046280045280045280045280045
4002428004420981000000002800292699971010105004927696402800442800443000390018102020280070280044100011000110021109101010000000006001541180015414228004110280071280045280045280045280045