Firestorm: ISB (SY) measurements

Code:

  isb sy

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	60	69	6a	6d	6e	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	3	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28048
4004	28026	209	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	209	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1002	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027
4004	28026	210	0	0	28011	27024	1	49	24946	28026	28026	3003	9010	28026	28026	1001	1001	1001	0	0	6006	2	18013	2	2	28023	28027	28027	28027	28027	28027

Code:

  isb sy

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 28.0134

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
40204	280160	2099	0	0	63	61	9249	5104	0	284012	273847	100	100	100	500	0	49	281150	284151	284206	30126	91196	100	202	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	42	180015	42	44	280131	100	280135	280135	280135	280135	280135
40204	280160	2099	0	0	0	0	0	0	16	280119	269727	100	100	100	500	0	49	277054	280134	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	44	180015	42	44	280131	100	280135	280135	280135	280135	280135
40204	280134	2099	0	0	0	0	0	0	16	280119	269753	100	100	100	500	0	49	277054	280134	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	44	180015	42	44	280131	100	280135	280135	280135	280135	280159
40204	280134	2098	0	0	0	0	0	0	16	280119	269727	100	100	100	500	0	49	277054	280134	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	44	180015	42	44	280131	100	280135	280135	280135	280135	280135
40204	280134	2099	0	0	0	0	0	0	16	280119	269727	100	100	100	500	0	49	277054	280134	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	3	0	0	0	60105	1	44	180015	42	44	280131	100	280135	280135	280135	280135	280135
40204	280134	2098	0	0	0	0	0	0	16	280119	269727	100	100	100	500	0	49	277054	280134	280134	30009	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	38	180015	43	45	280131	100	280135	280135	280135	280135	280135
40204	280134	2098	0	0	0	0	0	0	16	280119	269727	100	100	100	500	1	49	277054	280134	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	2	0	60105	1	45	180015	43	45	280131	100	280135	280135	280135	280135	280135
40204	280134	2099	0	0	0	0	12	0	16	280119	269727	100	100	100	500	0	49	277054	280135	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	45	180015	43	45	280131	100	280135	280135	280135	280135	280135
40204	280134	2099	0	0	0	0	39	0	16	280119	269727	100	100	100	500	0	98	277054	280134	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	45	180015	43	45	280131	100	280135	280135	280135	280135	280135
40204	280134	2098	0	0	0	0	0	0	16	280119	269727	100	100	100	500	0	49	277054	280134	280134	30003	90018	100	200	200	280134	280134	10001	10001	10201	100	99	100	100	100	0	0	0	0	0	0	0	0	0	60105	1	44	180015	37	44	280131	100	280135	280135	280135	280135	280135

1000 unrolls and 10 iterations

Result (median cycles for code): 28.0044

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
40024	280059	2097	1	0	0	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	1	0	60015	40	180015	41	41	280041	10	280045	280045	280045	280045	280045
40024	280044	2098	0	0	0	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	1	0	0	2	0	0	60035	42	180544	42	41	280853	10	280045	280629	280295	280045	280045
40024	280044	2098	1	0	0	0	0	0	0	352	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	0	0	60025	42	180015	47	42	280041	10	280045	280045	280045	280045	280045
40024	280044	2098	0	0	0	0	0	0	0	0	0	280029	269997	10	10	10	50	0	98	276964	0	280044	280070	30003	90018	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	0	0	60015	41	180015	40	4	280041	10	280045	280045	280045	280045	280045
40024	280044	2098	0	0	0	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	0	0	60015	43	180015	44	43	280041	10	280045	280045	280045	280045	280045
40024	280044	2098	1	0	1	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	2	0	0	0	0	0	60015	42	180015	40	41	280041	10	280045	280045	280045	280045	280045
40024	280044	2161	1	0	0	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90032	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	0	0	60015	42	180015	42	42	280041	10	280045	280045	280045	280045	280045
40024	280044	2098	0	0	1	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280044	280044	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	0	0	60015	40	180015	42	41	280041	10	280045	280045	280045	280045	280045
40024	280044	2098	0	0	0	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280044	280066	10001	10001	10021	10	9	10	10	10	0	0	0	0	201	0	0	0	60015	42	180015	42	42	280041	10	280046	280045	280045	280045	280045
40024	280044	2098	1	0	0	0	0	0	0	0	0	280029	269997	10	10	10	50	0	49	276964	0	280044	280044	30003	90018	10	20	20	280070	280044	10001	10001	10021	10	9	10	10	10	0	0	0	0	0	0	0	0	60015	41	180015	41	42	280041	10	280071	280045	280045	280045	280045

ISB (SY)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations