Firestorm: LDRSW (register, sxtw) measurements

Code:

  ldrsw x0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	374	3	0	0	0	0	0	65	0	0	1	384	2	18	18	15	25	1000	1000	1000	14060	0	374	391	212	3	257	1000	1000	2000	408	81	1	1	1001	1000	1000	0	1000	0	0	1039	0	0	0	0	1035	6	1	57	0	19	2	73	1	16	1	1	371	10	6	4	1000	375	375	375	395	390
1004	394	3	0	0	0	0	0	41	1	0	2	374	0	12	12	12	25	1000	1000	1000	14060	0	394	394	197	3	252	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	0	39	1000	0	0	0	0	1039	0	0	0	43	0	0	73	1	16	1	1	371	10	10	4	1000	395	375	375	390	395
1004	374	3	0	0	0	0	0	45	0	0	2	379	2	0	12	0	25	1000	1000	1000	15037	0	394	394	217	3	252	1000	1000	2000	374	71	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	39	1000	6	0	39	43	0	0	73	1	16	1	1	371	10	0	4	1000	395	395	375	375	375
1004	394	3	0	0	0	1	0	45	0	0	2	374	2	0	0	0	25	1000	1000	1000	14060	1	394	394	217	3	252	1000	1000	2000	381	71	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	42	1000	6	0	35	43	0	0	73	1	16	1	1	391	10	0	4	1000	395	375	395	375	375
1004	374	3	0	0	0	0	0	45	0	0	2	374	2	12	12	12	25	1000	1000	1000	14989	0	394	394	216	3	252	1000	1000	2000	389	72	1	1	1001	1000	1000	0	1000	0	0	1039	0	0	0	39	1035	6	1	35	39	0	0	73	1	16	1	1	391	10	6	0	1000	395	395	395	375	395
1004	389	3	0	0	0	0	0	41	0	0	0	359	0	0	12	16	25	1000	1000	1000	15037	0	374	394	197	3	253	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	39	1035	0	0	0	0	0	0	73	1	16	1	1	371	10	10	4	1000	395	395	390	395	395
1004	374	3	0	0	0	0	0	45	0	0	0	374	2	12	12	0	25	1000	1000	1000	14838	1	374	374	197	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	0	1000	0	0	0	35	1035	6	1	0	43	0	0	73	1	16	1	1	371	10	10	4	1000	395	395	375	395	395
1004	394	3	0	0	0	0	0	45	0	0	1	379	2	12	0	16	25	1000	1000	1000	14989	0	394	394	197	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	1039	0	0	0	39	1000	0	0	39	0	0	0	73	1	16	1	1	390	10	0	4	1000	395	395	375	395	379
1004	374	3	0	0	0	0	0	45	0	0	0	374	2	12	12	0	25	1000	1000	1000	15037	0	394	394	197	3	252	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	35	1000	0	0	35	0	0	0	73	1	16	1	1	391	6	6	2	1000	375	375	395	375	392
1004	394	3	0	0	0	1	1	0	0	0	2	359	2	0	0	16	25	1000	1000	1000	14060	0	394	374	216	3	232	1000	1000	2000	394	71	1	1	1001	1000	1000	0	1000	0	0	1000	0	0	0	0	1039	0	0	0	0	0	0	73	1	16	1	1	371	10	0	4	1000	390	395	375	375	375

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	1	0	0	0	0	1069	1	0	70020	69735	59709	25	40104	30103	10001	30100	10000	616015	3342062	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	10000	1	1	0	0	2610	2	71	2	2	69813	30003	6	0	9	10000	30100	70051	70048	70051	70051	70036
40204	70035	525	0	0	0	0	0	0	846	1	0	70032	69781	59709	25	40104	30103	10000	30100	10000	616175	3342206	49	66970	70050	70050	64631	3	64956	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	1	0	10000	0	1	0	0	2610	2	71	2	2	69813	30003	9	6	9	10000	30100	70051	70051	70036	70051	70051
40204	70050	525	0	0	0	0	0	0	861	1	0	70036	69764	59711	25	40149	30100	10001	30100	10000	616005	3342206	49	66955	70035	70050	64646	3	65008	40100	30200	10000	61180	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	10000	1	1	0	0	2610	2	71	2	2	69798	30003	9	9	9	10000	30100	70036	70051	70051	70051	70051
40204	70050	524	0	0	0	0	0	0	841	1	0	70035	69781	59709	25	40100	30103	10001	30100	10000	616175	3342446	49	66967	70050	70035	64643	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	10000	1	0	0	0	2610	2	71	2	2	69813	30000	0	6	0	10000	30100	70051	70051	70051	70036	70051
40204	70050	524	0	0	0	0	0	0	850	1	0	70035	69735	59709	25	40100	30103	10001	30100	10000	616015	3342206	49	66967	70050	70050	64643	36	64951	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	1	2610	2	71	2	2	69813	30003	6	6	6	10000	30100	70051	70036	70048	70036	70036
40204	70054	524	0	0	0	0	0	0	880	0	0	70032	69781	59695	25	40100	30103	10000	30100	10000	616005	3342206	49	66970	70050	70050	64646	3	64955	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	2610	2	71	2	2	69810	30003	9	0	0	10000	30100	70051	70051	70051	70051	70051
40204	70050	525	0	0	0	0	0	0	865	1	0	70032	69735	59695	25	40100	30103	10001	30100	10000	616175	3341470	49	66970	70047	70050	64646	3	64955	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	10000	1	0	0	0	2610	2	71	2	2	69798	30003	9	0	9	10000	30100	70051	70048	70051	70051	70051
40204	70050	524	0	0	0	0	0	0	849	1	0	70032	69735	59706	25	40100	30103	10001	30100	10000	616005	3342206	49	66970	70047	70035	64643	3	64955	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	2610	2	71	2	2	69813	30003	0	0	9	10000	30100	70048	70036	70048	70036	70036
40204	70035	525	0	0	0	0	0	0	892	0	0	70035	69781	59706	25	40104	30100	10000	30100	10000	616005	3342206	49	66956	70050	70039	64631	3	64951	40100	30200	10000	60200	20000	70049	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	1	0	0	2610	2	71	2	2	69798	30003	9	6	0	10000	30100	70051	70051	70036	70048	70051
40204	70050	525	0	0	0	0	0	0	802	0	0	70035	69781	59695	25	40104	30100	10000	30100	10000	616015	3342206	49	66970	70050	70050	64631	36	64956	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	3	10000	1	1	0	0	2610	1	71	2	2	69798	30003	0	6	6	10000	30100	70036	70051	70039	70051	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70050	524	0	0	1	0	1	0	1	0	70040	69728	59708	25	40010	30013	10002	30010	10000	616952	3341470	0	0	49	66967	70047	70047	64665	3	64973	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	3	10012	1	1	0	2520	2	71	3	2	69810	30003	6	0	6	10000	30010	70036	70036	70048	70048	70036
40024	70047	524	0	0	0	0	48	0	1	0	70071	69743	59696	25	40014	30013	10001	30010	10000	616952	3341470	0	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	2	71	3	2	69810	30003	0	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	0	1	0	1	0	70059	69728	59706	25	40014	30010	10000	30010	10000	616952	3342062	0	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	3	10012	1	1	0	2520	3	71	3	2	69810	30003	6	6	6	10000	30010	70038	70048	70048	70048	70048
40024	70035	525	0	0	0	0	0	0	1	0	70032	69728	59706	25	40014	30013	10000	30010	10000	616952	3342062	0	0	49	66967	70035	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	3	71	3	2	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70036
40024	70047	525	0	0	0	0	6	0	0	0	70032	69743	59695	25	40014	30013	10001	30010	10000	616952	3342062	0	0	49	66967	70035	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	3	71	3	2	69810	30003	6	6	6	10000	30010	70036	70048	70048	70048	70036
40024	70047	525	0	0	0	0	1	0	1	0	70032	69728	59706	25	40014	30013	10000	30010	10000	616952	3342062	0	0	49	67334	70047	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	2520	3	71	3	2	69810	30000	6	6	6	10000	30010	70052	70048	70048	70036	70048
40024	70035	524	0	0	1	0	0	0	0	0	70055	69735	59709	25	40014	30013	10001	30010	10000	617068	3342062	0	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	8991	10000	1	1	0	2520	2	71	2	3	69810	30003	6	0	6	10000	30010	70048	70048	70048	70048	70048
40024	70035	525	0	0	0	0	40	0	1	0	70032	69731	59706	25	40014	30010	10000	30010	10000	616952	3342062	1	0	49	66967	70047	70047	64665	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	2	71	2	2	69817	30003	6	6	6	10000	30010	70048	70053	70048	70036	70048
40024	70047	525	0	0	1	1	1	0	1	0	70032	69728	59695	25	40014	30013	10001	30010	10000	616952	3342062	0	1	49	66955	70047	70035	64653	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	2	71	2	2	69810	30003	6	6	6	10000	30010	70036	70036	70036	70048	70048
40024	70052	525	1	0	0	0	565	0	1	0	70020	69728	59706	25	40010	30013	10001	30010	10000	616952	3342062	0	0	49	66967	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70048	35	5	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	10000	1	1	0	2520	2	71	3	2	69810	30003	6	6	6	10000	30010	70036	70048	70048	70048	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	0	0	0	0	0	1	0	2	0	0	0	70042	69792	59776	25	40104	30103	10002	30100	10000	616078	3342542	49	66961	0	70057	70057	64660	3	64967	40100	30200	10000	60200	20000	70041	36	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	0	0	2610	1	71	1	1	69824	30006	0	10	13	10000	30100	70042	70058	70099	70069	70042
40204	70041	524	1	1	0	1	0	0	0	2	0	0	0	70045	69773	59719	25	40108	30106	10002	30100	10000	616095	3341769	49	66980	0	70060	70060	64657	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10001	0	0	1	10000	1	1	0	1	1	0	0	2610	1	71	1	1	69823	30006	13	0	13	10000	30100	70061	70058	70140	70092	70061
40204	70060	524	1	1	1	1	0	0	0	2	1	0	0	70042	69802	59716	25	40108	30106	10002	30100	10000	616095	3342686	49	66961	0	70041	70041	64663	3	64963	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10003	0	1	1	10000	1	1	1	1	1	0	0	2610	1	71	1	1	69823	30006	13	13	10	10000	30100	70061	70134	70066	70049	70061
40204	70060	524	1	1	0	1	0	0	0	1	0	0	1	70042	69860	59865	25	40108	30106	10002	30100	10000	616095	3342686	49	66980	0	70060	70060	64656	3	64968	40100	30200	10000	60200	20000	70183	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	0	178	10000	1	1	1	1	0	0	0	2610	1	71	1	1	69864	30006	13	13	10	10000	30100	70042	70114	70074	70089	70042
40204	70060	525	1	1	1	1	0	0	0	2	0	0	0	70042	69815	59719	25	40129	30103	10004	30100	10000	616095	3342686	98	67054	0	70041	70060	64656	3	64963	40100	30200	10000	60200	20000	70060	36	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10002	0	1	1	10000	0	1	1	1	0	0	0	2645	3	64	1	1	69823	30006	13	13	0	10000	30100	70062	70058	70058	70061	70061
40204	70060	525	1	1	0	0	0	0	0	2	0	0	0	70026	69791	59716	25	40133	30106	10002	30100	10000	616510	3342686	49	66980	0	70041	70057	64663	3	64944	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	3	0	10002	0	1	4	10000	1	1	0	1	0	0	0	2610	1	71	1	1	69804	30003	13	10	10	10000	30100	70061	70062	70042	70061	70042
40204	70041	525	1	1	0	1	0	0	0	2	1	0	0	70042	69791	59701	25	40108	30103	10001	30125	10000	616510	3342686	49	66961	0	70097	70041	64656	3	64944	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	0	0	2610	1	71	1	1	69823	30006	13	13	0	10000	30100	70066	70062	70061	70061	70042
40204	70060	524	1	0	0	1	1	0	0	2	0	0	0	70045	69791	59701	25	40108	30106	10001	30100	10000	616095	3341769	49	66980	0	70060	70060	64637	3	64963	40100	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	0	10001	0	0	1	10000	1	1	0	1	0	0	0	2610	1	71	1	1	69823	30003	0	0	0	10000	30100	70060	70062	70061	70061	70061
40204	70060	525	1	0	1	0	0	0	0	2	1	0	0	70045	69708	59716	25	40104	30106	10002	30100	10000	616078	3342686	49	66980	0	70057	70057	64653	3	64970	40125	30200	10000	60200	20000	70060	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	1	0	10003	1	0	1	10000	0	1	0	1	0	0	0	2610	1	71	1	1	69804	30006	13	10	13	10000	30100	70043	70059	70058	70061	70058
40204	70041	524	1	0	1	1	0	0	0	2	0	0	0	70026	69708	59719	25	40108	30103	10002	30125	10000	616434	3342542	49	66977	0	70060	70041	64653	3	64944	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	1	1	10003	0	1	1	10000	1	1	1	1	0	0	0	2610	1	71	1	1	69823	30003	0	13	13	10000	30100	70058	70061	70042	70042	70062

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70057	525	1	0	1	1	0	0	0	0	2	0	1	0	1	70055	69784	59716	25	40014	30016	10002	30010	10000	617072	3342686	0	0	49	66977	70057	70060	64659	3	64985	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	2	1	10002	0	0	1	10000	1	1	1	1	0	2520	9	71	0	0	2	2	69804	30003	13	10	13	10000	30010	70042	70042	70061	70042	70061
40024	70057	524	1	1	1	0	0	0	0	0	2	0	0	0	1	70026	69784	59701	25	40018	30016	10001	30010	10000	616995	3342686	0	0	49	66961	70060	70057	64678	3	64966	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	3	1	10001	0	0	1	10000	0	1	1	1	1	2520	3	71	0	0	6	2	69823	30049	0	10	13	10000	30010	70061	70061	70058	70042	70042
40024	70078	524	1	0	1	2	0	0	0	0	41	0	0	0	1	70026	69702	59719	25	40018	30013	10001	30010	10000	617072	3342542	0	1	49	66980	70057	70057	64659	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10001	0	0	1	10000	0	1	1	1	1	2520	2	71	0	0	2	3	69823	30006	13	0	10	10000	30010	70061	70061	70058	70061	70061
40024	70060	525	1	1	1	1	0	0	0	0	2	0	1	0	1	70150	69784	59719	25	40018	30016	10001	30010	10000	617072	3341769	0	1	49	66977	70041	70057	64678	3	64966	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	0	10002	0	1	1	10000	0	1	1	1	0	2520	6	71	0	0	6	2	69823	30006	13	0	13	10000	30010	70042	70061	70061	70061	70061
40024	70041	525	1	0	0	1	0	0	0	0	2	0	1	0	1	70045	69784	59716	25	40014	30016	10002	30010	10000	616995	3341769	0	0	49	66977	70041	70041	64678	3	64966	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	2	4	10000	1	1	0	1	2	2520	2	71	0	0	6	6	69823	30006	13	10	13	10000	30010	70061	70061	70061	70061	70042
40024	70041	525	1	0	0	0	0	0	0	0	2	0	1	0	1	70043	69702	59719	25	40018	30016	10002	30010	10000	616995	3342686	1	0	49	66980	70057	70041	64678	3	64985	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	3	1	10002	0	0	1	10000	0	1	1	1	0	2520	6	71	0	0	2	2	69823	30006	10	10	13	10000	30010	70042	70061	70058	70042	70061
40024	70060	525	1	0	1	1	0	0	0	0	7	0	1	0	1	70045	69702	59701	25	40014	30013	10001	30010	10000	617072	3341769	0	0	49	66977	70060	70060	64678	3	64966	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10001	1	1	10003	0	0	1	10000	1	1	1	1	0	2520	2	71	0	0	3	6	69823	30006	13	13	0	10000	30010	70042	70042	70061	70058	70061
40024	70060	524	1	1	0	0	0	0	0	0	1	0	1	0	1	70026	69781	59719	25	40018	30016	10002	30010	10000	617045	3341769	0	0	49	66977	70057	70041	64675	3	64982	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	0	10002	0	0	4	10000	1	1	0	1	0	2520	2	71	0	0	2	2	69823	30006	13	13	10	10000	30010	70061	70061	70061	70061	70061
40024	70060	524	1	0	0	1	0	0	0	0	2	0	1	0	1	70045	69784	59719	25	40018	30016	10002	30010	10000	617072	3342542	0	0	49	66980	70060	70057	64678	3	65037	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10003	0	0	1	10000	1	1	1	1	0	2520	2	71	0	0	2	2	69823	30006	10	0	0	10000	30010	70061	70042	70042	70061	70061
40024	70041	524	1	0	0	0	0	0	0	0	2	0	0	0	1	70042	69784	59719	25	40018	30016	10002	30010	10000	616995	3342686	0	0	49	66977	70060	70041	64659	3	64966	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10002	0	0	1	10000	1	1	1	1	0	2520	2	71	0	0	2	2	69823	30003	13	13	10	10000	30010	70061	70044	70061	70061	70058

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	1	1	0	0	0	0	66	1	0	3	26717	2	18	18	78	25	80100	100	80000	100	80015	500	1159191	1	49	23652	26732	26733	16660	6	16684	80115	200	80024	200	160048	26732	82	1	1	80201	100	99	100	80000	100	80000	1	100	80021	19	42	80057	1	0	0	59	80038	6	1	57	42	19	1	1	1	1	5118	2	16	3	4	26730	9	9	2	80000	100	26737	26715	26813	26715	26734
80204	26733	200	1	1	0	0	1	0	0	65	0	0	2	26717	2	0	18	15	25	80100	100	80000	100	80015	500	1167763	0	49	23652	26732	26732	16660	6	16666	80116	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	1	100	80019	20	42	80057	0	0	0	59	80038	6	1	56	42	19	2	1	1	1	5118	3	16	3	4	26730	9	9	2	80000	100	26739	26736	26739	26742	26733
80204	26732	201	1	1	1	0	0	0	0	66	0	0	2	26699	0	18	18	17	25	80100	100	80000	100	80016	500	1167095	0	49	23652	26732	26732	16659	6	16684	80115	200	80024	200	160048	26732	82	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	42	80057	0	0	1	59	80038	6	1	57	42	19	0	1	1	1	5118	3	16	3	4	26729	9	9	2	80000	100	26739	26737	26721	26742	26733
80204	26733	200	1	0	1	0	0	0	0	65	0	0	3	26699	2	18	18	23	25	80100	100	80000	100	80016	500	1166590	0	49	23652	26714	26732	16660	6	16684	80117	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	1	100	80019	20	42	80058	1	0	0	59	80038	6	0	56	42	19	1	1	1	1	5118	3	16	2	4	26730	9	9	2	80000	100	26734	26733	26733	26869	26740
80204	26732	200	1	0	1	0	0	0	0	65	0	0	3	26699	2	18	0	95	25	80100	100	80000	100	80014	500	1169418	1	49	23652	26733	26733	16660	6	16666	80115	200	80024	200	160048	26733	64	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	0	80019	1	0	0	59	80038	0	0	19	42	19	0	1	1	1	5146	4	16	4	5	26711	9	9	2	80000	100	26733	26740	26859	26735	26733
80204	26733	200	1	1	0	0	0	0	0	65	1	0	3	26717	2	18	18	19	25	80100	100	80000	100	80015	500	1167107	0	49	23653	26732	26733	16660	6	16684	80116	200	80024	200	160048	26732	82	1	1	80201	100	99	100	80000	100	80000	1	100	80019	20	42	80058	1	0	1	59	80037	6	1	57	42	19	1	1	1	1	5118	4	16	4	3	26729	9	9	2	80000	100	26738	26734	26739	26743	26733
80204	26732	200	1	0	0	0	0	0	0	65	1	0	2	26699	2	18	0	17	25	80100	100	80000	100	80015	500	1168190	0	49	23653	26732	26733	16660	6	16687	80114	200	80024	200	160048	26732	82	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	42	80057	0	0	1	0	80036	6	1	35	39	0	0	1	1	1	5118	3	16	4	3	26704	0	6	4	80000	100	26732	26726	26729	26732	26728
80204	26722	200	0	0	0	0	0	0	0	41	1	0	1	26707	2	12	18	12	25	80100	100	80000	100	80014	500	1167875	0	49	23627	26722	26722	16635	6	16659	80115	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	0	0	35	80035	6	0	35	43	0	0	1	1	1	5118	2	16	4	4	26719	10	6	4	80000	100	26729	26727	26729	26732	26708
80204	26722	200	0	0	0	0	0	0	0	45	0	0	0	26707	2	12	18	14	25	80100	100	80000	100	80015	500	1167875	0	49	23642	26722	26707	16650	6	16679	80114	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	80039	0	30	0	38	80035	6	1	35	39	0	0	1	1	1	5118	2	16	2	4	26719	6	6	2	80000	100	26727	26728	26872	26725	26723
80204	26722	199	0	0	0	1	1	0	0	0	1	0	1	26707	2	18	0	12	25	80100	100	80000	100	80016	500	1177165	0	49	23642	26727	26722	16650	6	16679	80114	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	80035	0	0	0	35	80035	6	1	35	43	0	0	1	1	1	5118	3	16	4	3	26719	6	6	2	80000	100	26734	26711	26791	26728	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26724	200	0	0	0	41	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	1	49	23642	0	26722	26708	16667	3	16702	80010	20	80000	20	160000	26804	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	0	80035	6	1	35	39	5020	7	16	2	2	26719	6	6	2	80000	10	26723	26709	26723	26723	26723
80024	26722	200	0	0	0	41	1	0	1	26707	0	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	0	49	23628	0	26722	26722	16667	3	16702	80010	20	80000	20	160000	26785	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	35	80035	6	1	35	39	5020	2	16	6	3	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	1	0	41	1	0	1	26707	2	18	18	11	25	80010	10	80000	10	80000	50	1167605	0	0	49	23642	0	26722	26722	16667	3	16702	80010	20	80000	20	160000	26736	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	0	80035	6	1	35	39	5020	2	16	3	2	26705	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	41	1	0	1	26707	2	18	18	110	25	80010	10	80000	10	80000	50	1167605	0	0	49	23642	0	26723	26722	16667	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	35	80035	6	1	0	39	5020	2	16	2	6	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	41	1	0	0	26707	2	18	18	11	25	80010	10	80000	10	80000	50	1166750	0	0	49	23645	0	26722	26722	16667	3	16702	80010	20	80000	20	160000	26787	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	35	80000	6	1	35	39	5052	2	16	2	2	26719	6	6	2	80000	10	26723	26723	26723	26709	26723
80024	26722	200	0	0	0	41	0	0	1	26707	2	18	18	11	25	80010	10	80000	10	80000	50	1166750	0	0	49	23642	0	26722	26722	16667	3	16702	80010	20	80000	20	160000	26792	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	35	80035	6	1	35	39	5020	6	16	2	6	26719	6	6	2	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	0	0	41	1	0	0	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1166993	0	0	49	23642	0	26722	26722	16667	3	16702	80010	20	80000	20	160000	26835	72	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	35	80035	6	1	35	39	5020	2	16	3	6	26719	6	6	2	80000	10	26709	26723	26723	26723	26709
80024	26722	200	0	0	0	41	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	0	49	23642	0	26722	26722	16668	3	16702	80010	20	80000	20	160000	26965	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	35	80035	6	1	35	39	5020	6	16	2	6	26721	6	6	2	80000	10	26723	26723	26723	26723	26729
80024	26722	200	0	0	0	41	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	0	0	49	23642	0	26722	26722	16667	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	35	80035	0	1	35	39	5020	6	16	3	2	26720	6	6	0	80000	10	26723	26723	26723	26723	26723
80024	26722	200	0	1	0	41	1	0	1	26707	2	18	0	12	49	80140	10	80000	10	80000	50	1167605	0	0	49	23642	0	26722	26722	16667	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	1	35	80035	6	1	35	39	5020	6	16	2	2	26721	6	6	2	80000	10	26723	26723	26723	26723	26723

LDRSW (register, sxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations