Firestorm: LDRSB (register, sxtw, 64-bit) measurements

Code:

  ldrsb x0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	389	3	0	0	1	41	0	1	0	1	374	2	18	18	12	25	1000	1000	1000	14774	389	389	212	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	393	390	390	390	390
1004	389	3	0	1	1	41	0	0	0	1	374	2	18	18	12	25	1000	1000	1000	14838	389	389	212	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	392	390	390
1004	389	3	0	0	0	41	0	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	389	389	212	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	390	390	390
1004	389	3	0	0	1	41	0	0	0	1	374	2	18	18	11	25	1000	1000	1000	14838	389	389	212	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	390	390	390
1004	389	3	0	0	1	41	0	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	389	389	212	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	392	390	390	390
1004	389	3	0	0	1	41	0	1	0	1	374	2	18	18	11	25	1000	1000	1000	14844	389	389	212	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	388	6	6	2	1000	392	390	406	391	390
1004	389	3	0	0	0	45	0	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	389	391	212	3	247	1000	1000	2000	391	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	392	390	390	390
1004	389	3	0	0	1	47	0	1	0	1	374	2	18	18	11	25	1000	1000	1000	14838	389	389	212	3	247	1000	1000	2000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	390	390	392
1004	389	3	0	0	1	41	0	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	389	391	212	3	247	1000	1000	2000	391	71	1	1	1001	1000	1000	0	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	386	6	6	2	1000	390	390	390	390	390
1004	389	3	0	0	1	41	0	1	0	1	376	2	18	18	12	25	1000	1000	1000	14844	389	391	212	3	247	1000	1000	2000	391	71	1	1	1001	1000	1000	1	1000	39	0	1035	0	0	35	1035	6	1	35	39	73	1	16	1	1	388	6	6	2	1000	392	390	390	390	390

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	66	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	529	1	0	1	1	0	1	1	1	0	0	1	1	0	70039	69774	59713	25	40100	30103	10001	30100	10000	616175	3342398	66	49	66974	70037	70054	64650	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	6	10000	1	1	0	0	2610	1	71	1	1	69817	30000	13	0	10	10000	30100	70056	70057	70146	70059	70036
40204	70035	524	0	0	0	0	0	0	0	0	0	0	1	0	0	70042	69782	59713	25	40104	30119	10001	30100	10000	616175	3342398	0	49	66974	70036	70149	64650	3	64939	40100	30200	10000	60530	20000	70038	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	10000	0	1	2	0	2610	1	74	1	1	69817	30000	13	13	0	10000	30100	70053	70036	70036	70055	70055
40204	70091	524	0	0	0	0	0	0	0	0	0	0	0	0	1	70036	69785	59695	25	40100	30103	10001	30100	10000	616175	3342254	0	49	66974	70054	70051	64650	3	64957	40304	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	10000	1	1	0	0	2610	1	71	1	1	69817	30000	13	13	13	10000	30100	70052	70058	70052	70052	70036
40204	70054	525	0	0	0	0	0	0	0	0	0	0	1	0	1	70039	69788	59713	25	40132	30103	10001	30100	10000	616041	3342398	0	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	0	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69798	30000	13	10	13	10000	30100	70040	70057	70052	70052	70036
40204	70057	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70039	69764	59713	25	40104	30103	10000	30100	10000	616014	3344242	0	49	66974	70051	70054	64650	3	65021	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	2254	10000	1	1	0	0	2610	1	71	1	1	69817	30000	13	13	13	10000	30100	70055	70058	70055	70055	70055
40204	70035	525	0	0	0	0	0	0	0	0	0	0	0	0	0	70058	69792	59713	48	40104	30100	10001	30100	10000	616014	3342398	0	49	66974	70035	70035	64631	3	64938	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	0	0	0	2610	1	71	1	1	69814	30000	13	0	10	10000	30100	70399	70052	70068	70053	70053
40204	70035	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70036	69764	59695	25	40104	30100	10001	30100	10000	616014	3342398	0	49	66971	70054	70057	64651	3	64957	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69814	30003	0	13	0	10000	30100	70059	70055	70052	70055	70055
40204	70035	525	0	0	0	0	0	0	0	0	0	0	1	0	0	70020	69782	59695	25	40104	30103	10001	30100	10000	616041	3342254	0	49	66955	70051	70054	64650	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69817	30006	13	0	13	10000	30100	70119	70053	70055	70052	70036
40204	70035	524	0	0	0	0	0	0	1	0	0	0	0	0	1	70020	69785	59715	51	40104	30103	10001	30100	10000	616014	3341470	0	49	67068	70054	70054	64631	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	2241	10000	1	1	0	0	2610	1	71	1	1	69817	30003	13	0	13	10000	30100	70058	70036	70060	70055	70055
40204	70035	524	0	0	0	0	0	0	1	1	0	0	1	0	0	70020	69764	59710	25	40100	30103	10001	30100	10000	616041	3342254	0	49	66971	70054	70054	64650	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	10000	0	0	0	0	2616	1	71	1	1	69818	30003	10	0	10	10000	30100	70037	70057	70055	70055	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	524	0	0	0	0	1	1	1	0	0	70026	69702	59715	25	40014	30016	10002	30010	10000	617036	3342494	1	49	66967	0	70047	70047	64668	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	3	10000	1	1	0	1	0	0	2525	1	71	1	1	2	69804	30006	9	0	9	10000	30010	70054	70057	70042	70057	70057
40024	70053	524	1	0	1	1	1	0	1	0	0	70039	69728	59695	25	40014	30013	10001	30010	10000	617068	3342206	0	49	66970	0	70050	70035	64665	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	31	0	0	10000	0	0	0	0	0	0	2525	1	71	1	1	2	69798	30003	0	0	9	10000	30010	70051	70051	70049	70054	70051
40024	70037	524	0	0	0	0	0	0	1	0	0	70020	69743	59793	25	40018	30016	10002	30010	10000	617009	3342494	1	49	66961	0	70053	70056	64674	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10014	1	0	0	10000	1	0	1	0	0	0	2525	1	71	2	1	2	69813	30000	9	6	6	10000	30010	70048	70051	70048	70054	70057
40024	70041	525	1	0	1	0	0	0	1	0	0	70026	69702	59743	25	40010	30013	10001	30010	10000	617068	3342206	0	49	66970	0	70078	70125	64658	3	64975	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10002	0	1	1	10000	0	1	1	1	2	0	2525	1	71	1	1	2	69804	30006	9	6	6	10000	30010	70042	70054	70042	70057	70048
40024	70047	525	0	0	0	0	0	0	1	0	0	70020	69743	59796	25	40018	30013	10002	30010	10000	617036	3341769	1	49	66961	0	70056	70056	64674	3	64981	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10001	0	0	1	10000	1	1	0	1	0	0	2525	1	71	1	1	2	69804	30006	9	6	9	10000	30010	70057	70042	70057	70042	70049
40024	70048	525	0	0	0	0	0	0	0	0	0	70035	69760	59795	25	40014	30010	10000	30010	10000	616982	3342206	0	49	66955	0	70050	70035	64668	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2525	1	71	1	2	2	69813	30000	9	6	9	10000	30010	70036	70036	70036	70057	70051
40024	70039	524	0	0	0	0	0	0	1	0	0	70035	69743	59707	25	40014	30013	10001	30010	10000	617068	3342110	0	49	66973	0	70050	70051	64723	3	64975	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	54	10012	1	0	1	0	0	0	2525	1	71	1	1	2	69813	30003	9	6	9	10000	30010	70054	70054	70150	70253	70053
40024	70222	524	0	0	0	0	0	0	1	0	0	70020	69728	59706	25	40010	30013	10000	30010	10000	616982	3342206	0	49	66967	0	70050	70050	64653	3	64975	40010	30020	10000	60020	20000	70050	77	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	0	0	1	0	0	0	2525	1	71	1	1	2	69815	30000	9	0	0	10000	30010	70051	70036	70051	70054	70233
40024	70047	526	0	0	0	1	0	0	30	1	0	70036	69760	59715	25	40014	30016	10002	30010	10000	617009	3341817	0	49	66961	0	70041	70041	64671	3	64966	40010	30020	10000	60020	20000	70053	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	2	1	10000	3	0	3	10000	1	0	1	0	0	0	2525	1	71	1	1	2	69813	30003	0	9	9	10000	30010	70051	70051	70048	70057	70059
40024	70041	524	1	0	0	0	1	1	2	1	0	70028	69765	59701	25	40010	30013	10001	30010	10000	616982	3342206	0	49	66955	0	70050	70035	64653	3	64972	40010	30682	10000	60020	20440	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10001	1	0	1	10000	1	1	1	1	0	0	2525	1	71	1	1	2	69819	30006	0	0	6	10000	30010	70042	70042	70042	70054	70048

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	0	0	0	0	0	0	2	0	0	0	0	70036	69782	59710	25	40104	30103	10002	30100	10000	616014	3342254	1	49	66971	0	70051	70035	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	1	0	0	0	2610	1	71	1	0	69814	30003	10	0	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	19	0	1	0	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616014	3341470	1	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70053	70052	70052	70052	70052
40204	70035	524	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10057	616853	3342254	1	49	66971	0	70051	70035	64647	3	64954	40100	30398	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	0	10000	30100	70036	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616175	3342254	0	49	66971	0	70051	70035	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	1	0	1	0	1	0	0	70020	69782	59695	25	40104	30103	10001	30100	10000	616175	3342254	1	49	66971	0	70051	70051	64647	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70053	70052
40204	70051	524	0	0	0	0	0	0	1	0	1	0	0	70036	69764	59710	25	40104	30103	10001	30100	10000	616175	3341470	1	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69870	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	0	0	0	1	0	0	70036	69782	59695	25	40104	30103	10001	30100	10000	616175	3342254	0	49	66971	0	70051	70160	64648	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70054	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59710	25	40104	30113	10000	30251	10000	616014	3342686	1	49	66971	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	3	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30000	0	10	0	10000	30100	70052	70052	70036	70052	70052
40204	70051	525	0	0	0	0	0	0	1	0	1	0	0	70036	69782	59695	25	40104	30100	10001	30100	10000	616014	3342254	0	49	66955	0	70051	70051	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	0	9	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616175	3342254	1	49	66955	0	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70052	70036	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	0	1	0	0	7	0	70020	69728	59825	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70048	70048	70048	70054	70048
40024	70047	525	0	0	0	1	1	1	70032	69837	59707	25	40014	30013	10004	30010	10000	616952	3342062	1	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70048	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	8	0	10000	1	1	1	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70048	70036	70048	70048	70048
40024	70049	524	0	0	0	0	1	0	70032	69728	59780	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70036	70048	70048	70048	70048
40024	70047	524	0	0	0	0	1	1	70032	69728	59786	25	40014	30013	10001	30010	10000	616952	3342062	1	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10014	1	0	10000	1	1	0	2520	1	71	1	1	69810	30003	6	6	0	10000	30010	70048	70048	70048	70171	70048
40024	70047	525	0	0	0	0	1	1	70032	69728	59723	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69819	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70035	525	0	0	0	0	1	0	70032	69728	59804	25	40014	30013	10001	30010	10000	617068	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	3	0	10000	1	1	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	524	0	0	1	0	1	1	70032	69728	59801	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70085	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70048	70048	70048	70054	70049
40024	70047	524	0	0	0	0	1	1	70032	69728	59706	25	40014	30013	10001	30010	10000	617068	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	2520	1	71	1	1	69810	30000	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	0	1	1	70032	69728	59790	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	1	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70048	70036	70048	70048	70048
40024	70047	525	0	0	0	0	1	0	70032	69728	59800	25	40014	30013	10001	30010	10000	616952	3342062	0	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	8	0	10000	1	1	0	2520	1	71	1	1	69810	30003	6	6	6	10000	30010	70048	70048	70036	70048	70048

Test 4: throughput

Count: 8

Code:

  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]
  ldrsb x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	map dispatch bubble (d6)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26732	200	1	0	41	0	0	1	26707	2	12	0	14	25	80100	100	80000	100	80015	500	1167875	1	3	49	23647	26722	26707	16650	6	16674	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	80035	0	36	80035	6	1	35	39	1	1	1	5118	3	16	26719	6	6	2	80000	100	26730	26735	26708	26723	26723
80204	26707	200	0	0	41	0	0	0	26707	3	18	18	16	25	80100	100	80000	100	80015	500	1166888	1	3	49	23642	26722	26727	16655	6	16674	80115	200	80024	200	160048	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80036	0	0	80000	0	1	35	39	1	1	1	5118	3	16	26719	6	0	2	80000	100	26720	26723	26708	26723	26723
80204	26707	200	0	0	0	1	0	0	26707	2	0	18	16	25	80100	100	80000	100	80014	500	1166596	1	3	49	23647	26722	26722	16655	6	16659	80114	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80000	0	35	80035	6	1	0	39	1	1	1	5118	3	16	26719	6	0	4	80000	100	26720	26727	26708	26729	26723
80204	26722	200	0	0	0	0	0	0	26712	2	0	0	12	25	80100	100	80000	100	80014	500	1159814	1	3	49	23642	26902	26867	16635	6	16659	80115	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	0	80035	0	35	80035	0	1	35	39	1	1	1	5118	3	16	26719	0	6	0	80000	100	26721	26709	26708	26723	26723
80204	26722	200	1	0	41	1	0	1	26715	2	0	12	12	25	80100	100	80000	100	80015	500	1167875	1	3	49	23627	26727	26707	16650	6	16659	80115	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	35	80039	6	1	35	39	1	1	1	5118	3	16	26704	10	6	2	80000	100	26730	26710	26728	26708	26708
80204	26727	200	0	0	0	0	0	1	26707	2	18	0	16	25	80100	100	80000	100	80014	500	1167875	1	3	49	23627	26722	26722	16650	6	16674	80114	200	80024	200	160048	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80035	0	35	80000	6	1	35	0	1	1	1	5118	3	16	26724	6	6	2	80000	100	26719	26723	26708	26723	26708
80204	26707	200	0	0	41	0	0	1	26707	2	18	18	12	25	80100	100	80000	100	80015	500	1167875	1	3	49	23642	26722	26722	16650	6	16674	80115	200	80024	200	160048	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	0	80039	6	1	35	39	1	1	1	5118	3	16	26719	10	0	0	80000	100	26737	26724	26728	26708	26708
80204	26707	200	0	0	0	0	0	0	26707	2	0	12	0	25	80100	100	80000	100	80014	500	1167303	1	3	49	23647	26722	26707	16655	6	16659	80114	200	80024	200	160048	26722	56	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	39	80035	0	0	80035	6	0	0	0	1	1	1	5118	3	16	26719	6	6	2	80000	100	26712	26782	26732	26728	26723
80204	26707	200	0	0	41	1	0	1	26707	2	18	18	13	25	80100	100	80000	100	80015	500	1167875	1	3	49	23642	26707	26707	16655	6	16659	80114	200	80024	200	160048	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80039	0	38	80035	0	0	35	43	1	1	1	5118	3	16	26704	0	6	0	80000	100	26735	26708	26728	26723	26723
80204	26722	200	0	1	41	0	0	0	26707	2	18	12	0	25	80100	100	80000	100	80014	500	1167875	1	3	49	23627	26707	26727	16658	6	16659	80114	200	80024	200	160048	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	35	80039	6	1	0	0	1	1	1	5118	3	16	26719	0	6	0	80000	100	26714	26863	26730	26716	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26723	200	1	0	0	0	0	41	1	0	1	26707	2	18	18	14	25	80010	10	80000	10	80000	50	1166691	49	23642	26722	26708	16667	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80021	0	39	0	80035	0	0	6	80000	6	1	36	39	5020	1	16	0	1	1	26719	0	6	6	2	80000	10	26723	26723	26723	26723	26734
80024	26728	200	0	0	0	0	0	41	1	0	1	26693	0	18	18	2	25	80010	10	80000	10	80000	50	1167605	49	23642	26722	26722	16667	3	16702	80010	20	80000	20	160000	26722	56	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80036	0	0	38	80035	6	0	35	39	5020	1	16	0	1	1	26719	0	6	6	2	80000	10	26724	26844	26730	26741	26723
80024	26722	200	0	0	0	0	0	41	1	0	1	26707	2	18	18	88	25	80010	10	80000	10	80000	50	1167605	49	23649	26722	26725	16652	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	3	35	80035	0	0	35	39	5020	1	16	0	1	1	26719	0	6	6	2	80000	10	26822	26713	26709	26729	26723
80024	26722	200	0	0	0	0	0	41	1	0	1	26707	2	18	18	7	25	80010	10	80000	10	80000	50	1167605	49	23628	26722	26722	16652	3	16702	80010	20	80000	20	160000	26722	56	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	0	35	80000	6	0	0	39	5020	1	16	0	1	1	26705	2	6	6	0	80000	10	26842	26729	26719	26729	26709
80024	26708	200	0	0	0	0	0	0	0	0	1	26693	0	0	18	14	25	80010	10	80000	10	80000	50	1167605	49	23642	26722	26722	16652	3	16702	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80027	0	0	35	80035	6	1	35	39	5020	1	16	0	1	1	26719	0	0	6	0	80000	10	26830	26714	26725	26729	26723
80024	26708	200	0	0	0	0	0	41	0	0	1	26707	2	18	18	15	25	80010	10	80000	10	80000	50	1167605	49	23628	26722	26722	16668	3	16702	80010	20	80000	20	160000	26722	56	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	80035	0	40	41	80035	0	1	0	0	5020	1	16	0	1	1	26719	0	6	6	2	80000	10	26723	26723	26723	26723	26725
80024	26722	200	0	0	0	0	0	0	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167726	49	23645	26727	26710	16669	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	0	35	80035	6	1	35	39	5020	1	16	0	1	1	26719	0	6	6	0	80000	10	26730	26723	26787	26723	26723
80024	26722	200	0	0	0	0	0	41	0	0	1	26707	2	18	18	19	25	80010	10	80000	10	80000	50	1167605	49	23642	26708	26722	16667	3	16705	80010	20	80000	20	160000	26722	72	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	0	158	80035	6	1	35	39	5020	1	16	0	1	1	26719	0	6	6	2	80000	10	26800	26731	26723	26731	26723
80024	26722	200	0	0	1	0	0	53	0	0	0	26707	0	18	18	102	25	80010	10	80000	10	80000	50	1167605	49	23631	26727	26726	16671	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	0	35	80035	6	0	35	39	5020	1	16	0	1	1	26705	0	6	0	2	80000	10	26723	26723	26723	26723	26725
80024	26710	200	0	0	0	0	0	12	1	0	1	26712	2	18	18	92	25	80010	10	80000	10	80000	50	1167605	49	23642	26722	26722	16668	3	16702	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	10	80000	0	39	0	80035	0	0	35	80000	6	1	0	39	5020	1	16	0	1	1	26719	0	6	6	2	80000	10	26728	26723	26709	26712	26726

LDRSB (register, sxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations