Firestorm: LDP (post-index, 32-bit) measurements

Code:

  ldp w0, w1, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	20	22	24	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
3005	1054	8	0	0	0	0	0	75	83	1	0	3	4	1025	0	2	7	6	20	25	2000	1000	1000	1000	1000	52844	45591	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1023	0	0	61	1033	4	0	32	12	29	1051	59	7	28	64	0	73	1	16	1	1	1037	1000	44	27	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	0	0	0	0	0	59	47	0	0	2	0	1028	0	2	4	4	15	25	2000	1000	1000	1000	1000	52840	45592	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1012	12	0	56	1034	9	0	29	6	17	1030	32	5	24	56	0	73	1	16	1	1	1037	1000	30	28	1000	2000	1041	1044	1041	1041	1041
3004	1040	8	0	0	0	0	0	62	48	1	0	2	0	1025	10	2	7	11	20	25	2000	1000	1000	1000	1000	52833	45592	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1016	12	5	40	1032	3	1	15	12	19	1058	49	5	21	48	0	73	1	16	1	1	1037	1000	31	24	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	0	0	0	0	72	41	1	0	2	0	1025	0	3	4	8	16	25	2000	1000	1000	1000	1000	52828	45592	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1024	0	0	51	1028	2	1	22	12	35	1057	35	5	13	64	0	73	1	16	1	1	1037	1000	30	31	1000	2000	1044	1041	1041	1109	1041
3004	1040	8	0	1	0	0	0	68	0	0	0	2	0	1025	0	3	8	5	19	25	2000	1000	1000	1000	1000	52847	45591	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1000	0	0	48	1020	0	0	0	0	27	1015	44	6	15	56	0	73	1	16	1	1	1020	1000	30	31	1000	2000	1044	1041	1041	1041	1041
3004	1040	8	0	0	0	0	0	80	35	1	0	2	0	1028	17	6	7	11	20	25	2000	1000	1000	1000	1000	52836	45592	0	1043	1040	574	3	651	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1017	0	0	65	1023	0	0	0	0	546	1026	47	4	25	72	0	73	1	16	1	1	1037	1000	35	31	1000	2000	1041	1041	1041	1041	1041
3004	1043	8	0	0	1	0	0	62	55	0	0	2	0	1028	9	3	6	6	15	25	2000	1000	1000	1000	1000	52840	45592	0	1043	1040	574	3	651	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1016	0	0	43	1027	1	0	13	6	20	1034	34	5	26	48	0	73	1	16	1	1	1037	1000	36	27	1000	2000	1044	1041	1044	1041	1041
3004	1040	8	0	1	0	0	0	61	40	0	0	2	20	1025	14	3	4	8	26	25	2000	1000	1000	1000	1000	52837	45592	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1021	0	0	57	1026	13	0	13	0	15	1030	40	7	31	56	0	73	1	16	1	1	1037	1000	41	28	1000	2000	1041	1044	1041	1041	1041
3004	1040	8	0	0	0	0	0	54	42	1	0	4	0	1025	0	3	4	11	16	25	2000	1000	1000	1000	1000	52830	45592	0	1040	1043	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1012	0	0	64	1028	4	0	15	18	22	1032	35	5	21	64	0	73	1	16	1	1	1037	1000	38	28	1000	2000	1041	1041	1123	1041	1044
3004	1040	8	0	0	0	0	0	43	29	1	0	2	0	1025	10	3	6	10	13	25	2000	1000	1000	1000	1000	52831	45592	1	1040	1055	574	3	657	2000	1000	2000	1000	1000	1043	38	1	1	1001	1000	1000	0	1000	0	0	56	1027	1	1	13	0	29	1054	41	5	21	56	0	73	1	16	1	1	1037	1000	36	27	1000	2000	1041	1041	1041	1041	1041

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.2198

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	72572	542	1	1	0	0	1	0	0	0	463	798	1	688	4	128	72170	795	44	1	71988	25	51020	40865	10173	40100	10000	620411	2754829	0	49	69199	72301	72011	64546	0	3	64587	50100	40200	20000	70200	10000	72098	35	1	1	40201	100	99	100	10000	30100	10000	100	10885	1	147	485	10675	259	5	878	114	55	11002	117	51	123	1	0	9	0	0	2612	6	57	5	3	71933	40752	971	1025	873	10000	50100	72179	72213	72102	72240	72309
60204	72136	540	2	1	0	0	1	0	0	1	449	823	1	544	3	96	72078	805	45	2	71962	25	50995	40796	10171	40100	10000	624605	2759210	0	49	69263	72148	72162	64201	0	3	64785	50100	40200	20000	70200	10000	72242	35	1	1	40201	100	99	100	10000	30100	10000	100	10914	1	142	489	10723	264	9	898	78	61	10994	130	48	123	1	0	7	0	0	2612	5	57	3	4	72163	40644	1142	1118	1073	10000	50100	72151	72290	72109	72009	72044
60204	72175	541	1	1	0	0	1	0	0	0	455	841	1	712	2	120	72061	805	50	1	71808	25	51020	40808	10158	40100	10000	622445	2763287	0	49	68974	72313	72369	64373	0	3	64574	50100	40200	20000	70200	10000	72134	35	1	1	40201	100	99	100	10000	30100	10000	100	10929	1	162	518	10665	238	6	938	74	67	10935	124	51	109	1	3	3	0	0	2612	3	57	4	5	72146	40656	1046	1000	999	10000	50100	72350	72136	72247	72413	72313
60204	72268	539	1	1	0	0	1	0	0	0	486	828	1	680	2	112	72134	803	52	2	72020	25	50955	40804	10171	40100	10000	621203	2755761	0	49	68958	72205	72406	64138	0	3	64652	50100	40200	20000	70200	10000	72147	35	1	1	40201	100	99	100	10000	30100	10000	100	10922	1	144	505	10684	269	6	877	44	55	10971	125	49	107	1	0	3	0	0	2612	5	57	5	5	72185	40592	1123	1164	926	10000	50100	72160	72152	72400	72258	72217
60204	72199	559	1	1	0	0	1	1	1	0	461	834	1	744	3	160	71934	816	47	1	71746	25	50935	40732	10169	40100	10000	621428	2754772	1	49	69258	72167	72031	64301	0	3	64625	50100	40200	20000	70200	10000	72440	35	1	1	40201	100	99	100	10000	30100	10000	100	10861	2	169	510	10674	291	6	887	50	60	10968	124	46	116	1	0	3	0	0	2612	5	57	4	4	71992	40676	963	1057	1027	10000	50100	72007	72170	72092	72126	72113
60204	72372	540	1	1	0	0	1	0	0	0	534	808	1	728	3	108	72082	779	49	0	71855	25	50980	40816	10164	40100	10000	621185	2755703	1	49	68990	72235	72146	64331	0	3	64605	50100	40200	20000	70200	10000	72083	35	1	1	40201	100	99	100	10000	30100	10000	100	10912	2	157	497	10676	265	7	864	44	62	10986	115	50	124	2	0	3	0	0	2612	5	57	6	4	72057	40648	995	1007	999	10000	50100	72214	72214	72190	72193	72003
60204	72000	540	2	1	0	0	1	0	0	0	495	816	1	704	4	132	72056	814	46	5	71941	25	51010	40776	10177	40100	10000	622913	2765553	1	49	69361	72169	72447	64477	0	3	64654	50100	40396	20000	70200	10000	72318	35	1	1	40201	100	99	100	10000	30100	10000	100	10914	3	157	503	10707	286	7	943	40	52	10951	128	51	117	2	0	3	0	0	2612	5	57	5	3	72169	40640	952	1066	1137	10000	50100	72127	72067	72195	72138	72170
60204	72301	541	2	1	0	0	1	0	0	0	528	799	1	680	3	104	72204	765	51	4	71792	25	50995	40836	10183	40100	10000	621149	2756698	1	49	68981	72292	72229	64204	0	3	64510	50100	40200	20000	70200	10000	72393	35	1	1	40201	100	99	100	10000	30100	10000	100	10915	6	158	502	10684	256	9	924	144	72	10960	124	49	118	2	2	5	0	0	2612	4	57	5	5	72140	40704	1134	966	1014	10000	50100	72351	72283	72196	72399	72241
60204	72196	540	2	1	2	0	1	0	0	0	483	817	1	712	3	112	72399	797	45	3	71998	25	50995	40844	10167	40100	10000	622922	2748895	1	49	68987	72393	72221	64444	0	3	64725	50100	40200	20000	70200	10000	72303	35	1	1	40201	100	99	100	10000	30100	10000	100	10894	2	152	516	10696	266	7	875	80	63	10961	118	49	129	2	0	7	0	0	2612	5	57	6	6	72068	40732	1104	983	1021	10000	50100	72008	72158	72193	72263	72078
60204	72048	559	2	1	0	0	1	0	0	0	469	810	1	688	3	144	72447	818	44	3	71955	25	50970	40856	10164	40100	10000	620537	2758854	0	49	68904	72131	72206	64043	0	3	64599	50100	40200	20000	70200	10000	72291	35	1	1	40201	100	99	100	10000	30100	10000	100	10892	4	145	496	10675	279	7	878	72	64	10964	135	48	126	1	0	7	0	0	2612	5	57	5	6	72176	40712	1031	1063	989	10000	50100	72287	72256	72212	72327	72278

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.2237

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	72147	541	1	0	0	0	0	0	0	0	581	0	807	1	720	2	96	72157	830	53	7	72057	25	50970	40786	10192	40010	10000	623895	2765598	1	49	69142	72229	72288	64571	0	3	64693	50010	40020	20000	70020	10000	72221	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10911	2	147	494	10747	263	12	934	48	90	10952	129	56	130	1	3	8	0	0	2520	1	56	1	1	72198	40720	948	930	960	10000	50010	72144	72206	72311	72143	72285
60024	72298	541	1	0	0	0	0	0	0	0	597	0	836	1	720	2	148	72365	820	52	9	71943	25	51018	40726	10187	40010	10165	633641	2765149	1	49	69064	72143	72237	64337	0	3	64547	50010	40020	20334	70020	10000	72102	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10901	1	160	503	10691	278	12	924	50	75	10986	129	53	134	1	0	7	0	0	2520	1	56	1	1	72183	40732	1000	1016	908	10000	50010	72335	72267	72349	72334	72249
60024	72248	540	1	0	0	1	0	0	0	0	622	0	802	1	712	2	112	72218	806	51	10	71987	25	50925	40734	10182	40010	10000	621771	2759874	1	49	69243	72224	72214	64431	0	3	64765	50010	40020	20000	70020	10000	72446	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10923	1	160	500	10699	279	13	960	48	92	10976	129	53	131	1	0	13	0	0	2520	1	56	1	1	72218	40764	900	928	1000	10000	50010	72180	72291	72313	72121	72143
60024	72197	541	1	1	0	0	0	0	0	0	680	0	809	1	448	2	128	72339	819	57	8	71909	25	50955	40706	10191	40010	10000	622383	2768174	1	49	69123	72196	72302	64460	0	3	64586	50010	40020	20000	70020	10000	72209	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10924	1	144	487	10716	257	10	892	44	84	11008	129	55	136	1	0	3	0	0	2520	1	56	2	1	71794	40736	940	984	986	10000	50010	72240	72196	72313	72272	72119
60024	72075	541	1	0	1	0	0	0	0	0	568	0	821	1	736	0	108	72226	817	53	7	71991	25	50985	40742	10195	40010	10000	622986	2757545	1	49	69239	72167	72189	64482	0	3	64534	50010	40020	20000	70020	10000	72208	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10916	1	159	528	10703	271	11	902	50	1893	10983	131	53	135	1	0	7	0	0	2520	1	56	1	1	71943	40724	940	980	982	10000	50010	72290	72343	72164	72279	72178
60024	72368	541	1	0	0	0	0	0	0	0	567	0	815	1	720	1	104	72189	805	54	5	71962	25	50865	40750	10185	40010	10000	623085	2758699	1	49	69156	72329	72194	64368	0	3	64764	50010	40020	20000	70020	10000	72167	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10956	1	150	512	10712	281	9	895	78	94	10973	119	53	132	1	3	7	0	0	2520	1	56	1	1	72088	40764	952	978	984	10000	50010	72267	72105	72173	72170	72233
60024	72222	541	1	0	0	0	1	0	0	0	599	0	900	1	768	1	144	72209	816	54	8	72048	25	50945	40774	10185	40010	10000	622896	2759892	0	49	69379	72083	72180	64498	0	3	64698	50010	40020	20000	70020	10000	72315	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10920	1	149	504	10713	274	11	902	48	77	10966	133	56	142	1	3	10	0	0	2520	1	56	1	1	71961	40800	914	950	1032	10000	50010	72286	72143	72185	72233	72230
60024	72293	540	1	1	0	1	0	0	0	0	592	0	831	2	720	1	100	72229	805	55	7	72122	25	50960	40702	10174	40010	10000	624111	2763317	1	49	69175	72041	72104	64527	0	3	64833	50010	40020	20000	70020	10000	72472	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10937	1	154	533	10701	258	11	932	78	86	11016	134	54	134	1	3	7	0	0	2520	1	56	1	1	72090	40768	980	1072	990	10000	50010	72189	72213	72151	72226	72003
60024	72269	542	1	0	0	1	1	0	0	0	654	0	852	1	744	0	136	72367	812	52	8	71989	25	50985	40698	10181	40010	10000	622635	2760763	1	49	69111	72208	72131	64341	0	3	64694	50010	40020	20000	70020	10000	72238	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10921	1	169	517	10717	275	13	928	76	94	10999	145	53	126	0	0	4	0	0	2520	1	56	1	1	71970	40716	938	972	940	10000	50010	72332	72158	72292	72139	72143
60024	71979	542	0	0	0	0	1	0	0	0	579	0	808	1	736	0	116	72228	812	60	9	71833	25	50915	40774	10166	40010	10000	620187	2759143	1	49	69115	72234	72330	64326	0	3	64690	50010	40020	20000	70020	10000	72265	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10879	0	132	504	10701	272	11	937	76	82	10978	127	53	141	0	0	7	1	0	2520	1	56	1	1	72150	40736	942	946	956	10000	50010	72361	72294	72148	72209	72290

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6], #8
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1915

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	72148	539	2	0	0	0	0	448	824	1	736	1	148	71931	795	3	2	71671	25	50725	40608	10141	40100	10000	620285	2745176	49	68864	72037	71888	64137	0	3	64300	50100	40200	20000	70200	10000	71810	35	1	1	40201	100	99	100	10000	30100	10000	100	10925	3	147	521	10663	262	13	906	166	30	10901	138	6	135	3	0	7	2610	2	57	1	1	71799	40528	1056	1021	1097	10000	50100	71710	71886	71884	72134	71869
60204	71833	538	1	0	0	1	0	448	818	1	680	1	100	71668	803	3	2	71653	25	50765	40616	10130	40100	10000	618737	2752806	49	68684	71933	71805	64003	0	3	64484	50100	40200	20000	70200	10000	71916	35	1	1	40201	100	99	100	10000	30100	10000	100	10877	1	163	492	10631	279	11	904	34	1971	10929	137	5	125	2	0	3	2610	1	57	1	1	71952	40508	1041	1022	965	10000	50100	71865	71777	71857	71975	71957
60204	71918	538	3	3	0	0	0	446	790	1	720	3	144	71842	810	3	2	71692	25	50775	40656	10122	40100	10000	618224	2744865	49	68795	71797	72199	64197	0	3	64350	50100	40200	20000	70200	10000	71815	35	1	1	40201	100	99	100	10000	30100	10000	100	10915	3	154	535	10666	255	12	908	76	32	10908	123	5	115	3	4	3	2610	1	57	1	1	71606	40540	1080	1189	1109	10000	50100	71812	71987	71898	71950	71904
60204	72024	539	3	0	0	0	0	428	818	1	704	3	116	71694	803	2	2	71669	25	50725	40600	10126	40100	10000	618962	2742137	49	68999	72004	71973	64092	0	3	64364	50100	40200	20000	70200	10000	71867	35	1	1	40201	100	99	100	10000	30100	10000	100	10906	3	145	500	10649	256	14	884	94	38	10891	125	6	124	1	0	2	2610	1	17	1	1	71884	40492	1027	1051	1044	10000	50100	71885	71725	72027	71891	71987
60204	71759	540	3	0	0	0	0	447	813	1	704	2	136	71774	798	2	3	71469	25	50790	40616	10128	40100	10000	618368	2750867	49	68802	71818	71835	64117	0	3	64263	50100	40200	20000	70200	10000	71857	35	1	1	40201	100	99	100	10000	30100	10000	100	10929	3	118	512	10625	258	13	914	78	35	10904	121	5	130	3	0	5	2610	1	57	1	1	71506	40472	956	1042	968	10000	50100	71927	71909	71920	71773	71675
60204	71840	539	3	1	1	0	0	429	837	1	688	3	148	71844	803	3	3	71575	25	50830	40584	10128	40100	10000	619979	2743854	49	68961	71983	72103	64071	0	3	64381	50100	40200	20000	70200	10000	71959	35	1	1	40201	100	99	100	10000	30100	10000	100	10913	3	145	492	10652	279	12	916	74	23	10948	125	5	132	3	0	3	2610	1	57	1	1	71598	40484	1007	1027	975	10000	50100	71828	71967	71883	71994	71975
60204	71972	538	3	0	0	0	0	474	802	1	712	2	112	71898	806	2	3	71609	25	50755	40656	10130	40100	10000	619556	2751100	49	68994	71972	71985	64130	0	3	64357	50100	40200	20000	70200	10000	72050	35	1	1	40201	100	99	100	10000	30100	10000	100	10889	3	162	525	10645	267	14	909	80	29	10921	122	6	128	3	0	3	2610	1	57	1	1	71519	40508	1150	1103	1010	10000	50100	71986	71859	71779	71956	71889
60204	71928	540	3	0	3	0	0	500	821	1	680	3	136	72013	787	3	2	71476	25	50785	40652	10134	40100	10000	620357	2745747	49	68872	71830	71945	64239	0	3	64439	50100	40200	20000	70200	10000	71988	35	1	1	40201	100	99	100	10000	30100	10000	100	10906	4	133	488	10630	256	13	881	74	28	10900	122	5	119	3	3	9	2610	1	57	1	1	71695	40540	1142	1070	1019	10000	50100	71861	72032	71856	71869	71766
60204	71823	539	4	4	4	0	0	451	827	1	720	3	152	71856	791	2	2	71774	25	50700	40624	10144	40100	10000	619169	2745929	49	68998	71949	72016	64130	0	3	64359	50100	40200	20000	70200	10000	72001	35	1	1	40201	100	99	100	10000	30100	10000	100	10929	3	148	506	10643	254	11	952	84	32	10926	123	5	134	3	0	5	2610	1	57	1	1	71751	40472	1043	1090	1060	10000	50100	71958	72039	71970	71941	71955
60204	72024	538	3	0	0	0	0	459	823	1	688	4	120	71872	792	2	2	71616	25	50760	40620	10125	40100	10000	618953	2750806	49	68843	72073	71697	64193	0	3	64481	50100	40200	20000	70200	10000	71901	35	1	1	40201	100	99	100	10000	30100	10000	100	10904	4	126	532	10640	275	15	886	78	30	10896	128	7	132	4	3	5	2610	1	57	1	1	71843	40596	1059	1076	1154	10000	50100	71961	72018	71857	71773	71876

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1733

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	1f	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	71855	538	1	0	0	1	1	464	0	827	2	392	1	212	71716	805	5	2	71586	25	50610	40538	10173	40010	10000	618302	2744689	0	98	68976	71691	71886	64031	3	64134	50010	40020	20000	70020	10000	71742	35	1	1	40021	10	9	10	10000	30010	10000	10	10893	1	160	517	10668	276	12	934	80	46	10915	127	7	130	1	3	3	0	2520	0	1	64	0	1	1	71724	40512	900	922	836	10000	50010	71768	71739	71496	71768	71895
60024	71665	537	1	0	0	1	0	509	0	829	2	544	1	288	71536	803	6	3	71567	25	50685	40562	10132	40010	10000	617096	2746089	0	49	68743	71812	71840	64096	3	64051	50010	40020	20000	70020	10000	71671	35	1	1	40021	10	9	10	10000	30010	10000	10	10911	1	143	492	10667	261	10	913	152	24	10930	108	8	126	1	0	14	0	2520	0	1	64	0	1	2	71537	40536	882	830	932	10000	50010	71644	71764	71824	71768	71797
60024	71801	537	1	0	0	1	0	517	0	876	2	568	1	276	71758	818	6	3	71565	25	50700	40518	10132	40302	10000	617492	2743111	0	49	68747	71626	71718	64014	3	64165	50010	40020	20000	70020	10000	71786	35	1	1	40021	10	9	10	10000	30010	10000	10	10905	2	132	530	10671	268	13	923	66	49	10943	135	10	132	1	1	12	0	2520	0	2	64	0	1	1	71625	40500	868	858	864	10000	50010	71693	71711	71741	71684	71855
60024	71729	537	1	0	0	0	0	512	0	837	2	496	1	280	71740	804	6	3	71520	25	50650	40534	10122	40010	10000	617069	2739732	0	98	68985	71547	71677	63991	3	64311	50010	40020	20000	70020	10000	71641	35	1	1	40021	10	9	10	10000	30010	10000	10	10922	1	151	530	10652	277	14	924	76	40	10948	130	6	128	1	5	11	0	2520	0	1	64	0	1	1	71574	40484	892	870	940	10000	50010	71693	71853	71530	71841	71647
60024	71850	538	1	0	1	0	0	506	0	845	2	496	1	228	71710	812	6	1	71525	25	50610	40534	10133	40010	10000	616862	2735554	0	49	68773	71927	71775	64006	3	64167	50010	40020	20000	70020	10000	71894	35	1	1	40021	10	9	10	10000	30010	10000	10	10890	1	152	519	10650	270	12	915	130	37	10904	113	8	123	1	3	7	0	2520	0	1	64	0	1	1	71696	40512	894	810	886	10000	50010	71834	71834	71694	71683	71652
60024	71587	537	1	0	1	0	0	532	0	830	2	480	1	272	71627	795	7	4	71680	25	50725	40506	10130	40010	10000	617150	2744457	0	49	68652	71861	71927	63973	3	64090	50010	40020	20000	70020	10000	71684	35	1	1	40021	10	9	10	10000	30010	10000	10	10897	1	155	517	10641	272	14	892	122	49	10903	121	5	141	1	25	11	0	2520	0	1	64	0	1	2	71457	40516	920	1022	942	10000	50010	71879	71803	71809	71684	71635
60024	71724	537	1	1	0	0	0	471	0	849	2	536	1	280	71903	809	6	3	71715	25	50640	40534	10121	40010	10000	617618	2744127	0	49	68544	71864	71602	63950	3	64198	50010	40020	20000	70020	10000	71932	35	1	1	40021	10	9	10	10000	30010	10000	10	10908	1	155	515	10673	253	13	902	104	36	10926	136	7	140	1	3	11	0	2520	0	1	64	0	1	1	71551	40524	976	906	842	10000	50010	71702	71799	71737	71808	71838
60024	71681	537	1	0	0	1	0	535	0	830	2	512	1	232	71675	805	5	7	71665	25	50675	40546	10126	40010	10000	618284	2742978	0	49	68849	71797	71669	63905	3	64267	50384	40354	20000	70020	10000	71784	35	1	1	40021	10	9	10	10000	30010	10000	10	10967	1	151	544	10650	267	13	904	134	148	10913	123	7	128	1	1	7	0	2520	0	1	64	0	1	1	71610	40524	902	978	900	10000	50010	71623	71636	71839	71816	71778
60024	71634	537	1	1	1	0	0	511	0	832	2	528	1	216	71609	821	6	3	71501	25	50580	40546	10132	40010	10000	618878	2746413	0	49	68721	71814	71724	64024	3	64202	50010	40020	20000	70020	10000	71888	35	1	1	40021	10	9	10	10000	30010	10000	10	10912	1	151	500	10675	255	9	932	134	44	10949	118	7	128	1	6	17	0	2520	0	1	64	0	1	1	71462	40544	862	916	854	10000	50010	71777	71759	71900	71767	71895
60024	71654	538	1	0	0	0	0	470	0	837	2	504	1	384	71731	820	8	3	71564	25	50675	40530	10128	40010	10000	617501	2739029	0	49	68588	71805	71602	63915	3	64124	50010	40020	20000	70020	10000	71596	35	1	1	40021	10	9	10	10000	30010	10000	10	10910	1	153	502	10649	269	9	937	84	43	10930	133	4	123	1	0	8	0	2520	0	1	64	0	1	1	71605	40536	922	920	910	10000	50010	71806	71825	71741	71669	71759

Test 4: throughput

Count: 8

Code:

  ldp w0, w1, [x6], #8
  ldp w0, w1, [x7], #8
  ldp w0, w1, [x8], #8
  ldp w0, w1, [x9], #8
  ldp w0, w1, [x10], #8
  ldp w0, w1, [x11], #8
  ldp w0, w1, [x12], #8
  ldp w0, w1, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3963

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240209	31973	237	3	0	1	1	0	0	6949	780	1	552	110	92	31757	785	382	2060	1972	1531	25	160120	80121	80000	80100	80000	400577	684404	0	18	49	28614	31816	31693	1477	89	3	1585	160100	80200	160000	80200	80000	31718	38	1	1	80201	100	99	37	100	80000	100	80000	0	100	80942	65	361	5291	85781	630	12	869	38	5092	85922	772	128	4841	4908	63	0	3	5110	1	16	1	1	31620	37	80023	535	526	7	80000	160100	31555	31605	31860	31688	31721
240204	31794	238	4	0	0	0	0	0	7473	783	1	704	93	116	31691	786	375	2067	2007	1495	25	160125	80116	80000	80100	80000	400576	689939	0	23	49	28529	32006	31910	1565	107	3	1777	160100	80200	160000	80200	80000	31584	38	1	1	80201	100	99	31	100	80000	100	80000	0	100	80949	48	393	5379	85643	693	11	876	42	5654	85984	899	125	5052	5250	47	2	6	5110	1	16	1	1	31606	38	80021	600	489	7	80000	160100	31814	31607	31612	31630	31580
240204	31612	237	3	0	0	3	0	0	6809	807	1	680	106	108	31669	780	351	2067	1966	1566	25	160124	80121	80000	80100	80000	400580	672869	0	31	49	28697	31720	31753	1627	147	3	1705	160100	80200	160000	80200	80000	31713	38	1	1	80201	100	99	45	100	80000	100	80000	0	100	80919	47	370	5720	85475	653	12	927	30	5164	86052	723	131	5139	5329	47	0	6	5110	1	16	1	1	31981	23	80018	471	571	4	80000	160100	31825	31503	31564	31608	31688
240204	31653	237	4	0	1	1	0	0	7489	781	1	720	90	104	31667	740	331	1888	1780	1557	25	160118	80125	80000	80100	80000	400572	687084	0	18	49	28727	31574	31642	1421	105	3	1701	160100	80200	160000	80200	80000	31760	38	1	1	80202	100	99	47	100	80000	100	80000	0	100	80953	47	327	5500	85649	695	17	855	38	5368	86393	815	126	5403	4873	47	3	1	5110	1	16	1	1	31684	21	80024	500	525	4	80000	160100	31658	31600	31751	31708	31712
240204	31675	236	3	0	0	0	0	0	7075	833	1	720	98	148	31599	793	355	1868	1782	1547	25	160121	80131	80000	80100	80000	400587	687325	1	25	49	28705	31553	31729	1564	82	3	1725	160100	80200	160000	80200	80000	31769	38	1	1	80201	100	99	34	100	80000	100	80000	0	100	80955	64	384	5206	85697	650	13	876	30	5345	86510	746	136	5582	5540	61	3	5	5110	1	16	1	1	31736	35	80138	638	571	6	80000	160100	31620	31721	31773	31782	31507
240204	31630	237	3	0	1	0	0	0	8551	797	1	704	102	88	31600	766	364	1961	1913	1662	25	160129	80120	80000	80100	80000	400573	680396	0	25	49	28553	31524	31715	1513	116	3	1682	160100	80200	160000	80200	80000	31710	38	1	1	80201	100	99	32	100	80000	100	80000	0	100	80913	32	378	6048	85510	641	13	860	42	5478	85946	714	141	5263	4767	34	0	3	5110	1	16	1	1	31776	23	80019	495	530	1	80000	160100	31641	31573	31828	31596	31657
240204	31780	238	2	0	0	2	1	0	7003	793	1	704	93	128	31742	754	337	2183	2059	1534	25	160122	80118	80000	80100	80000	400552	689435	0	28	49	28589	31690	31702	1354	94	3	1696	160100	80200	160000	80200	80000	31583	38	1	1	80201	100	99	33	100	80000	100	80000	0	100	80937	48	372	6008	85564	681	17	889	48	4937	85642	781	128	5432	5388	48	0	5	5110	1	16	1	1	31759	25	80025	627	542	4	80000	160100	31543	31661	31677	31645	31701
240204	31723	238	3	0	0	0	1	0	6160	778	1	672	102	156	31799	817	355	1906	1889	1688	25	160113	80123	80000	80100	80000	400586	671053	0	22	49	28741	31652	31818	1602	92	3	1678	160100	80200	160000	80200	80000	31691	38	1	1	80201	100	99	35	100	80000	100	80000	0	100	80933	48	331	5849	84649	656	11	854	36	5469	85710	750	118	5128	5493	49	0	5	5110	1	16	1	1	31735	28	80027	527	583	0	80000	160100	31730	31857	31605	31832	31543
240204	31677	237	3	0	0	0	0	0	6829	808	1	696	107	92	31743	787	315	1784	1961	1567	25	160122	80119	80000	80100	80000	400586	683311	0	19	49	28691	31710	31676	1573	161	3	1475	160100	80200	160000	80200	80000	31672	38	1	1	80201	100	99	43	100	80000	100	80000	0	100	80962	63	381	5577	84859	636	14	938	76	4964	86176	806	134	5369	4736	65	3	3	5110	1	16	1	1	31793	26	80017	539	509	3	80000	160100	31798	31691	31566	31700	31872
240204	31640	238	4	4	0	0	0	0	7288	814	1	728	100	92	31652	792	365	2101	1774	1538	25	160120	80131	80000	80100	80000	400585	689227	0	12	49	28649	31770	31890	1596	51	3	1919	160100	80200	160000	80200	80000	31727	38	2	1	80201	100	99	40	100	80000	100	80000	0	100	80941	64	388	5823	85359	684	9	902	34	5545	85616	729	129	5960	4904	64	0	6	5110	1	16	1	1	31614	29	80026	570	523	2	80000	160100	31553	31796	31570	31818	31758

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3973

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240029	31902	237	1	1	0	0	0	8474	0	859	1	720	82	156	32006	783	1992	1863	2111	1710	25	160029	80036	80000	80010	80000	400106	757773	0	26	49	28802	31605	31976	1588	110	3	1981	160010	80020	160000	80020	80000	31620	38	1	1	80021	10	9	6	10	80000	10	80000	0	10	80932	34	413	5496	86526	766	19	888	48	6439	87044	767	117	6879	4046	16	8	5	5020	7	16	12	3	6	31838	30	80023	503	433	14	80000	160010	31568	31816	31790	31610	31449
240024	31762	238	2	1	0	0	0	8670	0	773	1	624	94	96	31701	776	2075	1986	2340	1356	25	160040	80039	80000	80010	80000	400135	730654	0	22	49	28624	31634	31708	1519	162	3	1745	160010	80020	160000	80020	80000	31741	38	1	1	80021	10	9	9	10	80000	10	80000	0	10	80926	18	391	5715	86636	738	15	875	142	6715	87477	771	125	6647	5314	16	4	4	5020	6	16	8	3	2	31740	33	80028	511	474	7	80000	160010	31855	31854	31841	31704	31954
240024	31818	237	1	0	0	0	0	8812	0	816	1	720	99	356	31759	813	2013	2320	2597	1619	25	160029	80031	80000	80010	80000	400106	736113	0	30	49	28750	31677	31815	1630	178	3	1561	160010	80020	160000	80020	80000	31791	38	1	1	80021	10	9	7	10	80000	10	80000	0	10	80923	18	364	5650	86530	699	19	888	130	6528	87248	681	116	6816	4900	16	6	3	5020	3	16	10	2	3	31994	15	80033	612	427	21	80000	160010	31652	31680	31903	31660	31663
240024	31890	237	1	1	1	0	0	9491	0	793	1	720	93	128	31767	803	1907	2035	2383	1732	25	160039	80036	80000	80010	80000	400123	722421	0	31	49	28919	31747	31671	1547	139	3	2091	160010	80020	160000	80020	80000	31513	38	1	1	80021	10	9	9	10	80000	10	80000	0	10	80887	33	367	5670	86412	717	11	919	28	6811	87401	685	128	6474	5109	34	3	5	5020	2	16	10	2	2	31889	34	80028	441	426	22	80000	160010	31800	31738	31635	31596	31911
240024	31784	239	2	1	2	0	0	7822	0	806	1	736	93	152	31669	803	1921	2004	2276	1717	25	160030	80032	80000	80010	80000	400141	745665	0	24	49	28646	31916	31770	1751	158	3	1654	160010	80020	160000	80020	80000	31555	38	1	1	80021	10	9	11	10	80000	10	80000	0	10	80916	34	431	5609	86766	743	20	926	32	7292	87232	700	144	6549	5521	32	3	4	5020	2	16	8	3	2	31696	21	80023	486	504	12	80000	160010	31825	31798	31867	31838	31700
240024	31646	237	2	2	2	0	0	8803	0	814	1	632	86	156	31509	808	1996	2063	2401	1716	25	160029	80034	80000	80010	80000	400142	718843	0	27	49	28763	31782	31671	1408	143	3	1705	160010	80020	160000	80020	80000	31748	38	1	1	80021	10	9	9	10	80000	10	80000	0	10	80921	33	383	6038	87366	704	17	910	32	6832	87132	755	122	6553	4914	32	0	4	5020	2	16	8	2	6	31843	23	80020	516	495	10	80000	160010	31662	31786	31727	31880	31660
240024	31891	239	2	2	2	0	0	8893	0	843	1	728	96	152	31936	775	2153	2046	2228	1467	25	160032	80048	80000	80010	80000	400113	731718	0	34	49	28898	31845	31944	1575	96	3	1772	160010	80020	160000	80020	80000	31779	38	1	1	80021	10	9	13	10	80000	10	80000	0	10	80940	49	411	6133	86904	704	12	937	28	7271	87762	762	133	7046	5667	49	0	7	5020	2	16	8	2	2	31876	26	80032	502	468	18	80000	160010	31701	31814	31879	31761	31921
240024	31666	239	2	2	1	0	0	8449	0	814	1	704	86	116	31496	786	2407	2137	2198	1643	25	160039	80039	80000	80010	80000	400148	781797	0	27	49	28730	31872	31668	1549	101	3	1610	160010	80020	160000	80020	80000	31660	38	1	1	80021	10	9	11	10	80000	10	80000	1	10	80959	34	454	5867	86553	734	15	882	32	6594	88134	759	117	6474	5314	32	0	9	5020	3	16	8	7	3	31824	31	80024	487	474	16	80000	160010	31612	32002	31736	31901	31869
240024	31477	250	2	2	2	0	0	8003	0	828	1	712	83	108	31767	832	2088	2089	2161	1424	25	160036	80035	80000	80010	80134	400167	776232	1	18	49	28551	31712	31783	1379	102	3	1763	160010	80020	160000	80020	80000	31760	38	1	1	80021	10	9	7	10	80000	10	80000	0	10	80933	31	401	6164	86693	673	23	907	40	7150	87881	746	127	6398	5167	32	3	4	5020	2	16	10	3	2	32110	23	80041	535	566	8	80000	160010	31654	31913	31820	31946	31725
240024	31762	238	2	2	0	0	0	8561	0	813	1	720	90	108	31723	794	2164	1973	2189	1567	25	160050	80028	80000	80010	80000	400111	723237	0	29	49	28751	31834	31756	1452	175	3	1806	160010	80020	160000	80020	80000	31801	38	1	1	80021	10	9	16	10	80000	10	80000	0	10	80938	33	402	5266	86969	725	14	903	90	7381	88217	740	129	6182	4854	31	3	5	5020	6	16	10	2	2	31890	38	80028	533	561	22	80000	160010	31666	31981	31690	31781	31891

LDP (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations