Firestorm: PRFM (register, PLDL2KEEP) measurements

Code:

  prfm pldl2keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1594	12	31	17	34	2451	1574	859	25	1000	1000	1000	68407	1	1585	1570	1302	3	1460	1000	1000	1000	1581	1582	1	1	1001	241	2263	2283	3285	0	2423	2240	1000	73	1	16	1	1	1498	1000	1643	1614	1583	1612	1593
1004	1599	12	33	16	32	2435	1602	891	25	1000	1000	1000	68914	1	1612	1595	1290	3	1461	1000	1000	1000	1604	1569	1	1	1001	268	2255	2274	3284	0	2445	2264	1000	73	1	16	1	1	1504	1000	1608	1603	1613	1596	1599
1004	1612	12	33	15	32	2431	1591	866	25	1000	1000	1000	69429	0	1588	1601	1290	3	1422	1000	1000	1000	1609	1548	1	1	1001	251	2285	2236	3272	0	2444	2240	1000	73	1	16	1	1	1494	1000	1600	1598	1584	1597	1591
1004	1606	11	32	16	32	2455	1597	881	25	1000	1000	1000	69249	1	1576	1604	1303	3	1457	1000	1000	1000	1583	1589	1	1	1001	233	2219	2253	3279	0	2421	2291	1000	73	1	16	1	1	1493	1000	1598	1557	1580	1603	1616
1004	1612	12	33	16	33	2431	1556	859	25	1000	1000	1000	67935	0	1580	1594	1293	3	1474	1000	1000	1000	1580	1578	1	1	1001	267	2269	2252	3252	0	2429	2280	1000	73	1	16	1	1	1494	1000	1594	1612	1596	1596	1611
1004	1585	12	32	18	32	2456	1576	865	25	1000	1000	1000	70160	0	1612	1606	1286	3	1443	1000	1000	1000	1574	1587	1	1	1001	253	2267	2236	3258	0	2444	2261	1000	73	1	16	1	1	1525	1000	1589	1608	1610	1597	1591
1004	1601	12	31	15	32	2440	1589	878	25	1000	1000	1000	68945	1	1588	1612	1300	3	1466	1000	1000	1000	1582	1590	1	1	1001	260	2268	2258	3239	0	2442	2266	1000	73	1	16	1	1	1486	1000	1614	1608	1588	1604	1596
1004	1599	12	32	16	31	2424	1564	895	25	1000	1000	1000	69426	1	1573	1599	1300	3	1473	1000	1000	1000	1587	1610	1	1	1001	233	2262	2271	3256	0	2425	2256	1000	73	1	16	1	1	1498	1000	1567	1644	1614	1600	1575
1004	1603	12	32	16	32	2439	1541	869	25	1000	1000	1000	70419	1	1557	1555	1304	3	1471	1000	1000	1000	1568	1690	1	1	1001	254	2262	2282	3254	0	2419	2265	1000	73	1	16	1	1	1496	1000	1584	1598	1592	1617	1597
1004	1601	11	32	16	32	2455	1580	910	25	1000	1000	1000	69692	0	1554	1616	1295	3	1447	1000	1000	1000	1604	1588	1	1	1001	267	2255	2261	3271	0	2425	2264	1000	73	1	16	1	1	1487	1000	1613	1602	1595	1588	1609

Test 2: throughput

Code:

  prfm pldl2keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5600

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15645	118	369	193	367	0	0	24710	0	15672	9600	25	20196	10223	10000	10100	10000	131995	729345	1	36	49	12547	15503	15676	13124	3	13174	20100	10200	10000	10200	10000	15567	156	1	1	20201	100	99	2259	100	10100	100	22868	22990	32970	0	0	24758	23005	10000	0	1310	1	17	1	1	15533	10120	10000	10100	15573	15618	15556	15544	15605
20204	15648	116	362	197	365	0	0	24587	0	15510	9688	25	20211	10199	10000	10100	10000	131551	727639	1	28	49	12560	15488	15574	12861	3	13092	20100	10200	10000	10200	10000	15640	155	1	1	20201	100	99	2164	100	10100	100	22779	23000	32930	0	0	24803	23008	10000	0	1310	1	16	1	1	15548	10120	10000	10100	15535	15679	15563	15588	15631
20204	15681	117	360	199	360	0	0	24747	0	15515	9695	25	20211	10190	10000	10100	10000	130508	732651	1	39	49	12488	15638	15683	12797	3	13029	20100	10200	10000	10200	10000	15767	157	1	1	20201	100	99	2294	100	10100	100	22972	22822	33138	0	0	24718	23123	10000	0	1310	1	16	1	1	15465	10090	10000	10100	15644	15563	15702	15712	15740
20204	15671	115	364	195	361	0	0	24602	0	15574	9600	25	20184	10178	10000	10100	10000	130537	731001	1	32	49	12380	15655	15609	12913	3	13077	20100	10200	10000	10200	10000	15647	154	1	1	20201	100	99	2095	100	10100	100	23054	23095	33198	0	0	24781	22997	10000	0	1310	1	17	1	1	15608	10111	10000	10100	15563	15657	15669	15556	15599
20204	15585	117	368	195	364	0	0	24800	0	15601	9514	25	20181	10214	10000	10100	10000	131662	729748	1	31	49	12481	15661	15677	12890	3	13164	20100	10200	10000	10200	10000	15570	161	1	1	20201	100	99	2359	100	10100	100	23137	23316	32895	0	0	24875	22793	10000	0	1310	1	16	1	1	15510	10132	10000	10100	15595	15639	15529	15603	15797
20204	15570	117	364	198	362	0	0	24897	0	15543	9672	25	20190	10187	10000	10100	10000	130049	725644	1	40	49	12497	15638	15525	12877	3	13054	20100	10200	10000	10200	10000	15600	156	1	1	20201	100	99	2303	100	10100	100	22957	23014	33134	0	0	24816	23025	10000	0	1310	1	16	1	1	15439	10096	10000	10100	15623	15637	15506	15503	15732
20204	15557	116	362	194	360	0	0	24774	0	15550	9530	25	20211	10208	10000	10100	10000	130672	726608	1	36	49	12559	15710	15571	12862	3	13052	20100	10200	10000	10200	10000	15655	161	1	1	20201	100	99	2240	100	10100	100	23197	23014	33141	0	3	24683	23096	10000	0	1310	1	16	1	1	15440	10108	10000	10100	15550	15593	15662	15508	15653
20204	15714	116	362	196	360	0	0	24643	0	15623	9733	25	20217	10217	10000	10100	10000	131284	727681	0	30	49	12658	15750	15536	12882	3	13070	20100	10200	10000	10200	10000	15635	154	1	1	20201	100	99	2082	100	10100	100	22936	22997	33005	0	0	24675	23234	10000	0	1310	1	16	1	1	15450	10138	10000	10100	15597	15610	15588	15624	15638
20204	15669	117	366	191	365	0	0	24657	0	15562	9552	25	20181	10196	10000	10100	10000	130608	731010	1	44	49	12481	15578	15710	12852	3	13131	20100	10200	10000	10200	10000	15720	162	1	1	20201	100	99	2354	100	10100	100	23088	23099	33117	0	0	24693	23026	10000	0	1310	1	16	1	1	15417	10129	10000	10100	15710	15678	15716	15670	15524
20204	15563	116	356	193	358	0	0	24645	0	15649	9600	25	20235	10211	10000	10100	10000	131623	726827	0	34	49	12506	15532	15595	13079	3	12926	20100	10200	10000	10200	10000	15637	155	1	1	20201	100	99	2172	100	10100	100	22890	23060	32895	0	0	24691	23186	10000	0	1311	1	16	1	1	15443	10093	10000	10100	15486	15720	15540	15581	15587

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5755

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15803	117	350	183	344	0	24494	1	15737	9787	25	20142	10139	10000	10010	10000	132090	736892	1	61	49	12727	15767	15597	12955	3	13239	20010	10020	10000	10020	10000	15834	176	1	1	20021	10	9	2509	10	10010	10	22652	22807	32947	0	24460	22672	10000	1270	2	16	1	1	15779	10147	10000	10010	15601	15741	15838	15828	15742
20024	15751	119	351	184	345	0	24383	0	15745	9767	25	20115	10142	10000	10010	10000	133619	737287	1	43	49	12694	15708	15786	12997	3	13273	20010	10020	10000	10020	10000	15748	141	1	1	20021	10	9	2418	10	10010	10	22803	22770	32629	0	24492	22795	10000	1270	1	16	1	1	15745	10123	10000	10010	15733	15725	15833	15777	15712
20024	15850	118	350	183	346	0	24450	0	15716	9816	25	20121	10136	10000	10010	10000	133583	737912	0	43	49	12622	15738	15616	13105	3	13239	20010	10020	10000	10020	10000	15806	155	1	1	20021	10	9	2415	10	10010	10	22597	22793	32768	0	24545	22738	10000	1270	1	16	1	1	15572	10126	10000	10010	15752	15779	15812	15667	15588
20024	15826	118	345	181	345	0	24477	0	15728	9837	25	20127	10142	10000	10010	10000	132854	730279	1	55	49	12680	15809	15822	13065	3	13244	20010	10020	10000	10020	10000	15729	152	1	1	20021	10	9	2453	10	10010	10	22873	22677	32696	0	24338	22890	10000	1270	1	16	1	1	15479	10165	10000	10010	15698	15672	15811	15864	15807
20024	15785	118	346	183	344	0	24497	0	15664	9840	25	20190	10154	10000	10010	10000	133695	731485	1	45	49	12561	15716	15648	13123	3	13163	20010	10020	10000	10020	10000	15738	154	1	1	20021	10	9	2417	10	10010	10	22824	22631	32793	0	24427	22891	10000	1270	1	16	1	1	15476	10147	10000	10010	15849	15915	15725	15741	15797
20024	15723	118	348	190	351	0	24348	0	15769	9829	25	20136	10148	10000	10010	10000	132158	729701	0	46	49	12647	15678	15702	13100	3	13115	20010	10020	10000	10020	10000	15729	154	1	1	20021	10	9	2424	10	10010	10	22817	22910	32805	0	24438	22865	10000	1270	1	16	1	1	15495	10132	10000	10010	15701	15701	15841	15746	15758
20024	15680	118	348	190	346	0	24524	0	15681	9863	25	20136	10157	10000	10010	10000	132956	735447	0	44	49	12728	15792	15711	13003	3	13273	20010	10020	10000	10020	10000	15656	150	1	1	20021	10	9	2526	10	10010	10	22837	22807	32780	0	24486	22757	10000	1270	1	16	1	1	15625	10129	10000	10010	15788	15733	15825	15756	15659
20024	15704	118	345	182	347	0	24454	0	15817	9885	25	20130	10148	10000	10010	10000	132111	736519	1	36	49	12677	15717	15783	13095	3	13097	20010	10020	10000	10020	10000	15655	141	1	1	20021	10	9	2477	10	10010	10	22945	22624	32638	0	24532	22733	10000	1270	1	16	2	1	15605	10150	10000	10010	15712	15706	15858	15731	15667
20024	15780	117	345	190	346	0	24442	0	15899	9724	25	20127	10136	10000	10010	10000	134192	735375	1	37	49	12682	15765	15686	12992	3	13307	20010	10020	10000	10020	10000	15778	160	1	1	20021	10	9	2612	10	10010	10	22825	22811	32606	0	24426	22766	10000	1270	1	16	1	1	15678	10150	10000	10010	15770	15753	15656	15792	15740
20024	15679	118	342	185	347	0	24392	0	15835	9662	25	20163	10127	10000	10010	10000	131845	732423	1	44	49	12620	15834	15717	13003	3	13308	20010	10020	10000	10020	10000	15768	158	1	1	20021	10	9	2347	10	10010	10	22796	22555	32709	0	24380	22715	10000	1270	1	16	2	1	15567	10141	10000	10010	15792	15799	15784	15687	15620

Test 3: throughput

Code:

  prfm pldl2keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5444

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15459	116	331	181	351	24638	0	15390	9491	25	10100	100	10000	100	10000	500	721887	1	49	12331	0	15458	15366	13997	6	14197	10104	200	10016	200	10008	15405	12260	1	1	10201	100	99	2605	100	100	100	22706	22732	32807	0	0	24599	22818	10000	0	1	1	1	717	0	16	0	0	15334	0	10000	100	15427	15428	15439	15542	15547
10204	15536	115	332	174	334	24486	0	15475	9523	25	10100	100	10000	100	10005	500	719835	1	49	12423	0	15514	15862	13946	7	14173	10100	200	10008	200	10024	15380	12215	1	1	10201	100	99	2636	100	100	100	22741	22781	32704	0	0	24551	22711	10000	0	1	1	1	717	0	16	2	0	15357	0	10000	100	15451	15526	15493	15488	15384
10204	15433	116	332	177	338	24484	0	15467	9555	25	10100	100	10000	100	10000	500	722960	1	49	12374	0	15450	15451	13974	6	14134	10100	200	10016	200	10016	15492	12203	1	1	10201	100	99	2596	100	100	100	22982	22774	32859	0	0	24607	22775	10000	0	1	1	1	717	0	16	0	0	15345	0	10000	100	15463	15560	15423	15551	15451
10204	15457	115	339	172	337	24502	0	15417	9443	25	10100	100	10000	100	10000	500	721324	1	49	12496	0	15425	15308	13965	6	14077	10104	200	10008	200	10016	15447	12270	1	1	10201	100	99	2659	100	100	100	22760	22774	32694	0	0	24491	22812	10000	0	1	1	1	717	0	16	0	0	15336	0	10000	100	15433	15493	15472	15501	15458
10204	15437	115	333	176	336	24652	0	15452	9488	25	10100	100	10000	100	10000	500	717353	1	49	12377	0	15397	15501	14022	6	14171	10100	200	10008	200	10024	15474	12324	1	1	10201	100	99	2614	100	100	100	22694	22727	32820	0	0	24658	22818	10000	0	1	1	1	719	0	16	0	0	15458	0	10000	100	15474	15352	15444	15512	15483
10204	15418	115	334	180	329	24525	0	15536	9560	25	10100	100	10000	100	10003	500	717426	1	49	12357	0	15408	15324	13985	6	14073	10100	200	10016	200	10008	15430	12309	1	1	10201	100	99	2566	100	100	100	22770	22812	32776	0	0	24617	22578	10000	0	1	1	1	717	0	16	0	0	15312	0	10000	100	15437	15566	15388	15551	15416
10204	15426	116	334	182	336	24568	0	15446	9480	25	10100	100	10000	100	10000	500	725232	1	49	12374	0	15446	15454	14030	6	14134	10100	200	10008	200	10016	15342	12206	1	1	10201	100	99	2600	100	100	100	22716	22711	32677	0	0	24576	22752	10000	0	1	1	1	717	0	16	0	0	15295	0	10000	100	15480	15414	15486	15374	15463
10204	15530	116	331	178	333	24595	0	15462	9406	25	10100	100	10000	100	10000	500	723808	1	49	12317	0	15540	15442	14009	6	14131	10100	200	10016	200	10024	15437	12264	1	1	10201	100	99	2573	100	100	100	22732	22775	32896	0	0	24610	22734	10000	0	1	1	1	717	0	16	0	0	15312	0	10000	100	15412	15483	15454	15489	15420
10204	15426	117	337	180	336	24568	0	15396	9474	113	10100	100	10000	100	10000	500	721905	1	49	12377	0	15448	15389	14015	7	14107	10109	200	10016	200	10008	15345	12277	1	1	10201	100	99	2549	100	100	100	22733	22766	32778	0	0	24544	22757	10000	0	1	1	1	722	2	24	2	2	15313	0	10000	100	15488	15395	15498	15480	15411
10204	15458	115	337	177	337	24584	1	15477	9496	25	10100	100	10000	100	10000	500	718434	1	49	12334	0	15389	15379	13913	6	14112	10100	200	10000	200	10000	15335	12260	1	1	10201	100	99	2611	100	100	100	22930	22740	32691	0	0	24522	22766	10000	0	1	1	1	722	2	24	2	2	15344	0	10000	100	15446	15384	15426	15497	15539

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5433

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15432	116	333	169	337	0	24463	0	15468	9488	25	10010	10	10000	10	10000	50	720190	49	12390	15474	15409	14018	3	14194	10010	20	10000	20	10000	15420	15395	1	1	10021	10	9	2547	10	10	10	22829	22678	32658	0	0	24538	22815	10000	0	0	640	4	16	5	5	15305	10000	10	15504	15423	15513	15414	15469
10024	15403	116	341	182	340	0	24519	0	15397	9548	25	10010	10	10000	10	10000	50	726294	49	12376	15382	15470	14063	3	14107	10010	20	10000	20	10000	15467	15565	1	1	10021	10	9	2528	10	10	10	22650	22762	32749	0	0	24610	22758	10000	0	0	640	5	16	5	5	15315	10000	10	15416	15354	15465	15426	15468
10024	15420	116	334	172	337	0	24596	0	15427	9493	25	10010	10	10000	10	10000	50	720082	49	12292	15390	15474	13959	3	14197	10010	20	10000	20	10000	15405	15386	1	1	10021	10	9	2593	10	10	10	22829	22758	32812	0	0	24594	22807	10000	0	0	640	6	16	6	5	15363	10000	10	15515	15418	15445	15410	15581
10024	15525	115	334	180	332	0	24523	0	15372	9469	25	10063	10	10000	10	10000	50	728024	49	12351	15471	15434	13995	3	14241	10010	20	10000	20	10000	15538	15401	1	1	10021	10	9	2623	10	10	10	22763	22768	32677	0	0	24515	22770	10000	0	0	640	5	16	5	5	15395	10000	10	15395	15469	15447	15476	15492
10024	15447	115	339	177	337	0	24561	0	15408	9452	25	10010	10	10000	10	10000	50	721837	49	12358	15467	15448	14105	3	14244	10010	20	10000	20	10000	15480	15524	1	1	10021	10	9	2590	10	10	10	22758	22689	32720	0	0	24629	22690	10000	0	0	640	5	16	5	5	15438	10000	10	15389	15432	15438	15435	15403
10024	15473	116	332	176	336	0	24589	0	15466	9537	25	10010	10	10000	10	10000	50	724541	49	12450	15426	15471	14040	3	14219	10010	20	10000	20	10000	15523	15430	1	1	10021	10	9	2615	10	10	10	22688	22798	32722	0	0	24609	22856	10000	0	0	640	5	16	5	5	15307	10000	10	15423	15450	15431	15478	15473
10024	15411	115	336	174	335	0	24532	0	15378	9478	25	10010	10	10000	10	10000	50	722142	49	12227	15497	15412	14128	3	14295	10010	20	10000	20	10000	15353	15441	1	1	10021	10	9	2659	10	10	10	22756	22709	32753	0	0	24503	22754	10000	0	0	640	5	16	5	4	15301	10000	10	15396	15407	15420	15470	15426
10024	15514	116	334	173	336	0	24577	0	15497	9520	25	10010	10	10000	10	10000	50	723972	49	12271	15529	15525	14053	3	14209	10010	20	10000	20	10000	15398	15410	1	1	10021	10	9	2616	10	10	10	22715	22744	32716	0	0	24617	22808	10000	0	0	640	10	16	5	5	15229	10000	10	15492	15528	15469	15470	15414
10024	15368	115	335	174	338	0	24534	0	15416	9412	54	10010	10	10000	10	10000	50	724726	49	12437	15402	15402	14059	3	14206	10010	20	10000	20	10000	15470	15451	1	1	10021	10	9	2675	10	10	10	22697	22828	32760	0	0	24514	22729	10000	0	0	640	5	16	5	4	15345	10000	10	15431	15424	15541	15467	15446
10024	15395	115	335	177	333	0	24471	0	15426	9579	25	10010	10	10000	10	10000	50	723326	49	12513	15383	15453	14009	3	14243	10010	20	10000	20	10000	15466	15418	1	1	10021	10	9	2594	10	10	10	22802	22751	32804	0	3	24553	22687	10000	0	0	640	4	16	4	6	15423	10000	10	15363	15465	15435	15458	15481

PRFM (register, PLDL2KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations