Firestorm: AUTDB measurements

Code:

  autdb x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	0	0	192	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	2	85	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	3	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	1	3	73	1	93	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	65	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	2	85	0	0	2	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	3	73	2	85	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	2	85	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	12	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	71	0	0	0	103	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	0	0	73	1	85	0	0	1	2	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	0	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	2000	7029	870	1	1	1001	1000	1	0	73	1	85	0	0	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autdb x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	621	0	0	0	0	0	12	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	1	0	0	710	2	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	650	0	0	0	0	0	936	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	12	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	621	0	0	0	0	0	0	0	0	1869	59806	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	1	0	3	710	1	79	1	1	69796	10100	1	10100	70030	70030	70030	70030	70030
10204	70029	650	0	0	0	0	0	954	0	0	131	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	0	0	0	0	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	623	0	0	0	0	0	12	0	0	84	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	2	0	0	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	1041	0	0	264	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	3	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030
10204	70029	622	0	0	0	0	0	93	88	0	61	59824	25	10200	10200	10200	1808330	1	49	66949	70029	70029	68480	3	68674	10200	10200	20200	70029	912	1	1	10201	100	99	10100	0	0	0	18	710	1	79	1	1	69796	10100	0	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	a9	ab	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	619	0	0	103	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	3	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	8	0	0	0	0	0	640	2	79	2	3	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	89	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	2	3	0	0	640	3	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	623	0	12	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	1	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70059	70029	68502	3	68696	10020	10020	20154	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	3	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	618	0	222	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	1	0	0	48	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	618	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	20020	70029	870	1	1	10021	10	9	10010	1	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  autdb x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	80029	696	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	2	1	1	1920	1	16	1	1	79870	20100	30100	80030	80030	80030	80030	80030
30204	80029	750	0	0	0	0	0	0	12	0	159	69799	25	20200	20200	20211	4943049	1	49	76949	80029	80029	76028	7	76228	20211	20227	40254	80029	144	1	1	30201	100	99	30100	2	0	57	0	0	0	1	1	1	1941	1	16	1	1	79870	20100	30100	80030	80056	80030	80030	80030
30204	80029	748	0	0	0	0	0	0	0	0	61	69799	25	20200	20200	20211	4943049	1	49	76949	80029	80029	76020	7	76228	20211	20227	40254	80029	144	1	1	30201	100	99	30100	0	0	75	0	3	0	1	1	1	1920	1	16	1	1	79870	20100	30100	80030	80030	80030	80030	80030
30204	80029	751	0	0	0	0	0	0	12	0	61	69799	25	20200	20200	20211	4943049	1	49	76949	80029	80029	76020	7	76229	20211	20227	40254	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1	1	1	1920	1	16	1	1	79870	20100	30100	80030	80030	80030	80030	80030
30204	80029	700	0	0	0	0	0	0	0	0	349	69799	25	20200	20200	20211	4943049	1	49	76949	80029	80029	76020	7	76228	20211	20227	40254	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	1	1	1	1920	1	16	1	1	79870	20100	30100	80030	80030	80030	80030	80030
30204	80029	748	0	0	0	0	0	0	0	0	726	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	749	0	0	0	0	0	0	0	0	61	69799	25	20207	20200	20200	4942601	1	49	76949	80029	80029	75961	7	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80069	749	0	0	0	0	4	0	12	352	104	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	1	0	3	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	698	0	0	0	0	0	0	0	0	103	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80030	80030	80030	80030
30204	80029	750	0	0	0	0	0	1	0	0	61	69799	25	20200	20200	20200	4942601	1	49	76949	80029	80029	75961	3	76181	20200	20200	40200	80029	144	1	1	30201	100	99	30100	0	0	0	0	0	0	0	0	0	1910	1	72	1	1	79794	20100	30100	80030	80069	80030	80030	80030

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	80029	643	0	0	0	0	0	12	0	196	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	3	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	703	0	0	0	0	0	0	0	770	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	1	0	0	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	4	0	0	0	0	0	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	699	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	1138	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	3	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	697	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	3	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	703	0	0	0	0	0	0	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	0	1890	0	2	72	2	1	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	12	0	61	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030
30024	80029	702	0	0	0	0	0	0	0	726	69799	25	20020	20020	20020	4952048	1	49	76949	80029	80029	75983	3	76203	20020	20020	40020	80029	144	1	1	30021	10	9	30010	0	0	0	0	0	0	0	0	0	1890	0	2	72	2	2	79803	20010	30010	80030	80030	80030	80030	80030

Test 4: throughput

Count: 8

Code:

  autdb x0, x8
  autdb x1, x8
  autdb x2, x8
  autdb x3, x8
  autdb x4, x8
  autdb x5, x8
  autdb x6, x8
  autdb x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80204	80041	696	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	4	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	77	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	3	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	751	0	0	0	0	0	0	105	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	9	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	701	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	3	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	12	0	700	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	3	25	3	3	80025	80100	0	80100	80082	80036	80036	80036	80036
80204	80035	700	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	5123	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	700	0	0	0	0	12	0	225	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	2	0	0	0	0	3	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	748	0	0	0	0	0	0	147	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	1	0	0	5148	3	25	5	6	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	698	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	3	25	3	3	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	750	0	0	0	0	12	0	77	25	80200	80200	80200	401000	0	49	76955	80035	80035	69966	3	69984	80200	80200	160200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	5110	3	25	3	3	80025	80100	0	80100	80216	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	80040	693	0	0	0	0	0	0	0	18	0	0	700	25	80020	80041	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80081	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5033	0	16	25	0	17	6	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	751	0	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	7	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	1	0	3	0	0	5020	0	6	25	0	17	8	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	0	0	0	0	700	46	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5020	0	6	25	0	6	17	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	1	12	0	0	977	25	80020	80020	80020	400100	1	49	76955	0	80040	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	1	0	0	0	0	5020	0	6	25	0	6	17	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	747	0	0	0	0	0	0	0	0	0	0	700	25	80020	80020	80020	400207	1	49	76955	0	80081	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	1	0	3	0	0	5020	0	6	25	0	6	17	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	693	0	0	0	0	0	0	0	12	0	0	63	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5033	0	5	25	0	6	17	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	699	0	0	0	0	0	0	0	0	0	0	63	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	7	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	2	0	0	1	2	3	0	0	5020	0	17	25	0	17	6	80024	80010	0	80010	80036	80036	80036	80036	80036
80025	80035	699	0	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	3	0	0	5020	0	6	25	0	6	16	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80080	697	0	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	49	76955	0	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	1	0	0	0	0	5020	0	17	25	0	17	6	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	700	0	0	0	0	0	0	0	12	0	0	77	25	80020	80020	80020	400100	1	49	76955	3	80035	80035	69988	3	70006	80020	80020	160020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	5020	0	17	25	0	17	6	80024	80010	0	80010	80036	80036	80081	80036	80036

AUTDB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations