Firestorm: LDRSB (unsigned offset, 64-bit) measurements

Code:

  ldrsb x0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	45	0	0	1	359	2	1	12	19	25	1000	1000	1000	14060	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	1	1000	43	1039	0	0	1039	6	1	39	44	73	1	16	1	1	371	0	10	7	1000	395	395	399	375	395
1004	394	3	1	1	44	1	0	1	383	2	1	0	16	25	1000	1000	1000	15208	398	398	221	3	256	1000	1000	1000	374	56	1	1	1001	1000	1000	0	1000	44	1039	0	0	1000	6	0	39	44	73	1	16	1	1	371	14	0	4	1000	399	399	375	375	375
1004	398	3	1	1	44	1	0	0	383	0	1	1	0	25	1000	1000	1000	15208	398	374	221	3	256	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	0	1000	0	38	1038	6	1	39	44	73	1	16	1	1	395	0	14	7	1000	375	399	375	399	375
1004	398	3	0	0	44	0	0	0	359	2	0	1	0	25	1000	1000	1000	15274	398	398	221	3	232	1000	1000	1000	374	77	1	1	1001	1000	1000	0	1000	0	1038	1	38	1000	6	1	38	43	73	1	16	1	1	391	14	14	7	1000	399	375	395	399	399
1004	398	3	0	0	44	1	0	1	383	0	1	1	16	25	1000	1000	1000	15274	398	374	221	3	232	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	44	1038	1	41	1038	6	1	39	44	73	1	16	1	1	395	10	14	0	1000	375	399	399	375	375
1004	374	3	0	0	0	0	0	0	384	0	1	0	19	25	1000	1000	1000	15267	398	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	0	0	0	73	1	16	1	1	391	14	0	7	1000	375	375	399	376	399
1004	398	2	0	0	44	1	0	0	383	2	0	1	0	25	1000	1000	1000	14060	398	374	197	3	232	1000	1000	1000	399	79	1	1	1001	1000	1000	0	1000	43	1000	0	38	1000	6	1	39	0	73	1	16	1	1	395	14	14	0	1000	375	399	400	375	375
1004	398	3	0	0	0	1	0	1	359	2	1	1	19	25	1000	1000	1000	15267	374	398	221	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1000	0	0	1038	6	0	0	43	73	1	16	1	1	395	10	10	4	1000	399	399	399	399	399
1004	398	3	0	0	0	0	0	1	383	2	12	1	19	25	1000	1000	1000	15274	398	398	197	3	257	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	38	1038	6	1	0	0	73	1	16	1	1	371	14	0	4	1000	375	399	395	399	399
1004	398	3	1	0	44	1	0	1	379	2	1	1	19	25	1000	1000	1000	15274	398	398	217	3	256	1000	1000	1000	398	77	1	1	1001	1000	1000	0	1000	43	1038	0	0	1038	0	1	38	0	73	1	16	1	1	371	10	0	7	1000	399	399	399	402	375

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	1	1	0	0	0	0	0	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616175	3341470	0	49	67075	70050	70050	64631	3	64950	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	2	71	1	1	69813	30000	6	6	0	10000	30100	70036	70048	70051	70048	70051
40204	70047	525	0	0	0	0	0	0	0	0	0	70037	69781	59709	25	40100	30103	10001	30100	10000	616175	3342206	0	49	66970	70047	70050	64646	3	64950	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	0	0	10000	0	0	0	0	2610	1	71	1	1	69810	30003	6	0	9	10000	30100	70048	70048	70051	70048	70048
40204	70047	525	0	0	1	0	0	0	0	1	0	70035	69764	59695	25	40100	30103	10001	30100	10000	616005	3341470	0	49	66970	70035	70035	64631	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	0	0	0	10000	0	0	0	0	2610	1	71	1	1	69813	30003	6	6	9	10000	30100	70051	70036	70051	70051	70048
40204	70050	525	0	0	0	0	0	0	0	0	0	70020	69781	59706	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66967	70047	70050	64643	3	64953	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	0	0	10000	1	0	1	0	2610	1	71	1	1	69810	30000	9	6	6	10000	30100	70053	70036	70051	70036	70051
40204	70050	525	0	0	0	0	0	0	0	1	0	70036	69783	59695	25	40104	30103	10001	30100	10000	616005	3341470	0	49	66955	70050	70035	64631	3	64953	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69810	30003	6	0	7	10000	30100	70048	70051	70051	70051	70036
40204	70050	524	0	0	0	0	0	1	0	0	0	70020	69785	59708	73	40100	30100	10001	30100	10000	616005	3342062	0	49	66970	70050	70050	64631	3	64953	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69813	30000	6	6	0	10000	30100	70051	70048	70048	70048	70048
40204	70047	525	0	0	0	0	0	0	0	0	0	70035	69764	59709	25	40104	30103	10001	30100	10000	616005	3342062	0	49	66970	70035	70035	64692	3	64938	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69813	30000	6	0	9	10000	30100	70036	70036	70051	70036	70048
40204	70050	524	0	0	0	0	0	1	0	1	0	70032	69781	59695	25	40104	30103	10001	30100	10000	616005	3342206	0	49	66970	70035	70050	64646	3	64938	40100	30200	10000	60200	10000	70050	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69798	30003	9	6	0	10000	30100	70036	70036	70048	70051	70051
40204	70047	524	0	0	0	0	0	6	0	0	0	70020	69781	59695	25	40104	30103	10001	30100	10000	616015	3342206	0	49	66970	70047	70035	64646	3	64950	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69798	30000	6	0	0	10000	30100	70048	70051	70036	70036	70051
40204	70050	524	0	0	0	0	0	0	0	0	0	70035	69781	59706	25	40100	30103	10001	30100	10000	616005	3341470	0	49	66967	70035	70050	64646	3	64953	40100	30200	10000	60200	10000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	8	0	0	10000	1	0	1	0	2610	1	71	1	1	69798	30003	0	6	0	10000	30100	70036	70051	70036	70051	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	0	0	0	1	1	0	0	1	0	1	70032	69728	59695	25	40010	30013	10001	30010	10000	616952	3341470	0	0	49	66967	70035	70047	64665	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	2520	16	71	6	14	69798	30003	6	6	6	10000	30010	70048	70048	70048	70048	70048
40024	70035	525	0	0	0	1	0	0	0	1	0	1	70032	69728	59695	25	40014	30010	10001	30010	10000	616988	3342062	0	5	49	66967	70047	70047	64670	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	2520	5	71	13	5	69810	30003	6	6	0	10000	30010	70036	70048	70048	70048	70036
40024	70035	524	0	0	0	1	0	0	0	1	0	0	70020	69743	59706	25	40014	30013	10001	30010	10000	617068	3342062	0	5	49	66967	70035	70047	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	2520	11	71	14	4	69810	30003	6	0	0	10000	30010	70048	70048	70048	70048	70048
40024	70050	525	0	0	0	0	0	0	0	0	0	0	70020	69728	59695	25	40010	30013	10001	30010	10000	616952	3342062	0	5	49	66967	70035	70038	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	0	2520	14	71	5	14	69810	30000	6	6	0	10000	30010	70048	70048	70036	70048	70048
40024	70047	524	0	0	0	0	0	0	0	1	0	1	70020	69743	59706	25	40014	30013	10001	30010	10000	616952	3341470	0	5	49	66974	70035	70047	64653	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	2520	14	71	14	4	69810	30003	6	6	6	10000	30010	70048	70036	70036	70048	70036
40024	70035	524	0	0	0	0	0	0	0	1	0	0	70032	69760	59706	25	40014	30013	10001	30010	10000	616952	3342206	0	5	49	66955	70047	70035	64653	3	64960	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	2520	14	71	11	4	69810	30000	6	6	0	10000	30010	70048	70048	70036	70048	70036
40024	70035	525	0	0	0	0	0	0	0	0	0	0	70020	69743	59695	25	40014	30010	10000	30010	10000	616961	3341470	0	5	49	66955	70047	70047	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	0	0	0	2520	5	71	5	14	69810	30003	6	6	6	10000	30010	70048	70048	70036	70048	70048
40024	70047	525	0	0	0	0	0	0	0	1	0	0	70035	69743	59706	25	40014	30013	10001	30010	10000	617068	3341470	0	5	49	66955	70035	70047	64665	3	64960	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	2520	6	71	14	14	69810	30000	6	0	6	10000	30010	70036	70085	70048	70048	70051
40024	70050	524	0	0	1	0	1	0	0	0	0	0	70032	69728	59695	25	40014	30010	10001	30010	10000	617068	3342062	0	5	49	66955	70047	70047	64665	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	0	1	0	2520	14	71	5	14	69798	30000	6	6	0	10000	30010	70051	70036	70036	70051	70048
40024	70047	525	0	0	0	0	1	0	0	1	0	0	70032	69760	59695	25	40014	30013	10001	30010	10000	616952	3342062	0	5	49	66967	70035	70035	64653	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	2520	5	71	5	13	69810	30003	6	0	6	10000	30010	70048	70036	70048	70036	70036

Test 3: throughput

Count: 8

Code:

  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26728	200	0	0	0	0	0	0	0	66	1	0	2	26703	3	0	7	20	25	80100	100	80000	100	80000	500	1172437	0	49	23656	26737	26736	16659	3	16694	80100	200	80000	200	80000	26736	64	1	1	80201	100	99	100	80000	100	80000	1	100	80020	18	0	0	80059	0	0	0	21	80039	6	1	19	43	19	1	0	5110	3	16	3	3	26734	0	10	4	80000	100	26728	26708	26732	26728	26728
80204	26707	200	0	0	0	0	0	0	0	45	0	0	1	26894	3	7	7	20	25	80100	100	80000	100	80000	500	1166101	1	49	23634	26714	26736	16659	3	16694	80100	200	80000	200	80000	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	43	0	80018	1	0	1	60	80039	6	1	59	43	19	1	0	5110	3	16	3	3	26799	0	0	5	80000	100	26737	26716	26737	26738	26737
80204	26714	200	1	0	1	1	0	0	0	67	0	0	3	26704	3	7	7	19	25	80100	100	80000	100	80000	500	1167555	0	49	23634	26736	26736	16637	3	16694	80100	200	80000	200	80000	26736	64	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	43	0	80059	1	0	0	61	80039	6	1	58	43	19	2	0	5110	3	16	3	2	26734	0	0	7	80000	100	26708	26732	26708	26708	26708
80204	26731	200	0	0	0	0	0	0	0	45	1	0	1	26730	2	1	12	0	25	80100	100	80000	100	80000	500	1167127	1	49	23651	26731	26731	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	0	0	80000	0	0	0	38	80038	0	0	38	0	0	0	0	5110	3	16	2	3	26728	14	10	4	80000	100	26732	26708	26728	26708	26728
80204	26707	200	0	0	0	0	0	0	0	0	0	0	1	26692	2	12	1	19	25	80100	100	80000	100	80000	500	1166525	0	49	23647	26707	26731	16654	3	16665	80100	200	80000	200	80000	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80038	0	35	0	41	80038	6	0	38	0	0	0	0	5110	2	16	3	3	26704	14	14	7	80000	100	26816	26734	26883	26729	26728
80204	26727	200	0	0	0	0	0	0	0	44	0	0	0	26698	0	1	0	16	25	80100	100	80000	100	80000	500	1167127	1	49	23651	26707	26731	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80000	0	0	0	0	80000	6	0	0	44	0	0	0	5110	3	16	3	3	26704	14	0	7	80000	100	26732	26732	26728	26732	26708
80204	26731	200	0	0	0	0	0	0	0	44	0	0	1	26711	2	0	1	19	25	80100	100	80000	100	80000	500	1167127	1	49	23651	26731	26731	16654	3	16689	80100	200	80000	200	80000	26731	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80038	0	0	0	38	80000	6	0	39	44	0	0	0	5110	3	16	3	3	26704	0	14	4	80000	100	26732	26732	26711	26728	26732
80204	26731	200	0	0	0	0	0	0	0	44	0	0	1	26714	2	0	0	19	25	80100	100	80000	100	80000	500	1166525	0	49	23651	26731	26731	16654	3	16689	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80038	0	0	0	0	80038	0	1	0	44	0	0	0	5110	2	16	3	3	26728	14	0	0	80000	100	26708	26732	26732	26708	26732
80204	26731	200	0	0	0	0	0	0	0	44	0	0	1	26732	2	1	1	0	25	80100	100	80000	100	80000	500	1165556	1	49	23627	26727	26707	16654	3	16685	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	0	80038	0	0	0	38	80038	6	1	38	44	0	0	0	5110	3	16	3	3	26704	0	14	4	80000	100	26708	26708	26732	26728	26708
80204	26731	200	0	0	0	0	0	0	0	0	0	0	0	26727	0	1	12	16	25	80100	100	80000	100	80000	500	1165556	0	49	23627	26731	26727	16654	3	16665	80100	200	80000	200	80000	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80000	0	0	0	38	80038	6	0	39	0	0	0	0	5110	3	16	2	3	26728	10	0	4	80000	100	26732	26708	26732	26732	26732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26741	201	0	0	1	0	1	1	70	1	0	3	26722	0	7	7	19	25	80010	10	80000	10	80000	50	1167106	1	49	23661	26715	26741	16689	3	16717	80010	20	80000	20	80000	26736	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80021	20	0	80060	1	0	1	21	80038	6	1	19	43	19	1	5020	5	16	0	4	5	26734	13	13	5	80000	10	26737	26737	26737	26737	26738
80024	26737	200	1	0	0	0	0	1	0	0	0	1	26716	2	1	0	19	25	80010	10	80000	10	80000	50	1166750	1	49	23648	26731	26731	16652	3	16708	80010	20	80000	20	80000	26727	56	1	1	80021	10	9	0	10	80000	10	80000	1	10	80000	0	43	80038	0	0	0	38	80039	6	1	39	44	0	0	5020	5	16	0	6	5	26705	14	14	0	80000	10	26709	26732	26732	26732	26732
80024	26731	200	0	0	1	1	1	1	67	1	0	3	26700	2	0	0	0	25	80010	10	80000	10	80000	50	1167219	1	49	23656	26736	26715	16681	3	16716	80010	20	80000	20	80000	26714	64	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	80019	1	0	0	63	80000	6	1	59	43	19	1	5020	5	16	0	5	6	26735	13	0	5	80000	10	26737	26716	26737	26737	26715
80024	26737	201	1	0	0	0	0	1	44	0	0	1	26716	0	0	0	16	25	80010	10	80000	10	80000	50	1167501	1	49	23634	26715	26736	16659	3	16716	80010	20	80000	20	80000	26715	85	1	1	80021	10	9	0	10	80000	10	80000	0	10	80019	20	43	80058	0	0	0	60	80040	6	1	39	44	0	0	5020	5	16	0	6	5	26705	14	14	4	80000	10	26732	26732	26709	26728	26732
80024	26708	200	0	0	0	0	1	1	44	0	0	0	26693	0	0	0	0	25	80010	10	80000	10	80000	50	1167201	1	49	23628	26728	26731	16676	3	16711	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80000	0	0	0	38	80039	0	1	59	43	19	1	5020	5	16	0	5	6	26734	13	13	5	80000	10	26757	26715	26743	26715	26737
80024	26715	200	1	0	0	0	0	0	44	0	0	1	26693	0	0	1	19	25	80010	10	80000	10	80000	50	1166750	0	49	23671	26731	26731	16676	3	16711	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80038	0	0	0	39	80038	6	1	18	0	19	1	5020	6	16	0	5	5	26734	13	0	5	80000	10	26715	26737	26715	26737	26737
80024	26736	200	1	0	0	0	0	0	44	0	0	1	26716	2	0	1	16	25	80010	10	80000	10	80000	50	1166750	0	49	23651	26708	26731	16652	3	16711	80010	20	80000	20	80000	26731	56	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	39	80038	6	1	58	43	19	1	5020	5	16	0	4	5	26734	13	13	5	80000	10	26737	26737	26737	26737	26738
80024	26737	201	1	0	1	0	0	1	66	0	0	1	26700	2	7	7	19	25	80010	10	80000	10	80000	50	1167791	0	49	23628	26731	26731	16676	3	16688	80010	20	80000	20	80000	26731	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80038	0	0	0	0	80039	6	0	19	43	19	1	5020	6	16	4	6	5	26712	13	13	0	80000	10	26716	26738	26738	26738	26716
80024	26736	200	1	0	1	0	0	1	44	0	0	2	26693	2	1	1	19	25	80010	10	80000	10	80000	50	1166750	1	49	23628	26731	26728	16652	3	16688	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80038	0	0	0	38	80039	6	1	0	43	0	0	5020	6	16	0	5	7	26705	0	0	0	80000	10	26709	26732	26709	26709	26732
80024	26731	200	0	0	1	0	1	0	21	0	0	3	26722	2	7	7	20	25	80010	10	80000	10	80000	50	1166960	1	49	23651	26731	26731	16652	3	16711	80010	20	80000	20	80000	26708	77	1	1	80021	10	9	0	10	80000	10	80000	0	10	80000	0	43	80000	0	0	0	38	80000	6	1	39	0	0	0	5020	6	16	0	7	5	26728	14	14	7	80000	10	26732	26732	26732	26732	26732

LDRSB (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations