Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stnp w0, w1, [x6]
mov x0, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | 1e | 3d | 3f | 46 | 49 | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d cache miss st (a2) | st unit uop (a7) | l1d cache writeback (a8) | af | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | st nt uop (e5) | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 3 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 1 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 3 | 0 | 1 | 525 | 8 | 8 | 453 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 0 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
| 1004 | 540 | 4 | 0 | 1 | 525 | 8 | 8 | 25 | 1000 | 1000 | 1000 | 22352 | 540 | 540 | 353 | 3 | 398 | 1000 | 1000 | 3000 | 540 | 540 | 1 | 1 | 1001 | 1000 | 1000 | 1000 | 1000 | 1000 | 1 | 1000 | 1000 | 73 | 1 | 16 | 1 | 1 | 537 | 1000 | 1000 | 541 | 541 | 541 | 541 | 541 |
Code:
stnp w0, w1, [x6] add x6, x6, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 38 | 3f | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | st nt uop (e5) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 20209 | 10040 | 75 | 1 | 1 | 1 | 0 | 0 | 7 | 1248 | 10025 | 2 | 25 | 20101 | 10100 | 10000 | 10104 | 10000 | 544030 | 468824 | 2 | 49 | 6960 | 10040 | 10040 | 7430 | 6 | 7492 | 20104 | 10208 | 10008 | 10208 | 30024 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10007 | 8 | 10000 | 0 | 10007 | 2 | 0 | 7 | 10000 | 7 | 10000 | 7 | 1 | 1 | 1 | 1 | 1317 | 0 | 16 | 0 | 0 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 75 | 1 | 1 | 1 | 1 | 0 | 7 | 1248 | 10025 | 3 | 25 | 20102 | 10101 | 10000 | 10104 | 10000 | 544044 | 468824 | 3 | 49 | 6960 | 10040 | 10040 | 7430 | 7 | 7492 | 20104 | 10208 | 10008 | 10208 | 30024 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10007 | 7 | 10000 | 1 | 10007 | 1 | 1 | 7 | 10000 | 7 | 10000 | 7 | 0 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 76 | 1 | 0 | 1 | 1 | 3 | 7 | 1248 | 10025 | 3 | 25 | 20102 | 10100 | 10000 | 10100 | 10000 | 543996 | 468824 | 2 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10008 | 7 | 10000 | 1 | 10007 | 0 | 1 | 136 | 10000 | 7 | 10000 | 7 | 1 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 75 | 1 | 1 | 1 | 1 | 0 | 7 | 1248 | 10025 | 4 | 25 | 20101 | 10100 | 10000 | 10100 | 10000 | 543998 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10009 | 8 | 10000 | 1 | 10007 | 5 | 1 | 10 | 10000 | 7 | 10000 | 7 | 1 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 75 | 1 | 1 | 0 | 1 | 0 | 7 | 1248 | 10025 | 4 | 25 | 20102 | 10102 | 10000 | 10100 | 10000 | 543994 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10008 | 7 | 10000 | 1 | 10007 | 0 | 1 | 7 | 10000 | 7 | 10000 | 7 | 1 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 75 | 1 | 0 | 1 | 1 | 0 | 7 | 1248 | 10025 | 3 | 25 | 20102 | 10101 | 10000 | 10100 | 10000 | 543994 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10009 | 8 | 10000 | 2 | 10007 | 0 | 1 | 7 | 10000 | 7 | 10000 | 7 | 0 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 75 | 1 | 1 | 1 | 1 | 6 | 7 | 1248 | 10025 | 3 | 25 | 20101 | 10101 | 10000 | 10100 | 10000 | 544008 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10008 | 7 | 10000 | 1 | 10007 | 0 | 0 | 7 | 10000 | 7 | 10000 | 7 | 0 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 75 | 1 | 1 | 1 | 1 | 0 | 7 | 1248 | 10025 | 3 | 25 | 20101 | 10103 | 10000 | 10100 | 10000 | 543992 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10007 | 7 | 10000 | 1 | 10007 | 0 | 0 | 7 | 10000 | 7 | 10000 | 7 | 0 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 75 | 1 | 1 | 1 | 0 | 0 | 7 | 1248 | 10025 | 4 | 25 | 20103 | 10100 | 10000 | 10249 | 10000 | 543994 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10008 | 8 | 10000 | 0 | 10007 | 4 | 0 | 10 | 10000 | 7 | 10000 | 7 | 0 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20204 | 10040 | 76 | 1 | 1 | 1 | 0 | 0 | 7 | 1248 | 10025 | 3 | 25 | 20101 | 10101 | 10000 | 10100 | 10000 | 543998 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 7424 | 3 | 7498 | 20100 | 10200 | 10000 | 10200 | 30000 | 10040 | 123 | 1 | 1 | 20201 | 100 | 99 | 100 | 10000 | 10100 | 10000 | 100 | 10008 | 7 | 10000 | 0 | 10007 | 3 | 0 | 10 | 10000 | 7 | 10000 | 7 | 2 | 0 | 0 | 0 | 1310 | 1 | 16 | 1 | 1 | 10037 | 10007 | 10000 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | 1e | 38 | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | bc | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | st nt uop (e5) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 20029 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 543433 | 468824 | 1 | 1 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 0 | 9 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10011 | 10000 | 10010 | 10000 | 543435 | 468824 | 1 | 1 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 0 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 76 | 0 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 543433 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 0 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 6 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 543433 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 0 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10110 | 10000 | 10010 | 10000 | 543433 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 1 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10051 | 543425 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 1 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 543433 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 4 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 543433 | 468824 | 0 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 0 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 543433 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 1 | 3 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 1 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 20024 | 10040 | 75 | 0 | 1249 | 10025 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 543433 | 468824 | 1 | 0 | 49 | 6960 | 10040 | 10040 | 7446 | 3 | 7520 | 20010 | 10020 | 10000 | 10020 | 30000 | 10040 | 124 | 1 | 1 | 20021 | 10 | 9 | 10 | 10000 | 10010 | 10000 | 10 | 10000 | 10000 | 10000 | 1 | 0 | 10000 | 0 | 10000 | 1270 | 1 | 16 | 1 | 2 | 10037 | 10000 | 10000 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Code:
stnp w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 0.5209
| retire uop (01) | cycle (02) | 03 | 1e | 3a | 3d | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | ac | af | l1d cache miss st nonspec (c0) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | st nt uop (e5) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10205 | 5209 | 39 | 0 | 0 | 18 | 5194 | 144 | 144 | 168 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 237288 | 49 | 2128 | 5209 | 5208 | 3859 | 6 | 3905 | 10100 | 200 | 10000 | 200 | 30000 | 5209 | 4121 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 100 | 0 | 10000 | 0 | 3 | 10000 | 10000 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 5205 | 10000 | 10000 | 100 | 5209 | 5210 | 5209 | 5210 | 5209 |
| 10204 | 5208 | 39 | 0 | 0 | 18 | 5193 | 144 | 144 | 152 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 237288 | 49 | 2128 | 5209 | 5208 | 3859 | 6 | 3904 | 10100 | 200 | 10000 | 200 | 30000 | 5208 | 4122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 100 | 0 | 10000 | 0 | 3 | 10000 | 10000 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 5205 | 10000 | 10000 | 100 | 5214 | 5209 | 5210 | 5209 | 5210 |
| 10204 | 5209 | 39 | 0 | 0 | 18 | 5194 | 144 | 144 | 152 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 237288 | 49 | 2128 | 5209 | 5208 | 3859 | 14 | 4110 | 10100 | 200 | 10000 | 200 | 30000 | 5208 | 4122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 84 | 0 | 10000 | 0 | 0 | 10000 | 10000 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 5206 | 10000 | 10000 | 100 | 5209 | 5214 | 5209 | 5210 | 5209 |
| 10204 | 5208 | 39 | 0 | 0 | 18 | 5194 | 144 | 144 | 168 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 237336 | 49 | 2128 | 5209 | 5208 | 3859 | 6 | 3904 | 10100 | 200 | 10000 | 200 | 30000 | 5208 | 4122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 84 | 0 | 10000 | 0 | 0 | 10000 | 10000 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 5205 | 10000 | 10000 | 100 | 5210 | 5209 | 5210 | 5209 | 5210 |
| 10204 | 5209 | 39 | 0 | 0 | 18 | 5193 | 144 | 144 | 152 | 25 | 10100 | 100 | 10000 | 100 | 10006 | 500 | 237442 | 49 | 2128 | 5209 | 5208 | 3877 | 7 | 3910 | 10106 | 200 | 10016 | 200 | 30048 | 5208 | 4122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 84 | 0 | 10000 | 0 | 0 | 10000 | 10000 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 5205 | 10000 | 10000 | 100 | 5210 | 5209 | 5210 | 5209 | 5210 |
| 10204 | 5209 | 39 | 0 | 0 | 18 | 5193 | 144 | 144 | 152 | 25 | 10100 | 100 | 10000 | 100 | 10108 | 500 | 237442 | 49 | 2128 | 5208 | 5209 | 3878 | 7 | 3911 | 10106 | 200 | 10016 | 200 | 30048 | 5209 | 4121 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 100 | 0 | 10000 | 36 | 0 | 10000 | 10000 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 5206 | 10000 | 10000 | 100 | 5209 | 5210 | 5209 | 5210 | 5209 |
| 10204 | 5208 | 39 | 0 | 0 | 18 | 5194 | 144 | 144 | 168 | 25 | 10100 | 100 | 10000 | 100 | 10006 | 500 | 237490 | 49 | 2129 | 5208 | 5209 | 3878 | 7 | 3911 | 10106 | 200 | 10016 | 202 | 30048 | 5209 | 4121 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 84 | 0 | 10000 | 0 | 0 | 10000 | 10000 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 5602 | 10000 | 10000 | 100 | 5210 | 5209 | 5210 | 5209 | 5210 |
| 10204 | 5209 | 39 | 0 | 0 | 18 | 5194 | 144 | 144 | 152 | 25 | 10100 | 100 | 10000 | 100 | 10006 | 500 | 237442 | 49 | 2128 | 5209 | 5208 | 3877 | 7 | 3910 | 10106 | 200 | 10016 | 200 | 30048 | 5208 | 4122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 100 | 0 | 10000 | 0 | 3 | 10000 | 10000 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 5205 | 10000 | 10000 | 100 | 5210 | 5209 | 5210 | 5209 | 5210 |
| 10204 | 5209 | 39 | 0 | 0 | 18 | 5194 | 144 | 144 | 168 | 25 | 10100 | 100 | 10000 | 100 | 10006 | 500 | 237490 | 49 | 2128 | 5209 | 5208 | 3877 | 7 | 3910 | 10106 | 200 | 10016 | 200 | 30048 | 5208 | 4122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 100 | 0 | 10000 | 0 | 0 | 10000 | 10000 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 5206 | 10000 | 10000 | 100 | 5210 | 5209 | 5210 | 5209 | 5210 |
| 10204 | 5209 | 39 | 0 | 0 | 18 | 5193 | 144 | 144 | 168 | 25 | 10100 | 100 | 10000 | 100 | 10006 | 500 | 237490 | 49 | 2129 | 5208 | 5209 | 3878 | 7 | 3911 | 10106 | 200 | 10016 | 200 | 30048 | 5209 | 4121 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10000 | 0 | 10000 | 100 | 0 | 10000 | 2 | 3 | 10018 | 10000 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 5206 | 10000 | 10000 | 100 | 5209 | 5210 | 5209 | 5210 | 5209 |
Result (median cycles for code): 0.5209
| retire uop (01) | cycle (02) | 03 | 09 | 18 | 1e | 3d | 3f | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | a4 | st unit uop (a7) | l1d cache writeback (a8) | ac | af | l1d cache miss st nonspec (c0) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | st nt uop (e5) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10025 | 5209 | 39 | 0 | 0 | 0 | 18 | 5193 | 144 | 144 | 168 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237416 | 0 | 49 | 2128 | 5209 | 5208 | 3893 | 3 | 3939 | 10010 | 20 | 10000 | 20 | 30000 | 5209 | 5208 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 84 | 10000 | 2 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5206 | 10000 | 10000 | 10 | 5209 | 5210 | 5209 | 5210 | 5209 |
| 10024 | 5208 | 39 | 0 | 0 | 0 | 18 | 5194 | 144 | 144 | 168 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237464 | 0 | 49 | 2129 | 5208 | 5209 | 3894 | 3 | 3939 | 10010 | 20 | 10000 | 20 | 30000 | 5209 | 5208 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 100 | 10000 | 8 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5205 | 10000 | 10000 | 10 | 5209 | 5210 | 5209 | 5210 | 5209 |
| 10024 | 5208 | 39 | 0 | 0 | 0 | 18 | 5194 | 144 | 144 | 168 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237416 | 0 | 49 | 2129 | 5208 | 5209 | 3894 | 3 | 3939 | 10010 | 20 | 10000 | 20 | 30000 | 5209 | 5208 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 84 | 10000 | 0 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5206 | 10000 | 10000 | 10 | 5209 | 5210 | 5209 | 5210 | 5213 |
| 10024 | 5208 | 38 | 0 | 0 | 0 | 18 | 5193 | 144 | 144 | 152 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237416 | 1 | 49 | 2128 | 5209 | 5208 | 3893 | 3 | 3938 | 10010 | 20 | 10000 | 20 | 30000 | 5208 | 5209 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 84 | 10000 | 3 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5205 | 10000 | 10000 | 10 | 5209 | 5210 | 5209 | 5210 | 5209 |
| 10024 | 5208 | 39 | 0 | 0 | 0 | 18 | 5193 | 144 | 144 | 168 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237464 | 0 | 49 | 2129 | 5208 | 5209 | 3894 | 3 | 3939 | 10010 | 20 | 10000 | 20 | 30000 | 5209 | 5208 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 100 | 10000 | 15 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5206 | 10000 | 10000 | 10 | 5209 | 5210 | 5209 | 5210 | 5213 |
| 10024 | 5212 | 39 | 0 | 0 | 0 | 18 | 5193 | 144 | 144 | 152 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237416 | 0 | 49 | 2128 | 5209 | 5208 | 3893 | 3 | 3938 | 10010 | 20 | 10000 | 20 | 30000 | 5208 | 5209 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 100 | 10000 | 16 | 117 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5205 | 10000 | 10000 | 10 | 5209 | 5210 | 5209 | 5210 | 5209 |
| 10024 | 5208 | 39 | 0 | 0 | 0 | 18 | 5193 | 144 | 144 | 168 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237464 | 1 | 49 | 2129 | 5208 | 5209 | 3894 | 3 | 3939 | 10010 | 20 | 10000 | 20 | 30000 | 5209 | 5208 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 84 | 10000 | 20 | 78 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5206 | 10000 | 10000 | 10 | 5214 | 5209 | 5210 | 5209 | 5210 |
| 10024 | 5209 | 39 | 0 | 0 | 0 | 18 | 5193 | 144 | 144 | 152 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237416 | 1 | 49 | 2129 | 5208 | 5209 | 3894 | 3 | 3939 | 10010 | 20 | 10000 | 20 | 30000 | 5209 | 5208 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 84 | 10000 | 0 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5206 | 10000 | 10000 | 10 | 5210 | 5209 | 5210 | 5209 | 5214 |
| 10024 | 5209 | 39 | 0 | 0 | 0 | 18 | 5193 | 144 | 144 | 168 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237464 | 0 | 49 | 2128 | 5209 | 5208 | 3893 | 3 | 3938 | 10010 | 20 | 10000 | 20 | 30000 | 5208 | 5209 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 100 | 10000 | 0 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5205 | 10000 | 10000 | 10 | 5211 | 5210 | 5209 | 5210 | 5209 |
| 10024 | 5208 | 39 | 0 | 0 | 0 | 18 | 5194 | 144 | 144 | 168 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 237464 | 0 | 49 | 2129 | 5208 | 5209 | 3894 | 3 | 3939 | 10010 | 20 | 10000 | 20 | 30000 | 5209 | 5208 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10000 | 0 | 10000 | 100 | 10000 | 0 | 0 | 10000 | 10000 | 640 | 3 | 16 | 3 | 3 | 5205 | 10000 | 10000 | 10 | 5210 | 5210 | 5209 | 5210 | 5209 |