Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDPSW (pre-index)

Test 1: uops

Code:

  ldpsw x0, x1, [x6, #8]!
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0f18191e202223292b3a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int load (95)inst ldst (9b)l1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaabacafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
30051040811100006518100020102500222125200010001000100010005284345591104010405743648200010002000100010001040381110011000100010677262104770300838104046104463700731161110371000492501000200010411041104110411041
300410407111100068020001010250022152520001000100010001000528454559110401040574364820001000200010001000104038111001100010001009806310322016001910134862763720731161110371000412901000200010411041104110411041
300410407101000080141000101025101111128252000100010001000100052822455891040104057436482000100020001000100010403811100110001000103180601065101601835105456552717044731161110371000342701000200010411041104110411041
3004104081010000971510004010251007212825200010001000100010005284845587104010405743648200010002000100010001040381110011000100010227170108451190646105850843477046731161110371000302701000200010411041104110411041
3004104081100000702800240101025805519252000100010001000100052851455901040104057436482000100020001000100010403811100110001000106283601047101510102510515654363600731161110371000282901000200010411041104110411041
30041040811110008828100060102516161230252000100010001000100052812455891040104057436482000100020001000100010403811100110001000103080661047702201222106656630717042731161110371000293601000200010411041104110411041
3004104081010000842810004010251853172225200010001000100010005282645589104010405743648206610002000100010001040381110011000100010217059104400200143310364251847710731161110371000312901000200010411041104110411041
30041040811110007001004412102500222825200010001000100010005284845588104010405743648200010002000100010001040381110011000100010437268106312022084010664981790700731161110371000352701000200010411041104110411041
30041040711110001201810044010251605419252000100010001000100052831455901040104057436482000100020001000100010403811100110001000100760551022002002210134262271710731161110371000412701000200010411041104110411041
300410407101100054151004101025142104202520001000100010001000528474559210401040574364820001000200010001000104038111001100010001038808010443032062510454862971610731161110371000293801000200010411041104110411041

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldpsw x0, x1, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1864

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f191e2022293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6020971853539200000036381525681184717798075171607255067540672101394010010000618205273961304968688719397158064033036406650100402002000070200100007192735114020110099100100003010010000010010895314750810596235109811283110891111811622826102581171477404328631041119010000501007163871874719727171271849
60204720805372202000314784253621447174280061713522550730406561013440100100006190462746417049687797187071833640160364213501004020020000702001000071762351140201100991001000030100100000100108802163507106732576934942610918114812621626101571171700405521036117795510000501007176771822718457187371917
6020471826537200400044182625522220717547816171624255073540588101344010010000617322274780404968715718007171764134036410550100402002000070200100007163535114020110099100100003010010000010010929116150710676249895618624108531217114198261015611716774050010271058105010000501007183571623718357172271667
602047192553611000004118022520119672590778517146225507004065210130401001000061708227386531496873171933719006400703641715010040200200007020010000717033511402011009910010000301001000001001090911605181063024710936742510932109710910626401571171709404881010916105410000501007156371826715537192171863
60204717945381000000355780251212207183079551717602550720405601012640100100006186372744773049687587185271696639210364430501004020020000702001000071978351140201100991001000030100100000100108791180520106292771191464201089312961031082610157117162540496940950100610000501007185771440717427160571868
6020471628538100000039580625361240716887614171550255074040580101254010010000619035274238904968720716717192063983036427250100402002000070200100007174835114020110099100100003010010000010010851116651710669247893411234109021105101157261015711716974056098888697010000501007176371577718527190371656
6020471820538100101039981125361212716777926171668255071040580101154010010000619018273864004968532718897176963827036412750100402002000070200100007170335114020110099100100003010010000010010912116150410682253997770431091913171091116261015611717074052810101105105210000501007194771866719377196271638
6020472018538100100273482635361264721607825171610255077040654101224010010165617478274258204968815718617166764095012642895010040200200007020010000719483511402011009910010000301001000001001090211474681062224810898124321091810871071117261015711715614049699897299310000501007171871822717807174971835
60204717725371003010471796251213007169778150713992550655405921012840100100006181532746078049686467178371730637420364218501004020020000702001000071879351140201100991001000030100100000100108991118485106732641396111630109171097121106261015711716464043210141073105410000501007180071773718757192471726
6020471719557110300042982625041252716687565171488255076040616101154010010000617504274078504968800717737192963981036429450100402002000070200100007192335114020110099100100003010010000010010887116047010634276994513041108821238115167261015711716634050099894498810000501007197271701718907186871952

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1814

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2022293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6002971493535000000005540833173601087169379611715312550685405381010740010100006181892747407149687707176771949640343640935001040020200007002010000718053511400211091010000300101000001010928113647810653276159447238109151383138003252045664716414056099093098010000500107188971983717867181571786
6002471904539000000005980872174401407176081700715712550720405421011940010100006173972740977149687087175871714639293642435001040020200007002010000717193511400211091010000300101000001010936016951210636250159027443109051301120114252046445715764052896692284410000500107187771728718747176671694
600247175553710000000564085316880108719498111171521425059040586101404001010000617703275143214968651717707160564040364201500104002020000700201000071831351140021109101000030010100000101092511575001065026214949744410955126413000725204564371791405248721110103610000500107188571750716147184471866
6002471796539000000005230859172811567174982311716412550730405221013440010100006176542748502049688607185271867640563643395001040020200007002010000716683511400211091010000300101000001010940015047610658285149314446109591452134109252056454716604054494495298610000500107186571894719517186871760
6002471659536101000005990818168001127177482211716042550640405141014240010100006175912741109149687467169471944640673641005001040020200007002010000718443511400211091010000300101000001010888016350610645286109404843109761302139105252046434715124050897095497810000500107179472055719977192271853
6002471698539111000005340847173601087178380411716082550685405741013440010100006180632744662049687827164871683639573640395001040020200007002010000716793511400211091010000300101000001010910115448810665301119287639109281363130005252065644715614050893694695210000500107189171784717937184771832
6002471972537000000005730826172811607171482411714592550610405421013240010100006187342741910049688267195371856639413642525001040020200007002010000717973511400211091010000300101000001010946013847510661267118907646109491425131103252046444714964054497695283010000500107179371874717567191571718
6002471791537100001005300851173601047196082011715342550734404821012640010100006193682739546049686367210071901642143643255001040020200007002010000717963511400211091010000300101000001010934317149810634272169149650109421334128035252045644717524053690693499410000500107163371736717367172471805
6002471792539000000004990836173601007193180911715672550725405421012040010100006185042742159049688207183172004639153641865001040020200007002010000718423511400211091010000300101000001010928014550310641265139284440109491304128113254146444716194054494492496010000500107182371902718137212371747
60024718295371011000062408401760013671910816117163925505854050210132400101000061872927515801496878771843718106397436417450010400202000070020100007177035114002110910100003001010000010109361136522106012631291732411093013011340002520456447173340580916888101010000500107184971926718377199071797

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldpsw x0, x1, [x6, #8]!
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1876

retire uop (01)cycle (02)030e0f191e2022293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)c2c3branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60209720435390003968251736012871842791007160725506504060410135401001000061771927364571496876107196671904641800364095501004020020000702001000071788351140201100991001000030100100000100108711314861065023310885441510911121112209026102561171616405361020960107810000501007192671979718127180771856
6020471947537000421853172019271926810007166325506554059210118401001000061700827486341496874407191671939639560364264501004020020000702001000071912351140201100991001000030100100000100109251514781062425199219215109251340132030261015611717264053212191052102310000501007177971737718687174171956
6020471870538000408800173609271805799007143925507054060010127401001000061921727485211496889907170971993639190364303501004020020000702001000071985351140201100991001000030100100000100109081735601062828110884501410912118013933026101561171540405201064101899710000501007191471781718877181171928
60204718115380004338171704113271957810007141925507104056410118401001000061934427394971496862807191071989641260364168501004020020000702001000071873351140201100991001000030100100000100109361754751064828179301369108631230119390261015611715484050811281080101710000501007176471788717807189371922
60204718945370103537981536110071912793007151825506754059210119401001000062011727460171496883907198171781641020364288501004020020000702001000071748351140201100991001000030100100000100109001505271063324588864815108781180121030261015611716994046010571042107910000501007169171924717987183871899
602047175753801043278716961128718407900071644255072540532101214010010000620326275073114968539071761719136398303642075010040200200007020010000718783511402011009910010000301001000001001092214151410648267109185018109131150128550261015811716644046810501082109910000501007205271688718957189171894
602047163253700034679117121567181176700714882550675406081012440100100006190862745037149688650719587196463907036416850100402002000070200100007192435114020110099100100003010010000010010916149488106612691091840121091611901213630261015611717934052810351144104810000501007202571985718717185771918
602047192553800040481217041136717257650071545255074540560101164010010000619429274772414968732071690719326391503641155010040200200007020010000717153511402011009910010000301001000001001092015546510649273893946151093212201260130261015611715594047211201082112110000501007194971788717497188271846
602047188853700044687517681132717348090071595255074540560101294010010000619159273842014968586071830718736386203643095010040200200007020010000719063511402011009910010000301001000001001089816849510634252892010422109261260129030261015711717984047210971076100810000501007180071802718047180871819
6020471895538000385797169618071747770007153225507304056010132401001000061893927442171496870007179971873640180364365501004020020000702001000071904351140201100991001000030100100000100108931424801066126978744815108831300119040261015711715384051611311085105210000501007195971763720147168971823

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1842

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e2022293a3e3f4043494d51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60029723955393001004267991712310871678816227159625507004051810147400101000062002127476700049687640716037189064133364458500104002020000700201000071717351140021109101000030010100001101088621584721065026599283619108941194125203252036411716344055210361079103810000500107189271960718427192071837
6002471907538100011451800174411487174581312715482550610405341012840010100426172942748803004968818071898718086413636411750010400202000070020100007229635114002110910100003001010000010109461143476106472761291970211093013031131132520164117169240440949952108310000500107179071982717297188971628
600247194453911010038481416961144718277912271743255065540554101274001010000619202274558400496874107182771902640443643115001040020200007002010000717763511400211091010000300101000001010917116746610654254789532181090611541292372520464217160640548992984100610000500107170571941719367178071879
6002471997538200200497822171221607170281322715602550560404941012640010100006191032756953004968730071842717916397736426850010400202000070020100007195835114002210910100003001010000010109305163489106642588904342210953137412323325201641171813405321047106799510000500107197971761719347182271929
60024718195382100004278161712210071657806227162025506454056210115400101000061935527472170049686130718347181464001364248500104002020000700201000071750351140021109101000030010100000101088121524971066529398853619108931354113203252016411717304051610041067101610000500107194971782718887178071700
600247184253821010039780217441100717268002371658255063540530101164001010000618716275417700496848007172671767639203641765001040020200007002010000718483511400211091010000300101000001010985113446710636273894810218109231163118105252016411715854053610651211106110000500107195171832719837184571772
60024716195372001004319061712214071834795237148725506304050210122400101000061988627505840049687170717947169463856364407500104002020000700201000071733351140021109101000030010100000101095011515171061428849918802510926132310910325201641271710405281018106295610000500107189671805718987179271921
60024717305392000004058241664110471694808227149525506854049810113400101000061923827452840149689230719877175364038364258500104002020100700201000071756351140021109101000030010100000101089811384911066125898968021109611144122209252026411716054050010341055103110000500107195371813716787192071833
60024716475392000003988251824110471813799227146025505854049810145400101000061914727387990049687710717237214164091364162500104002020000700201000071794351140021109101000030010100000101090001374901062628510922962710884117213000325201642171582405121049106491410000500107189571953719737182971898
60024718125370000004708341712010071742794227157925505854054610124400101000061783327441970049687330719497184764088364231500104002020000700201000071790351140021109101000030010100000101093211524771063426398548023109301143117109252016411716224050410581064110410000500107201571945717477182971975

Test 4: throughput

Count: 8

Code:

  ldpsw x0, x1, [x6, #8]!
  ldpsw x0, x1, [x7, #8]!
  ldpsw x0, x1, [x8, #8]!
  ldpsw x0, x1, [x9, #8]!
  ldpsw x0, x1, [x10, #8]!
  ldpsw x0, x1, [x11, #8]!
  ldpsw x0, x1, [x12, #8]!
  ldpsw x0, x1, [x13, #8]!
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3957

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0f1e1f2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6067696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
2402093200423821006432079417201131083169581733816961616158425160124801298000080100801344005966879960274928631316673169415494831649160100802001600008020080000316003811802011009928100800001008000001008093836403510585417629119514449208597272812450045019320105110116113171433800267076692800001601003155531512316773159931908
240204316132372000680108601720135136316287943341690211215832516012380116800008010080000400554698058023492867031603316451627373161816010080200160000802008000031686381180201100992910080000100800000100809865042548718488265116914704650851867561244672485849055110116113164340800166746882800001601003160331609315253155031690
24020431623237300063700823175211588318298083731628180215892516012780120800008010080000400581698736028492861331663317811646433166016010080200160000802008000031625381180201100992410080000100800000100809444838947708476266212888804093857697411404384502148035110116113189441800326967106800001601003176631638315853166931712
24020431831237301074800819169610710431745796347194117631699251601288013380000801008000040056470346801749285743145831636148784316181601008020016000080200800003168838118020110099291008000010080000010080934534145192846846238896744734857456991274750578949085110116113169827800227116466800001601003143231632318933167731792
240204316532363000668208281736121100315607753831783167115722516012680120800008010080000400555678926026492861831819316601506923155016010080200160000802008000031607381180201100993310080000100800000100809524943355098462962499151425270858677351174587471348105110116413183824800307227128800001601003165631607316903182331683
240204317882372000642908111712120168315138293561722180615092516012780128800008010080000400554659719031492867831712318331473463166316010080200160000802008000031693381180201100991810080000100800000100809943437151288565065914907745105857286951264812485732035110116113194736800267446744800001601003152331631316183163131647
240204316292382200724608261704128128315998093351670163816012516012680125800008010080000400578668324028492859931769318321526613161516010080200160000802008000031601381180201100992510080000100800000100809734940953998449563810898464739858187801225253530449045110116413181734800327036836800001601003159631598315873159531618
240204314812383000638008271704136116317148163441599162415832516013480120800008010080000400592691832030492868431705316981791443199116010080200160000802008000031648381180201100992510080000100800000100809543235954758485461715914684557863317401174499542733335110116143203231800306236931800001601003153731672315723151231809
240204315512373010633508531784121148316997903531828205717022516012580117800008010080000400558672868033492853331610317181592563161216010080200160000802008000031769381180201100992510080000100800000100809443741753928504669213918464968852667211184544484932035110116413163543800277217039800001601003174831658316333159931806
2402043168923730006750083817521281243162780635716601691162625160127801318000080100800004006206748300234928547316773189916581023179316010080200160000802008000031592381180201100993110080000100800000100809323241859508502068815930724475860378351275506495232035110116113186337800216707596800001601003171031882317953166531526

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3955

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0f181e2022293a3e3f404346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6067696a6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int load (95)inst int alu (97)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9ddfetch restart (de)e0e7? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
24002932102238200000647182516961351243163081334217701785155325160028800298000080010800004001516750290026492865031712317071518483166416001080020160000800208000031675381180021109291080000108000001080929163715083853556471294032459685419797113489549711613502000012150993148335800257166402800001600103161531635317643161231808
240024317052371000006561841172012211231731811363175317641507251600328004180000800108000040012367950400274928453315863164116551103149816001080020160000800208000031649381180021109241080000108000001080919839252138478662411910385183858808221304661516616065020000816081031788338002572972111800001600103166431551316083167931584
240024316392371000006692834172812710031725782369175518081603251600358003380000800108000040013068510100214928569317203169615207931609160010800201600008002080000315033811800211092810800001080000010808941637749028477864510860444829858817361254768518616095020000131501083157526800287336552800001600103140931750316383156431516
240024313642361000006324834170413310031534793335154116691420251600348003280000800108000040012968221501454928548314703162814657431527160010800201600008002080000316953811800211092910800001080000010809291637551568544862310901725125856808041294886551516035020000101508103151129800306446903800001600103161431535316763177231587
24002431670238101000695883117041241003150580835018411533160425160029800298000080010800004001186851970125492848031679315411416683141116001080020160000800208000031643381180021109221080000108000001080942313855737850676001190850476785779814125498851433233502000091501293180247800246756377800001600103165631719316843154131760
240024316322372000006626813171212112431580793346177218111688251600298002880000800108000040012468359801254928708317303169214558231421160010800201600008002080000316383811800211093010800001080000010809203337453718511666011915724947863387401334941572633375020000101608103149737800247127353800001600103171231683314933176431690
24002431559237200200625581217361311363159278036019281707158425160032800378000080010800004001606824470019492843431670317511581543174716001080020160000800208000031798381180021109261080000108000001080953333775415850256001192972489785966734135490151373203502201191601083165026800307906391800001600103168031434316403157631580
240024315732362000007188816153612396317287913622090158215532516003880036800008001080000400139666908012649285433161931752158510731756160010800201600008002080000317583811800211092910800001080000110809363235550418535264213929765510854867411305177524032005020000816091031618398002980264712800001600103172131720316013142631597
24002431527237200000638983816961341083159279532116921855157525160034800458000080010800004001426644971138492867331728318301450573165116001080020160000800208000031589381180021109191080000108000001080918243515357853006151290872541386073840132498950643303502000010160973168229800196746803800001600103164431510316643154831642
24002431674237300000687984017361241323169880335517481832153425160032800378000080010800004001126938170029492866331672317061494933170016001080020160000800208013831729381180021109291080000108000001080933483735741852516431493474542685475804133493653504906502000010160973163634800258017286800001600103155931642316053163831806