Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stp w0, w1, [x6, #8]!
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int store (96) | inst ldst (9b) | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1005 | 1040 | 7 | 0 | 0 | 0 | 0 | 0 | 17 | 21 | 1 | 0 | 15 | 0 | 1025 | 9 | 6 | 2 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50746 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1023 | 8 | 64 | 3 | 35 | 1014 | 1 | 0 | 29 | 8 | 15 | 1045 | 12 | 63 | 7 | 0 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 1 | 1 | 1 | 0 | 16 | 0 | 0 | 0 | 8 | 0 | 1025 | 11 | 12 | 0 | 8 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50746 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1025 | 7 | 53 | 3 | 26 | 1014 | 0 | 1 | 31 | 12 | 15 | 1034 | 12 | 70 | 7 | 0 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 0 | 1 | 1 | 0 | 15 | 18 | 2 | 0 | 5 | 0 | 1025 | 17 | 15 | 10 | 8 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1028 | 7 | 77 | 7 | 22 | 1012 | 1 | 1 | 28 | 12 | 18 | 1024 | 14 | 71 | 7 | 1 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 1 | 0 | 0 | 14 | 18 | 1 | 0 | 7 | 0 | 1025 | 16 | 15 | 10 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1047 | 31 | 69 | 0 | 1 | 1012 | 2 | 0 | 0 | 0 | 12 | 1005 | 12 | 71 | 7 | 2 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 1 | 6 | 20 | 21 | 2 | 0 | 12 | 12 | 1025 | 0 | 0 | 2 | 6 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1019 | 7 | 70 | 7 | 27 | 1013 | 0 | 0 | 21 | 18 | 20 | 1028 | 12 | 56 | 7 | 2 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 0 | 6 | 16 | 17 | 1 | 0 | 11 | 0 | 1025 | 16 | 1 | 15 | 5 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50730 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 8 | 61 | 7 | 21 | 1020 | 0 | 0 | 30 | 18 | 11 | 1023 | 12 | 71 | 0 | 1 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 0 | 0 | 0 | 0 | 0 | 14 | 14 | 1 | 0 | 8 | 0 | 1025 | 19 | 0 | 0 | 3 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50762 | 45824 | 0 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1008 | 8 | 68 | 6 | 10 | 1015 | 0 | 2 | 28 | 0 | 12 | 1005 | 12 | 47 | 7 | 2 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 1 | 1 | 0 | 15 | 14 | 2 | 0 | 9 | 0 | 1025 | 0 | 5 | 2 | 7 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50746 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1024 | 8 | 54 | 6 | 24 | 1016 | 1 | 1 | 25 | 12 | 13 | 1027 | 12 | 59 | 7 | 0 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 7 | 1 | 0 | 0 | 1 | 6 | 18 | 20 | 1 | 0 | 7 | 12 | 1025 | 0 | 1 | 0 | 8 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50738 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1033 | 8 | 61 | 6 | 23 | 1017 | 0 | 0 | 22 | 6 | 15 | 1019 | 13 | 63 | 7 | 1 | 73 | 3 | 17 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
| 1004 | 1040 | 8 | 1 | 1 | 0 | 1 | 6 | 18 | 17 | 1 | 0 | 7 | 0 | 1025 | 22 | 0 | 5 | 10 | 25 | 2000 | 1000 | 1000 | 1000 | 1000 | 50754 | 45824 | 1 | 1040 | 1040 | 824 | 3 | 898 | 2000 | 1000 | 3000 | 1040 | 124 | 1 | 1 | 1001 | 1000 | 1000 | 1007 | 8 | 68 | 5 | 1 | 1020 | 1 | 1 | 32 | 0 | 12 | 1022 | 12 | 79 | 7 | 2 | 73 | 3 | 16 | 3 | 3 | 1037 | 1000 | 1000 | 1000 | 1041 | 1041 | 1041 | 1041 | 1041 |
Code:
stp w0, w1, [x6, #8]!
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10209 | 10040 | 75 | 0 | 2298 | 88 | 811 | 1 | 704 | 86 | 0 | 172 | 10025 | 813 | 69 | 106 | 59 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 522055 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8681 | 7 | 8743 | 20106 | 200 | 10008 | 200 | 30024 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10924 | 1422 | 399 | 0 | 692 | 10240 | 302 | 0 | 909 | 40 | 829 | 10941 | 11 | 1233 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 10037 | 10000 | 0 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2064 | 81 | 827 | 1 | 784 | 92 | 0 | 120 | 10025 | 804 | 82 | 73 | 56 | 25 | 20100 | 10100 | 10000 | 10106 | 10000 | 522133 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8681 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10908 | 1325 | 380 | 0 | 644 | 10237 | 298 | 0 | 932 | 34 | 857 | 10899 | 15 | 1143 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 1 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2130 | 88 | 840 | 1 | 728 | 81 | 0 | 96 | 10025 | 798 | 81 | 95 | 72 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522059 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10904 | 1412 | 419 | 6 | 679 | 10250 | 270 | 0 | 905 | 40 | 936 | 10929 | 8 | 1062 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 1 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2148 | 87 | 847 | 1 | 776 | 70 | 0 | 120 | 10025 | 805 | 100 | 105 | 60 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522079 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10902 | 1378 | 440 | 0 | 671 | 10241 | 293 | 0 | 932 | 62 | 829 | 10923 | 11 | 1166 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 3 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2223 | 70 | 845 | 1 | 712 | 74 | 0 | 164 | 10025 | 771 | 71 | 63 | 84 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522165 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10922 | 1359 | 379 | 0 | 683 | 10250 | 257 | 0 | 901 | 34 | 839 | 10882 | 13 | 1124 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2250 | 77 | 811 | 1 | 696 | 96 | 0 | 152 | 10025 | 760 | 93 | 81 | 55 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522079 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10156 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10910 | 1140 | 363 | 0 | 684 | 10244 | 266 | 0 | 919 | 32 | 854 | 10947 | 11 | 1159 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2271 | 66 | 831 | 1 | 720 | 77 | 0 | 160 | 10025 | 814 | 69 | 76 | 55 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522029 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10924 | 1361 | 372 | 2 | 661 | 10257 | 287 | 0 | 905 | 34 | 884 | 10950 | 10 | 1256 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2247 | 74 | 806 | 1 | 744 | 63 | 0 | 120 | 10025 | 800 | 104 | 70 | 52 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522027 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10888 | 1206 | 379 | 0 | 685 | 10245 | 295 | 0 | 881 | 40 | 788 | 10914 | 10 | 1203 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2199 | 93 | 823 | 1 | 768 | 80 | 0 | 96 | 10025 | 809 | 80 | 104 | 56 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522117 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10942 | 1311 | 441 | 11 | 693 | 10256 | 296 | 0 | 920 | 34 | 909 | 10943 | 17 | 1108 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 1 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10204 | 10040 | 75 | 0 | 2403 | 89 | 840 | 1 | 728 | 89 | 0 | 120 | 10025 | 783 | 74 | 102 | 56 | 25 | 20100 | 10100 | 10000 | 10100 | 10000 | 522121 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8674 | 3 | 8747 | 20100 | 200 | 10000 | 200 | 30000 | 10040 | 122 | 1 | 1 | 10201 | 100 | 99 | 100 | 10000 | 100 | 10000 | 100 | 10936 | 1227 | 375 | 0 | 687 | 10247 | 279 | 0 | 917 | 40 | 951 | 10937 | 10 | 1245 | 0 | 0 | 0 | 710 | 1 | 17 | 1 | 1 | 10037 | 10000 | 0 | 0 | 10000 | 10100 | 10041 | 10041 | 10041 | 10041 | 10041 |
Result (median cycles for code): 1.0040
| retire uop (01) | cycle (02) | 03 | 18 | 19 | 1e | 1f | 20 | 22 | 29 | 3a | 3c | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d cache miss st (a2) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10029 | 10040 | 75 | 1 | 1 | 2190 | 74 | 809 | 1 | 744 | 71 | 1 | 152 | 10025 | 801 | 102 | 116 | 98 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 518889 | 468824 | 1 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10922 | 1303 | 408 | 693 | 10223 | 308 | 0 | 942 | 38 | 800 | 10926 | 14 | 1178 | 0 | 640 | 6 | 16 | 3 | 3 | 10037 | 10000 | 7 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2331 | 90 | 840 | 1 | 768 | 81 | 0 | 96 | 10025 | 804 | 103 | 104 | 63 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521097 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10922 | 1181 | 410 | 689 | 10244 | 282 | 0 | 912 | 42 | 860 | 10911 | 13 | 1114 | 0 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 2 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 76 | 0 | 0 | 2265 | 69 | 807 | 1 | 688 | 86 | 0 | 152 | 10025 | 809 | 88 | 92 | 56 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521081 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10898 | 1295 | 400 | 688 | 10232 | 290 | 0 | 914 | 36 | 840 | 10927 | 10 | 1077 | 0 | 640 | 2 | 16 | 2 | 2 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2010 | 76 | 804 | 1 | 752 | 84 | 0 | 148 | 10025 | 809 | 94 | 106 | 57 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521113 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10914 | 1286 | 378 | 683 | 10216 | 284 | 0 | 936 | 36 | 863 | 10946 | 10 | 1033 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2337 | 90 | 815 | 1 | 776 | 76 | 0 | 156 | 10025 | 802 | 111 | 99 | 53 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521113 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10930 | 1218 | 378 | 684 | 10252 | 298 | 0 | 868 | 32 | 876 | 10917 | 12 | 1043 | 0 | 640 | 3 | 16 | 2 | 2 | 10037 | 10000 | 0 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2187 | 85 | 842 | 1 | 720 | 82 | 1 | 120 | 10025 | 799 | 108 | 96 | 55 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521105 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10882 | 1336 | 395 | 667 | 10240 | 305 | 0 | 914 | 40 | 857 | 10917 | 11 | 1194 | 0 | 640 | 3 | 16 | 3 | 3 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2220 | 79 | 832 | 1 | 728 | 81 | 0 | 92 | 10025 | 807 | 101 | 106 | 53 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521097 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10894 | 1239 | 388 | 680 | 10235 | 260 | 0 | 922 | 42 | 893 | 10911 | 14 | 1136 | 0 | 640 | 3 | 16 | 3 | 2 | 10037 | 10000 | 1 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2310 | 74 | 834 | 1 | 752 | 94 | 0 | 116 | 10025 | 811 | 110 | 110 | 60 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521113 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 11 | 8770 | 20010 | 20 | 10000 | 20 | 30240 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10890 | 1337 | 367 | 710 | 10246 | 305 | 0 | 902 | 46 | 815 | 10890 | 14 | 1068 | 0 | 640 | 3 | 16 | 2 | 3 | 10037 | 10000 | 6 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2094 | 92 | 842 | 1 | 752 | 76 | 6 | 160 | 10025 | 821 | 100 | 82 | 48 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521113 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10932 | 1350 | 389 | 700 | 10238 | 281 | 0 | 948 | 42 | 947 | 10934 | 16 | 1199 | 0 | 640 | 2 | 16 | 3 | 3 | 10037 | 10000 | 3 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
| 10024 | 10040 | 75 | 0 | 0 | 2184 | 81 | 830 | 1 | 704 | 73 | 1 | 160 | 10025 | 765 | 122 | 110 | 61 | 25 | 20010 | 10010 | 10000 | 10010 | 10000 | 521097 | 468824 | 0 | 49 | 6960 | 10040 | 10040 | 8696 | 3 | 8770 | 20010 | 20 | 10000 | 20 | 30000 | 10040 | 124 | 1 | 1 | 10021 | 10 | 9 | 10 | 10000 | 10 | 10000 | 10 | 10886 | 1197 | 363 | 698 | 10243 | 281 | 0 | 934 | 36 | 858 | 10952 | 14 | 1225 | 3 | 640 | 3 | 16 | 2 | 3 | 10037 | 10000 | 0 | 0 | 10000 | 10010 | 10041 | 10041 | 10041 | 10041 | 10041 |
Count: 8
Code:
stp w0, w1, [x6, #8]! stp w0, w1, [x7, #8]! stp w0, w1, [x8, #8]! stp w0, w1, [x9, #8]! stp w0, w1, [x10, #8]! stp w0, w1, [x11, #8]! stp w0, w1, [x12, #8]! stp w0, w1, [x13, #8]!
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.5103
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | c3 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80209 | 40560 | 304 | 1 | 1 | 0 | 0 | 0 | 1833 | 350 | 831 | 1 | 728 | 102 | 148 | 40520 | 820 | 2002 | 2237 | 128 | 25 | 160717 | 80938 | 80014 | 80100 | 80000 | 402144 | 1859584 | 1 | 353 | 49 | 37432 | 40361 | 40466 | 30430 | 3 | 30383 | 160100 | 200 | 80000 | 200 | 240000 | 40363 | 76 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80945 | 0 | 5016 | 531 | 6 | 875 | 80297 | 273 | 0 | 915 | 70 | 1146 | 81199 | 292 | 5007 | 14 | 0 | 0 | 5110 | 12 | 16 | 13 | 11 | 40449 | 80242 | 80000 | 80100 | 40486 | 40469 | 40448 | 40396 | 40438 |
| 80204 | 40409 | 303 | 1 | 0 | 1 | 0 | 1 | 1752 | 393 | 850 | 1 | 664 | 132 | 140 | 40486 | 891 | 2010 | 2194 | 138 | 25 | 160581 | 80489 | 80000 | 80100 | 80000 | 412104 | 1861072 | 0 | 47 | 49 | 37504 | 40454 | 40391 | 30322 | 3 | 30442 | 160100 | 200 | 80000 | 200 | 240000 | 40370 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80933 | 12 | 4907 | 484 | 7 | 888 | 80259 | 278 | 1 | 927 | 74 | 1250 | 81157 | 259 | 4535 | 13 | 2 | 0 | 5110 | 13 | 18 | 10 | 14 | 40462 | 80710 | 80000 | 80100 | 40433 | 40460 | 40402 | 40415 | 40477 |
| 80204 | 40472 | 303 | 0 | 0 | 0 | 0 | 0 | 1860 | 306 | 830 | 1 | 792 | 102 | 112 | 40502 | 794 | 2170 | 2016 | 114 | 25 | 160482 | 85977 | 80000 | 80100 | 80000 | 401327 | 1862008 | 0 | 250 | 49 | 37298 | 40413 | 40447 | 30347 | 3 | 30401 | 160100 | 200 | 80000 | 200 | 240000 | 40374 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80905 | 0 | 4919 | 471 | 9 | 939 | 80274 | 288 | 0 | 929 | 84 | 1245 | 81202 | 275 | 4754 | 0 | 0 | 0 | 5110 | 11 | 16 | 14 | 13 | 40365 | 82171 | 80000 | 80100 | 40411 | 40439 | 40413 | 40445 | 40477 |
| 80204 | 40477 | 303 | 1 | 0 | 0 | 0 | 0 | 1989 | 380 | 821 | 1 | 744 | 112 | 148 | 40611 | 803 | 2064 | 2045 | 137 | 25 | 164239 | 80369 | 80000 | 80100 | 80000 | 409727 | 1858600 | 1 | 1016 | 49 | 37406 | 40441 | 40458 | 30393 | 3 | 30444 | 160100 | 200 | 80000 | 200 | 240000 | 40431 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80950 | 13 | 4930 | 486 | 6 | 912 | 80288 | 270 | 1 | 915 | 52 | 1150 | 81211 | 296 | 4821 | 13 | 1 | 0 | 5110 | 15 | 18 | 12 | 11 | 40429 | 83289 | 80000 | 80100 | 40765 | 40835 | 40857 | 40940 | 40863 |
| 80204 | 40944 | 307 | 1 | 0 | 1 | 0 | 0 | 1683 | 909 | 815 | 1 | 680 | 136 | 152 | 40780 | 808 | 1925 | 1800 | 210 | 25 | 160821 | 80989 | 80026 | 80100 | 80000 | 415202 | 1873768 | 1 | 1839 | 49 | 37740 | 40891 | 40817 | 30732 | 3 | 30744 | 160100 | 200 | 80000 | 200 | 240000 | 40964 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80893 | 0 | 4412 | 464 | 6 | 895 | 80587 | 251 | 0 | 937 | 98 | 1546 | 81352 | 573 | 4370 | 0 | 0 | 0 | 5110 | 12 | 16 | 13 | 13 | 40821 | 81454 | 80000 | 80100 | 40823 | 40781 | 40816 | 40777 | 40681 |
| 80204 | 40882 | 306 | 0 | 0 | 0 | 0 | 0 | 1857 | 845 | 793 | 1 | 752 | 137 | 104 | 40931 | 795 | 2026 | 1849 | 174 | 25 | 160806 | 81104 | 80000 | 80100 | 80000 | 402915 | 1874152 | 0 | 1676 | 49 | 37764 | 40747 | 40936 | 30696 | 3 | 30760 | 160100 | 200 | 80000 | 200 | 240000 | 40851 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80919 | 0 | 4532 | 503 | 6 | 878 | 80536 | 274 | 0 | 917 | 40 | 1575 | 81452 | 488 | 4575 | 0 | 0 | 0 | 5110 | 12 | 17 | 13 | 12 | 40844 | 84622 | 80000 | 80100 | 40880 | 40770 | 40817 | 40841 | 40821 |
| 80204 | 40821 | 305 | 0 | 0 | 0 | 0 | 0 | 1887 | 737 | 802 | 1 | 728 | 134 | 104 | 40783 | 801 | 1904 | 1981 | 157 | 25 | 160502 | 81108 | 80000 | 80100 | 80000 | 402963 | 1879672 | 1 | 334 | 49 | 37740 | 40812 | 40863 | 30746 | 3 | 30820 | 160100 | 200 | 80000 | 200 | 240000 | 40886 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80889 | 0 | 4195 | 452 | 9 | 867 | 80453 | 256 | 0 | 893 | 36 | 1503 | 81506 | 485 | 4091 | 0 | 0 | 0 | 5110 | 10 | 16 | 14 | 14 | 40912 | 80616 | 80000 | 80100 | 40841 | 40807 | 40953 | 40849 | 41038 |
| 80204 | 40754 | 305 | 0 | 0 | 0 | 1 | 0 | 1755 | 757 | 821 | 1 | 680 | 122 | 184 | 40801 | 790 | 1786 | 1969 | 146 | 25 | 160744 | 81227 | 80007 | 80100 | 80000 | 403363 | 1872143 | 1 | 2441 | 49 | 37925 | 40833 | 40922 | 30745 | 3 | 30864 | 160100 | 200 | 80000 | 200 | 240000 | 40869 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80897 | 0 | 4268 | 492 | 10 | 930 | 80497 | 242 | 0 | 937 | 36 | 1683 | 81398 | 521 | 4435 | 0 | 0 | 0 | 5110 | 12 | 17 | 13 | 11 | 40890 | 80221 | 80000 | 80100 | 40892 | 40751 | 40889 | 40834 | 40759 |
| 80204 | 40773 | 305 | 0 | 0 | 0 | 0 | 0 | 1653 | 878 | 783 | 1 | 696 | 130 | 144 | 40741 | 803 | 1707 | 1810 | 169 | 25 | 160735 | 80594 | 80000 | 80100 | 80000 | 401925 | 1872256 | 1 | 414 | 49 | 37792 | 40751 | 40888 | 30812 | 3 | 30807 | 160100 | 200 | 80000 | 200 | 240000 | 40788 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80915 | 0 | 4568 | 484 | 13 | 954 | 80571 | 250 | 0 | 863 | 84 | 1626 | 81434 | 474 | 4458 | 12 | 0 | 0 | 5110 | 14 | 17 | 12 | 14 | 40733 | 80623 | 80000 | 80100 | 40815 | 40997 | 40881 | 40907 | 40859 |
| 80204 | 40812 | 323 | 1 | 0 | 0 | 0 | 1 | 1788 | 868 | 835 | 1 | 664 | 107 | 100 | 40759 | 796 | 2007 | 1760 | 170 | 25 | 164809 | 80701 | 80000 | 80100 | 80000 | 419900 | 1873960 | 1 | 2491 | 49 | 37665 | 40824 | 40996 | 30690 | 3 | 30763 | 160100 | 200 | 80000 | 200 | 240000 | 40778 | 75 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 100 | 80929 | 15 | 4516 | 481 | 5 | 879 | 80578 | 276 | 0 | 905 | 26 | 1679 | 81402 | 528 | 4693 | 14 | 0 | 0 | 5110 | 13 | 16 | 12 | 10 | 40903 | 80856 | 80000 | 80100 | 40851 | 40850 | 40926 | 40869 | 40893 |
Result (median cycles for code divided by count): 0.5103
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 1e | 1f | 20 | 22 | 29 | 3a | 3e | 3f | 40 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5f | 60 | 67 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int store (96) | inst int alu (97) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss st (a2) | l1d cache miss ld (a3) | a4 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | aa | ab | ac | af | bc | l1d cache miss st nonspec (c0) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d5 | map dispatch bubble (d6) | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80029 | 40725 | 306 | 2 | 0 | 0 | 1983 | 711 | 782 | 1 | 720 | 106 | 100 | 40855 | 796 | 1510 | 1772 | 181 | 25 | 162684 | 82478 | 80166 | 80010 | 80000 | 401641 | 1881164 | 0 | 1 | 74 | 49 | 37817 | 40839 | 40821 | 30778 | 3 | 30862 | 160010 | 20 | 80000 | 20 | 240000 | 40899 | 88 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80827 | 27 | 4601 | 503 | 5 | 897 | 80493 | 297 | 2 | 940 | 32 | 1751 | 81411 | 588 | 4006 | 27 | 0 | 5020 | 0 | 3 | 17 | 0 | 4 | 7 | 40881 | 80782 | 80000 | 80010 | 40841 | 40814 | 40782 | 40885 | 40852 |
| 80024 | 40868 | 305 | 2 | 0 | 2 | 1836 | 811 | 781 | 1 | 672 | 115 | 128 | 40840 | 792 | 1639 | 1957 | 135 | 46 | 160664 | 80595 | 80023 | 80010 | 80108 | 402379 | 1876844 | 0 | 1 | 357 | 49 | 38184 | 40864 | 40907 | 30820 | 3 | 30773 | 160010 | 20 | 80000 | 20 | 240360 | 40888 | 88 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 81028 | 25 | 4322 | 512 | 10 | 869 | 80594 | 260 | 0 | 898 | 40 | 1650 | 81472 | 542 | 4279 | 21 | 2 | 5020 | 0 | 7 | 17 | 0 | 5 | 6 | 40697 | 87974 | 80000 | 80010 | 40801 | 40818 | 40855 | 40778 | 40758 |
| 80024 | 40869 | 305 | 2 | 0 | 0 | 1932 | 831 | 806 | 1 | 704 | 123 | 132 | 40846 | 781 | 1665 | 2061 | 169 | 25 | 168370 | 80583 | 80000 | 80010 | 80000 | 402059 | 1881164 | 0 | 1 | 2199 | 49 | 37766 | 40781 | 40800 | 30729 | 3 | 30824 | 160010 | 20 | 80000 | 20 | 240000 | 40807 | 87 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80931 | 21 | 5105 | 504 | 5 | 853 | 80534 | 298 | 0 | 894 | 46 | 1627 | 81354 | 584 | 4045 | 27 | 0 | 5020 | 0 | 2 | 17 | 1 | 7 | 9 | 40828 | 80636 | 80000 | 80010 | 40734 | 40808 | 40857 | 40900 | 40843 |
| 80024 | 41004 | 307 | 2 | 2 | 0 | 1632 | 889 | 796 | 1 | 720 | 114 | 100 | 40906 | 816 | 1786 | 1804 | 192 | 25 | 160403 | 80265 | 80000 | 80010 | 80000 | 406969 | 1880324 | 0 | 0 | 352 | 49 | 37695 | 40838 | 40813 | 30812 | 3 | 30920 | 160010 | 20 | 80000 | 20 | 240000 | 40836 | 87 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80896 | 29 | 4494 | 494 | 1 | 861 | 80564 | 272 | 0 | 857 | 44 | 1648 | 81415 | 575 | 4034 | 27 | 0 | 5020 | 0 | 5 | 18 | 0 | 3 | 5 | 40847 | 87188 | 80000 | 80010 | 40870 | 40851 | 40770 | 40856 | 40828 |
| 80024 | 40941 | 306 | 2 | 0 | 0 | 1833 | 837 | 765 | 1 | 720 | 116 | 100 | 40764 | 758 | 1881 | 1849 | 168 | 25 | 160438 | 80520 | 80000 | 80010 | 80000 | 405122 | 1877972 | 0 | 0 | 141 | 49 | 37688 | 40749 | 40822 | 30732 | 3 | 30866 | 160010 | 20 | 80000 | 20 | 240000 | 40785 | 88 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80938 | 27 | 4591 | 513 | 1 | 874 | 80509 | 281 | 0 | 906 | 28 | 1616 | 81345 | 487 | 4416 | 28 | 4 | 5020 | 0 | 5 | 17 | 0 | 5 | 6 | 40790 | 80387 | 80000 | 80010 | 40808 | 40855 | 40747 | 40881 | 40899 |
| 80024 | 40809 | 305 | 2 | 0 | 0 | 1692 | 947 | 848 | 1 | 640 | 114 | 100 | 40782 | 774 | 1527 | 1714 | 200 | 25 | 160215 | 82322 | 80000 | 80010 | 80000 | 400585 | 1875860 | 0 | 0 | 3337 | 49 | 37744 | 40848 | 40928 | 30668 | 3 | 30899 | 160010 | 20 | 80000 | 20 | 240000 | 40924 | 88 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80915 | 27 | 4745 | 427 | 4 | 898 | 80582 | 260 | 2 | 868 | 110 | 1689 | 81450 | 552 | 4838 | 27 | 0 | 5020 | 0 | 7 | 17 | 0 | 7 | 5 | 40869 | 80618 | 80000 | 80010 | 40941 | 40815 | 40846 | 40936 | 40757 |
| 80024 | 40885 | 307 | 2 | 0 | 0 | 1950 | 796 | 819 | 1 | 664 | 86 | 200 | 40863 | 822 | 1557 | 1644 | 192 | 25 | 160371 | 82438 | 80167 | 80010 | 80000 | 401830 | 1874468 | 0 | 0 | 337 | 49 | 38276 | 40899 | 40843 | 30760 | 3 | 30774 | 160010 | 20 | 80000 | 20 | 240000 | 40917 | 88 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80944 | 27 | 4145 | 430 | 5 | 872 | 80471 | 251 | 4 | 893 | 32 | 1789 | 81432 | 630 | 4039 | 22 | 0 | 5020 | 0 | 3 | 16 | 0 | 5 | 3 | 40794 | 80470 | 80000 | 80010 | 40889 | 40890 | 40708 | 40901 | 40816 |
| 80024 | 40787 | 306 | 2 | 0 | 0 | 1797 | 892 | 845 | 1 | 696 | 93 | 100 | 40704 | 765 | 1586 | 1697 | 156 | 25 | 160650 | 81534 | 80000 | 80010 | 80000 | 406695 | 1878621 | 1 | 1 | 175 | 49 | 37776 | 40719 | 40753 | 30767 | 3 | 30805 | 160010 | 20 | 80000 | 20 | 240000 | 40920 | 96 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80952 | 27 | 4128 | 475 | 16 | 998 | 80548 | 288 | 0 | 867 | 44 | 1676 | 81384 | 555 | 4584 | 28 | 0 | 5020 | 0 | 4 | 17 | 0 | 5 | 7 | 40777 | 80541 | 80000 | 80010 | 40878 | 40812 | 40880 | 40865 | 40727 |
| 80024 | 40757 | 306 | 2 | 2 | 0 | 1749 | 875 | 831 | 1 | 528 | 118 | 96 | 40804 | 762 | 1678 | 1884 | 138 | 25 | 160430 | 80630 | 80000 | 80010 | 80000 | 402137 | 1879508 | 0 | 0 | 369 | 49 | 37835 | 40844 | 40902 | 30710 | 3 | 30837 | 160010 | 20 | 80000 | 20 | 240000 | 40910 | 84 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80926 | 28 | 4805 | 478 | 5 | 906 | 80519 | 292 | 0 | 890 | 34 | 1738 | 81413 | 492 | 4461 | 27 | 2 | 5020 | 0 | 4 | 16 | 0 | 6 | 4 | 40906 | 80456 | 80000 | 80010 | 40907 | 40775 | 40924 | 40799 | 40862 |
| 80024 | 40763 | 305 | 2 | 2 | 2 | 1845 | 799 | 811 | 1 | 656 | 96 | 136 | 40739 | 748 | 1741 | 1707 | 173 | 25 | 160546 | 87382 | 80029 | 80010 | 80000 | 401008 | 1880423 | 0 | 1 | 975 | 49 | 37743 | 40761 | 40912 | 30836 | 3 | 30835 | 160010 | 20 | 80000 | 20 | 240000 | 40808 | 88 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 10 | 80940 | 24 | 3784 | 479 | 6 | 883 | 80551 | 264 | 0 | 850 | 46 | 1778 | 81470 | 484 | 4052 | 28 | 0 | 5020 | 0 | 7 | 16 | 0 | 5 | 5 | 40807 | 80503 | 80000 | 80010 | 40804 | 40850 | 40913 | 40849 | 40770 |