Firestorm: STRH (post-index) measurements

Code:

  strh w0, [x6], #8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	20	22	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
1005	1040	8	1	1	1	1	6	15	16	0	4	0	1025	8	3	6	8	25	2000	1000	1000	1000	1000	50738	45824	0	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1035	7	61	0	18	1015	1	2	17	8	15	1024	12	56	7	2	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	0	6	15	17	1	1	12	1025	19	3	4	9	25	2000	1000	1000	1000	1000	50730	45824	0	1040	1040	824	3	897	2000	1000	2000	1040	124	1	1	1001	1000	1000	1029	13	50	0	13	1012	1	0	0	0	15	1005	13	48	7	1	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	1	6	15	13	1	8	0	1025	9	0	3	6	25	2000	1000	1000	1000	1000	50738	45824	1	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1021	7	74	1	21	1017	1	1	28	0	17	1034	17	48	7	0	73	1	17	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	7	1	1	1	2	6	15	23	1	5	0	1025	10	3	3	7	25	2000	1000	1000	1000	1000	50746	45824	0	1040	1040	824	3	897	2000	1000	2000	1040	124	1	1	1001	1000	1000	1025	8	85	3	0	1012	1	0	0	0	15	1005	12	40	7	0	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	2	2	0	12	19	12	0	5	4	1025	18	4	4	9	25	2000	1000	1000	1000	1000	50730	45824	0	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1025	7	61	5	20	1012	1	0	10	0	18	1021	13	64	7	1	73	1	17	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	0	1	6	20	0	0	13	0	1025	14	2	4	7	25	2000	1000	1000	1000	1000	50730	45824	0	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1007	7	61	0	16	1013	1	2	0	0	15	1005	12	64	7	2	73	1	17	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	1	0	0	20	0	0	1	4	1025	0	4	3	8	25	2000	1000	1000	1000	1000	50722	45824	1	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1029	9	46	2	13	1013	1	0	28	6	20	1031	17	56	7	1	73	1	17	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	1	0	1	6	15	20	0	1	0	1025	0	0	0	6	25	2000	1000	1000	1000	1000	50738	45824	0	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1022	8	38	6	26	1013	2	2	17	14	15	1027	12	88	7	1	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	1	0	6	15	36	1	5	4	1025	0	2	4	8	25	2000	1000	1000	1000	1000	50722	45824	0	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1025	7	70	5	15	1012	1	0	15	6	24	1022	12	48	7	1	73	1	16	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041
1004	1040	8	1	0	0	0	6	14	8	1	7	4	1025	10	5	15	6	25	2000	1000	1000	1000	1000	50738	45824	0	1040	1040	824	3	898	2000	1000	2000	1040	124	1	1	1001	1000	1000	1019	8	53	3	10	1022	0	2	20	12	15	1020	12	96	7	1	73	1	17	1	1	1037	1000	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 2->2

Code:

  strh w0, [x6], #8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10209	10040	75	2166	99	845	1	728	80	5	116	10025	777	104	95	44	25	20100	10100	10000	10100	10000	522203	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10900	1348	377	8	660	10247	293	930	34	819	10880	15	1011	710	2	17	2	2	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2376	93	815	1	760	76	3	112	10025	845	104	95	24	25	20100	10100	10000	10100	10000	521895	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10930	1396	353	8	652	10253	293	888	40	915	10905	17	1203	710	2	17	2	2	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2277	97	834	1	712	71	11	152	10025	758	67	65	47	25	20100	10100	10000	10100	10000	522101	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10922	1260	375	0	669	10257	289	896	42	791	10892	13	1175	710	2	17	2	2	10037	10000	2	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2307	95	809	1	768	84	5	96	10025	764	117	95	43	25	20100	10100	10000	10100	10000	522155	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10894	1426	355	0	656	10252	281	908	34	854	10909	10	1312	710	2	17	2	2	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2226	77	863	1	736	86	5	148	10025	816	114	53	23	25	20100	10100	10019	10100	10000	522195	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10926	1458	357	0	674	10267	281	922	32	824	10949	21	1115	710	2	17	2	2	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2172	91	862	1	784	86	10	92	10025	780	74	98	26	25	20100	10100	10000	10100	10000	522203	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10888	1285	375	6	707	10270	302	900	38	910	10924	15	1236	710	2	17	2	2	10037	10000	1	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2289	91	855	1	752	77	0	108	10025	818	129	103	28	25	20100	10100	10000	10100	10000	522157	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10938	1398	360	0	658	10253	290	920	34	820	10931	12	1149	710	2	17	2	2	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	76	2106	93	815	1	760	76	5	148	10025	792	75	105	26	25	20100	10100	10000	10100	10000	522163	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10910	1410	384	0	684	10260	242	900	44	821	10980	12	1156	710	2	17	2	2	10037	10000	0	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2295	83	851	1	744	71	0	116	10025	760	71	92	17	25	20100	10100	10000	10100	10000	522147	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10912	1365	365	0	655	10267	278	888	50	868	10984	13	1168	710	2	17	2	2	10037	10000	4	10000	10100	10041	10041	10041	10041	10041
10204	10040	75	2220	89	820	1	776	85	11	152	10025	787	68	55	31	25	20100	10100	10000	10100	10000	522171	468824	49	6960	10040	10040	8674	3	8747	20100	200	10000	200	20000	10040	122	1	1	10201	100	99	100	10000	100	10000	100	10900	1216	333	0	635	10280	300	956	44	868	10973	17	1188	710	2	17	2	2	10037	10000	0	10000	10100	10041	10041	10041	10041	10041

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0040

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	20	22	29	3a	3c	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10029	10040	75	2445	87	852	1	768	56	0	120	10025	805	127	93	26	25	20010	10010	10000	10010	10000	521113	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10914	1343	415	0	635	10264	309	934	36	850	10882	10	1295	671	4	16	3	3	10037	10000	1	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2316	82	817	1	752	70	0	152	10025	766	110	83	47	25	20010	10010	10000	10010	10000	521121	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10896	1350	376	0	654	10262	296	868	42	899	10927	21	1328	640	3	16	3	3	10037	10000	3	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2331	74	807	1	712	71	0	124	10025	739	73	81	28	25	20010	10010	10000	10010	10000	521137	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10950	1329	401	0	673	10261	301	890	38	926	10914	22	1233	640	2	16	2	2	10037	10000	1	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2292	79	835	1	720	71	0	124	10025	766	94	98	28	25	20010	10010	10000	10010	10000	521137	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10858	1351	346	0	659	10249	314	866	36	861	10916	15	1165	640	3	16	3	2	10037	10000	5	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2304	81	810	1	696	76	0	120	10025	775	129	80	27	25	20010	10010	10000	10010	10000	521131	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10884	1348	414	0	679	10282	260	906	40	916	10890	19	1226	640	2	16	2	2	10037	10000	2	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2448	97	789	1	704	56	0	152	10025	795	90	75	25	25	20010	10010	10000	10010	10000	521065	468824	0	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10912	1306	444	0	650	10244	303	926	52	919	10920	15	1341	640	3	16	3	3	10077	10000	2	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2313	95	803	1	792	68	0	124	10025	792	86	86	22	25	20010	10010	10000	10010	10000	521131	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10910	1298	370	0	633	10247	304	890	36	878	10889	13	1240	640	2	16	2	3	10037	10000	0	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2466	89	811	1	728	61	0	104	10025	753	110	93	36	25	20010	10010	10000	10010	10000	521137	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10886	1275	384	2	661	10259	296	922	36	863	10898	18	1316	640	2	16	3	3	10037	10000	0	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	75	2439	96	824	1	712	71	0	104	10025	816	91	75	19	25	20010	10010	10000	10010	10000	521099	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10854	1574	417	0	643	10246	289	902	50	920	10846	13	1161	640	3	16	2	2	10037	10021	0	0	10000	10010	10041	10041	10041	10041	10041
10024	10040	76	2205	101	836	1	752	65	0	168	10025	803	116	73	27	25	20010	10010	10000	10010	10000	521121	468824	1	49	6960	10040	10040	8696	3	8770	20010	20	10000	20	20000	10040	124	1	1	10021	10	9	10	10000	10	10000	10	10930	1336	408	0	635	10259	310	918	38	899	10921	30	1213	640	3	16	3	3	10037	10000	1	0	10000	10010	10041	10041	10041	10041	10041

Test 3: throughput

Count: 8

Code:

  strh w0, [x6], #8
  strh w0, [x7], #8
  strh w0, [x8], #8
  strh w0, [x9], #8
  strh w0, [x10], #8
  strh w0, [x11], #8
  strh w0, [x12], #8
  strh w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5097

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80209	40792	306	3	0	0	0	0	1881	771	831	1	696	101	132	40846	735	1695	1831	161	25	163324	80709	80014	80100	80000	416486	1874012	0	707	49	37750	0	40854	40807	30681	3	30672	160100	200	80000	200	160000	40797	87	1	1	80201	100	99	100	80000	100	80000	100	80919	42	4391	565	12	843	80509	287	0	885	42	1651	81382	504	4155	34	0	5110	1	17	1	1	40765	80922	80000	80100	40720	40854	40818	40712	40803
80204	40801	305	3	0	0	0	0	1803	759	802	1	728	115	104	40825	776	1664	1813	167	25	160563	80830	80000	80100	80000	402618	1878692	0	1047	49	37687	0	40847	40710	30585	3	30877	160100	200	80000	200	160000	40830	87	1	1	80201	100	99	100	80000	100	80000	100	80929	29	3940	510	8	868	80525	293	0	894	122	1630	81441	551	4426	27	0	5110	1	16	1	1	40769	80258	80000	80100	40795	40818	40740	40768	40732
80204	40805	305	2	2	0	0	0	1704	775	745	1	696	106	136	40846	760	1744	1830	162	25	160841	80745	80008	80100	80000	401943	1870712	0	1281	49	37718	0	40746	40871	30754	3	30704	160100	200	80000	200	160000	40789	87	1	1	80201	100	99	100	80000	100	80000	100	80901	23	4045	480	2	902	80556	286	0	852	94	1782	81426	539	4831	28	0	5110	1	17	1	1	40807	80458	80000	80100	40731	40851	40931	40832	40716
80204	40760	305	2	0	0	0	0	1740	892	761	1	592	98	96	40760	785	1775	1700	190	25	160701	82725	80000	80100	80000	402685	1877564	0	519	49	37648	0	40782	40795	30677	3	30752	160100	200	80000	200	160000	40656	76	1	1	80201	100	99	100	80000	100	80000	100	80890	13	4257	524	12	887	80526	262	0	848	54	1640	81415	539	4126	14	1	5110	1	17	1	1	40710	87434	80000	80100	40738	40798	40741	40859	40810
80204	40687	305	1	0	0	0	0	1953	874	796	1	704	131	144	40679	754	2090	1957	177	25	163206	83618	80000	80100	80000	411570	1873432	0	344	49	37580	0	40888	40687	30736	3	30695	160100	200	80000	200	160000	40673	75	1	1	80201	100	99	100	80000	100	80000	100	80896	8	4636	487	6	825	80542	268	0	914	46	1609	81429	549	4228	0	0	5110	1	16	1	1	40840	80636	80000	80100	40775	40784	40755	40755	40775
80204	40712	306	0	0	0	0	0	1842	667	814	1	696	108	100	40760	790	1729	1646	150	25	160736	80451	80000	80100	80000	402474	1871931	0	274	49	37644	0	40811	40797	30634	3	30699	160100	200	80000	200	160000	40855	75	1	1	80201	100	99	100	80000	100	80000	100	80873	0	4797	532	13	888	80507	303	0	877	68	1688	81383	484	4304	0	0	5110	1	17	1	1	40746	80193	80000	80100	40785	40884	40818	40690	40791
80204	40788	305	0	0	0	0	0	1827	829	743	1	688	113	192	40849	754	1744	1654	173	25	163120	80544	80000	80100	80000	401769	1875928	0	1056	49	37667	0	40762	40711	30770	3	30654	160100	200	80000	200	160000	40677	75	1	1	80201	100	99	100	80000	100	80000	100	80879	0	4318	508	3	826	80491	283	0	868	30	1557	81391	493	4775	0	0	5137	1	17	1	1	40690	80563	80000	80100	40827	40801	40831	40744	40669
80204	40812	305	0	0	0	0	0	1809	892	789	1	704	79	96	40789	790	1884	1745	167	25	164250	81409	80005	80100	80000	403797	1874248	0	3366	49	37680	0	40785	40767	30683	3	30542	160100	200	80000	200	160000	40679	76	1	1	80201	100	99	100	80000	100	80000	100	80917	0	4341	504	7	871	80521	251	0	896	78	1548	81378	471	4085	0	0	5110	1	18	1	1	40693	80525	80000	80100	40768	40818	40654	40698	40687
80204	40807	305	0	0	0	0	0	1890	734	798	1	736	101	128	40826	788	1874	1901	151	25	167236	81036	80000	80100	80000	413977	1875088	0	106	49	37675	0	40792	40800	30640	3	30680	160100	200	80000	200	160000	40800	75	1	1	80201	100	99	100	80000	100	80000	100	80858	0	4370	476	4	835	80478	283	0	873	30	1661	81449	531	3970	0	0	5110	1	16	1	1	40687	80385	80000	80100	40782	40760	40832	40695	40709
80204	40699	304	0	0	0	0	0	1890	788	767	1	672	109	132	40736	760	1877	1937	194	25	160475	80286	80059	80100	80000	402886	1875016	0	1265	49	37763	0	40789	40738	30598	3	30779	160100	200	80000	200	160000	40743	75	1	1	80201	100	99	100	80000	100	80000	100	80881	0	4521	514	14	858	80525	293	0	848	42	1654	81345	535	3925	0	0	5110	1	16	1	1	40750	80574	80000	80100	40853	40772	40831	40807	40761

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5101

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	1e	1f	20	22	29	3a	3e	3f	40	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80029	40804	305	0	0	1554	917	754	1	696	111	108	40879	778	2025	2103	151	25	160585	84302	80083	80010	80000	401097	1879874	0	198	49	37774	0	40807	40708	30682	3	30855	160010	20	80000	20	160000	40803	85	1	1	80021	10	9	10	80000	10	80000	10	80877	0	4086	475	5	861	80561	239	0	835	32	1609	81356	569	4135	14	0	5023	0	2	17	2	2	3	40881	80225	80000	80010	40749	40865	40786	40788	40764
80024	40794	306	0	0	1638	766	784	1	720	86	116	40795	768	1814	1686	189	25	160653	86259	80000	80010	80000	401187	1875304	1	325	49	37575	0	40784	40801	30702	3	30725	160010	20	80000	20	160000	40812	76	1	1	80021	10	9	10	80000	10	80000	10	80886	0	4247	471	11	835	80486	267	1	849	26	1535	81409	574	4296	0	0	5023	0	2	16	2	2	3	40800	82510	80000	80010	40929	40856	40845	40838	40683
80024	40873	305	0	0	1590	869	794	1	672	124	100	40776	758	1702	1963	195	25	168179	87232	80000	80010	80000	417205	1878112	0	2506	49	37734	0	40846	40784	30739	3	30767	160010	20	80000	20	160000	40833	75	1	1	80021	10	9	10	80000	10	80000	10	80841	0	4158	431	4	877	80501	222	0	823	34	1392	81361	544	4173	0	0	5023	0	2	16	2	2	3	40803	80559	80000	80010	40818	40724	40665	40964	40856
80024	40852	306	0	0	1632	800	772	1	672	123	108	40740	777	1974	1736	136	25	160568	80344	80000	80010	80000	402318	1874956	0	216	49	37667	0	40822	40756	30754	3	30832	160010	20	80000	20	160000	40799	75	1	1	80021	10	9	10	80000	10	80000	10	80878	0	4298	439	2	852	80537	249	0	871	32	1548	81431	518	4193	0	0	5023	0	2	18	2	2	3	40846	83646	80000	80010	40816	40789	40793	40746	40716
80024	40830	306	0	0	1728	748	767	1	672	115	100	40805	753	1554	1783	144	25	160575	80591	80000	80010	80000	421585	1879154	0	347	49	37758	0	40827	40793	30720	3	30894	160010	20	80000	20	160000	40738	75	1	1	80021	10	9	10	80000	10	80000	10	80859	0	4179	467	7	856	80456	220	0	843	30	1488	81419	544	4203	0	0	5023	0	2	16	2	2	3	40816	80401	80000	80010	40835	40806	40864	40795	40723
80024	40780	306	0	0	1710	768	774	1	744	116	96	40810	767	1409	1660	145	25	168650	85543	80000	80010	80000	402498	1876720	0	280	49	37693	0	40796	40774	30710	3	30806	160010	20	80000	20	160000	40787	76	1	1	80021	10	9	10	80000	10	80000	10	80858	0	4235	494	10	853	80544	227	0	867	36	1343	81471	562	4119	0	0	5023	0	2	16	2	2	3	40756	80677	80000	80010	40773	40819	40818	40762	40825
80024	40813	305	0	0	1812	835	770	1	728	106	132	40833	742	1667	1783	143	25	161814	80407	80000	80010	80000	400856	1878256	0	312	49	37757	0	40770	40814	30712	3	30865	160010	20	80000	20	160000	40707	75	1	1	80021	10	9	10	80000	10	80000	10	80842	0	3995	463	6	836	80477	215	0	902	32	1318	81382	516	4037	0	0	5023	0	2	17	2	2	3	40759	80730	80000	80010	40803	40825	40820	40781	40962
80025	40782	305	0	0	1638	784	755	1	688	122	136	40766	767	1862	1866	152	25	160554	80358	80000	80010	80000	401899	1872568	0	324	49	37839	0	41042	40911	30843	3	30773	160010	20	80000	20	160000	40871	75	1	1	80021	10	9	10	80000	10	80000	10	80847	0	4498	516	6	854	80496	231	0	869	28	1569	81373	498	4287	0	0	5023	0	2	18	2	2	3	40792	84313	80000	80010	40826	40736	40836	40768	40862
80024	40829	306	0	0	1596	830	803	1	688	99	108	40876	757	1873	2026	145	25	160572	88375	80000	80010	80000	404382	1874824	0	261	49	37739	0	40790	40751	30662	3	30765	160010	20	80000	20	160000	40749	75	1	1	80021	10	9	10	80000	10	80000	10	80867	0	4433	422	10	829	80554	262	0	873	78	1556	81383	528	4081	14	1	5023	0	2	17	2	2	3	40694	81913	80000	80010	40789	40829	40728	40812	40761
80024	40836	306	0	0	1821	838	796	1	680	115	104	40756	751	1844	1750	161	25	162212	80408	80000	80010	80000	401764	1874848	0	633	49	37709	0	40751	40849	30752	3	30773	160010	20	80000	20	160000	40813	76	1	1	80021	10	9	10	80000	10	80000	10	80837	0	4416	459	9	897	80481	243	0	851	82	1490	81383	528	3425	0	0	5023	0	2	18	2	2	3	40886	80375	80000	80010	40712	40772	40797	40828	40804

STRH (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations