Firestorm: STRH measurements

Code:

  strh w0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	560	4	0	3	1	527	16	16	0	25	1000	1000	1000	22424	549	542	363	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	0	8	1002	2	34	73	2	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	9	1	534	16	16	0	25	1000	1000	1000	22808	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	3	0	534	16	16	0	25	1000	1000	1000	22424	549	542	363	3	400	1000	1000	2000	550	542	1	1	1001	1000	1000	1000	0	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	647	543	543	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22424	542	549	355	3	400	1000	1000	2000	542	550	1	1	1001	1000	1000	1000	0	34	1002	0	8	1002	2	34	73	1	16	1	1	548	1000	552	552	543	543	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22424	549	542	363	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	0	5	1002	2	34	73	1	16	1	1	546	1000	550	543	543	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22424	542	550	355	3	407	1000	1000	2000	542	551	1	1	1001	1000	1000	1000	0	34	1002	0	8	1002	2	34	73	1	16	1	1	539	1000	550	551	543	543	543
1004	542	4	0	3	1	535	16	16	0	25	1000	1000	1000	22784	542	542	363	3	400	1000	1000	2000	550	542	1	1	1001	1000	1000	1000	0	34	1002	0	2	1002	2	34	73	1	16	1	1	539	1000	550	551	543	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22760	542	542	355	3	407	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	0	2	1002	2	34	73	1	16	1	1	548	1000	551	552	543	543	543
1004	542	4	0	3	0	527	16	16	0	25	1000	1000	1000	22760	542	542	355	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	0	8	1002	2	34	73	1	16	1	1	548	1000	543	543	583	543	552
1004	542	4	0	3	0	535	16	16	0	25	1000	1000	1000	22784	542	542	364	3	408	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	34	1002	0	8	1002	2	34	73	1	16	1	1	539	1000	551	552	543	543	543

Count: 8

Code:

  strh w0, [x6]
  strh w0, [x6]
  strh w0, [x6]
  strh w0, [x6]
  strh w0, [x6]
  strh w0, [x6]
  strh w0, [x6]
  strh w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	300	0	0	0	693	3	1	0	40028	16	16	1	25	80100	100	80000	100	80006	500	1839474	0	49	36962	40040	40042	29961	7	29995	80106	200	80016	200	160032	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	80002	2	0	0	1	1	1	5118	11	16	10	10	40037	80000	100	40041	40055	40043	40043	40043
80204	40042	300	0	0	0	117	0	1	0	40025	16	16	1	25	80100	100	80000	100	80006	500	1839503	0	49	36962	40040	40043	29961	7	30006	80106	200	80016	200	160032	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	2	42	0	1	1	1	5118	10	16	7	12	40039	80000	100	40044	40043	40041	40044	40043
80204	40040	300	0	0	0	486	3	1	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839472	0	49	36962	40043	40043	29955	3	30012	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	0	0	0	0	0	0	5110	12	16	12	14	40040	80000	100	40041	40043	40041	40044	40043
80204	40043	300	0	0	0	525	3	0	0	40025	0	16	1	25	80100	100	80000	100	80000	500	1839352	0	49	36960	40040	40042	30014	3	30012	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	2	42	0	0	0	0	5110	13	16	11	11	40039	80000	100	40043	40043	40043	40043	40041
80204	40040	300	0	0	0	0	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839448	0	49	36974	40042	40040	29955	3	30001	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	80000	2	0	0	0	0	0	5110	11	16	10	12	40039	80000	100	40043	40041	40043	40043	40043
80204	40042	300	0	0	0	519	3	1	0	40025	16	16	1	25	80100	100	80000	100	80000	500	1839472	0	49	36960	40042	40042	29956	3	29998	80100	200	80000	200	160000	40054	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	1	0	80002	0	42	0	0	0	0	5110	12	16	10	10	40039	80000	100	40041	40041	40043	40044	40043
80204	40040	300	0	0	1	84	3	1	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	0	49	36962	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	0	80002	2	42	0	0	0	0	5110	10	16	8	11	40037	80000	100	40043	40043	40041	40043	40043
80204	40040	300	0	0	0	516	3	1	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839352	0	49	36962	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80000	0	2	80002	2	42	0	0	0	0	5110	12	16	11	7	40039	80000	100	40043	40043	40043	40043	40044
80204	40040	300	0	0	0	450	0	1	0	40028	0	0	0	25	80100	100	80000	100	80000	500	1839448	0	49	36960	40040	40043	29953	3	30000	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80000	0	2	80002	2	42	0	0	0	0	5110	12	16	11	10	40039	80000	100	40043	40043	40043	40043	40041
80204	40042	300	0	0	0	444	3	1	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839448	0	49	36960	40042	40040	29955	3	30000	80100	200	80000	200	160000	40043	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	1	2	80002	0	42	0	0	0	0	5110	12	16	11	10	40037	80000	100	40044	40043	40043	40044	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	1	1	0	1	24	20	1	0	0	1	40037	16	16	5	25	80010	10	80000	10	80000	50	1839860	1	49	36980	40058	40047	29996	3	30040	80010	20	80000	20	160000	40058	40057	1	1	80021	10	9	10	80000	10	80000	10	80014	14	0	0	0	80016	0	1	18	80002	16	36	14	1	5020	0	16	16	10	10	40046	0	80000	10	40060	40053	40062	40053	40060
80024	40053	300	1	1	1	0	6	15	1	0	0	1	40044	16	16	5	25	80010	10	80000	10	80000	50	1840268	1	49	36972	40052	40053	29987	3	30038	80010	20	80000	20	160000	40053	40047	1	1	80021	10	9	10	80000	10	80000	10	80016	15	36	0	1	80016	0	0	14	80002	14	36	14	0	5020	0	9	16	10	8	40056	0	80000	10	40053	40060	40053	40048	40053
80024	40047	300	1	0	0	1	0	19	1	0	0	1	40036	0	16	0	25	80010	10	80000	10	80000	50	1839692	1	49	36983	40048	40047	29995	3	30032	80010	20	80000	20	160000	40058	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	36	0	2	80016	0	0	14	80000	16	36	14	1	5020	0	9	16	9	9	40048	0	80000	10	40061	40060	40061	40059	40049
80024	40052	300	1	0	1	0	0	17	1	0	0	1	40038	16	16	1	25	80010	10	80000	10	80000	50	1839932	1	49	36970	40058	40050	29985	3	30032	80010	20	80000	20	160000	40060	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	15	0	0	0	80016	0	1	17	80000	16	0	14	2	5020	0	9	16	10	10	40047	0	80000	10	40059	40053	40061	40060	40059
80024	40047	300	1	0	0	0	6	19	1	0	0	1	40046	16	16	9	25	80010	10	80000	10	80000	50	1840174	1	49	36969	40058	40058	29994	3	30040	80010	20	80000	20	160000	40058	40058	1	1	80021	10	9	10	80000	10	80000	10	80014	16	36	0	1	80016	1	0	15	80002	16	34	14	1	5020	0	9	16	9	8	40044	0	80000	10	40059	40048	40060	40051	40053
80024	40061	300	1	1	0	1	0	14	1	0	0	1	40035	16	16	0	40	80010	10	80000	10	80000	50	1840220	1	49	36987	40052	40059	29987	3	30039	80010	20	80000	20	160000	40047	40059	1	1	80021	10	9	10	80000	10	80000	10	80014	15	0	2	0	80014	0	0	18	80000	16	36	14	0	5020	0	10	16	10	9	40044	0	80000	10	40053	40060	40054	40060	40052
80024	40058	300	1	0	0	1	0	19	1	0	0	1	40043	16	16	5	25	80010	10	80000	10	80000	50	1839692	1	49	36981	40052	40059	29987	3	30027	80010	20	80000	20	160000	40052	40059	1	1	80021	10	9	10	80000	10	80000	10	80014	15	36	0	1	80016	0	0	17	80000	16	36	14	1	5020	0	10	16	9	10	40058	0	80000	10	40060	40053	40059	40048	40059
80024	40047	300	1	0	1	1	0	19	0	0	0	1	40035	16	0	5	25	80010	10	80000	10	80000	50	1840244	1	49	36972	40053	40052	29987	3	30027	80010	20	80000	20	160000	40053	40058	1	1	80021	10	9	10	80000	10	80000	10	80015	15	36	0	1	80014	0	1	18	80002	16	36	14	2	5020	0	8	16	10	11	40049	0	80000	10	40053	40049	40054	40060	40052
80024	40058	300	1	1	1	1	0	19	1	0	0	1	40044	16	15	5	25	80010	10	80000	10	80000	50	1840268	1	49	36973	40051	40053	29987	3	30038	80010	20	80000	20	160000	40052	40052	1	1	80021	10	9	10	80000	10	80000	10	80016	14	0	0	0	80016	0	1	18	80002	16	36	14	1	5020	0	10	16	9	9	40048	0	80000	10	40061	40060	40048	40059	40058
80024	40047	300	1	1	1	1	0	21	1	0	0	1	40044	0	16	5	25	80010	10	80000	10	80000	50	1839956	1	49	36971	40061	40051	29986	3	30039	80010	20	80000	20	160000	40049	40052	1	1	80021	10	9	10	80000	10	80000	10	80014	14	36	0	0	80016	0	1	19	80000	14	35	14	2	5020	0	10	16	9	9	40055	0	80000	10	40054	40059	40048	40062	40053

STRH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations