Firestorm: STP (64-bit) measurements

Code:

  stp x0, x1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	547	4	1	1	1	1	0	21	0	1	543	16	16	9	25	1000	1000	1000	23174	1	547	559	364	3	410	1000	1000	3000	547	552	1	1	1001	1000	1000	1014	14	36	0	0	1016	0	0	18	1000	16	36	14	1	73	3	16	4	4	544	1000	553	553	551	548	559
1004	557	4	1	1	1	0	0	15	1	1	545	16	16	0	25	1000	1000	1000	23292	0	559	552	371	3	410	1000	1000	3000	547	552	1	1	1001	1000	1000	1014	15	36	2	1	1014	0	1	17	1002	14	0	14	1	73	3	16	4	4	555	1000	562	560	560	560	548
1004	547	4	1	1	0	0	0	14	0	1	532	0	0	2	25	1000	1000	1000	22692	1	547	560	360	3	405	1000	1000	3000	547	547	1	1	1001	1000	1000	1014	15	0	0	0	1014	0	1	18	1002	16	36	14	1	73	4	16	4	4	544	1000	549	559	548	553	554
1004	552	4	1	0	1	1	0	17	0	1	537	16	16	7	25	1000	1000	1000	23197	0	547	551	361	3	408	1000	1000	3000	547	547	1	1	1001	1000	1000	1016	14	36	0	2	1014	0	0	18	1002	14	36	14	0	73	4	16	4	4	549	1000	548	560	553	548	552
1004	550	4	1	0	1	0	0	14	0	1	532	16	16	5	25	1000	1000	1000	22718	1	560	547	360	3	405	1000	1000	3000	551	559	1	1	1001	1000	1000	1014	14	0	0	0	1016	0	0	18	1002	16	36	14	1	73	4	16	4	4	544	1000	548	559	548	554	554
1004	552	4	1	1	1	1	0	21	0	1	532	16	0	0	25	1000	1000	1000	22932	1	547	549	360	3	418	1000	1000	3000	558	552	1	1	1001	1000	1000	1014	14	36	0	1	1014	0	0	20	1000	14	0	14	1	73	4	16	4	4	556	1000	559	553	554	548	552
1004	547	4	1	1	1	0	0	19	0	1	627	16	16	3	25	1000	1000	1000	22788	0	559	551	361	3	409	1000	1000	3000	558	547	1	1	1001	1000	1000	1015	14	0	0	1	1014	2	1	18	1002	16	36	14	1	73	4	16	4	4	555	1000	552	561	559	560	548
1004	547	5	1	1	1	0	0	14	1	1	543	16	16	5	25	1000	1000	1000	22692	0	547	552	373	3	405	1000	1000	3000	560	547	1	1	1001	1000	1000	1015	15	0	0	0	1014	0	0	18	1002	16	0	14	0	73	4	16	4	4	549	1000	548	548	548	548	561
1004	560	4	1	0	1	1	0	14	0	1	532	16	0	6	25	1000	1000	1000	22692	0	558	553	360	3	410	1000	1000	3000	558	547	1	1	1001	1000	1000	1015	16	36	0	1	1014	0	0	14	1002	16	35	14	1	73	4	16	4	4	550	1000	560	548	548	551	548
1004	547	4	1	1	0	1	0	18	1	1	536	16	16	5	25	1000	1000	1000	23268	0	553	557	360	3	405	1000	1000	3000	547	547	1	1	1001	1000	1000	1014	15	0	0	0	1016	0	1	17	1000	16	36	14	1	73	4	16	4	4	555	1000	560	560	548	553	552

Count: 8

Code:

  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]
  stp x0, x1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	22	23	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	299	4	24	3	1	0	0	40025	16	16	1	25	80100	100	80000	100	80006	500	1839474	1	49	36960	0	40042	40042	29962	7	29994	80106	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	80002	2	42	1	1	1	5118	0	16	0	1	40037	80000	100	40041	40054	40041	40043	40044
80204	40040	300	0	0	3	0	0	0	40027	16	0	0	25	80100	100	80000	100	80006	500	1839936	1	49	36960	0	40042	40042	29961	7	29992	80106	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	0	0	1	1	1	5118	0	16	0	1	40037	80000	100	40043	40043	40044	40044	40044
80204	40043	300	0	0	3	1	0	0	40027	0	16	0	25	80100	100	80000	100	80006	500	1839378	1	49	36962	0	40054	40040	29961	7	29994	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	0	80002	2	42	1	1	1	5118	0	16	0	1	40039	80000	100	40041	40043	40041	40041	40043
80204	40040	299	0	0	3	1	0	0	40025	16	16	0	25	80100	100	80000	100	80006	500	1839474	1	49	36962	0	40040	40042	29959	7	29994	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80000	0	2	80002	2	42	1	1	1	5118	0	16	0	1	40041	80000	100	40041	40043	40044	40044	40041
80204	40040	299	0	0	0	0	0	0	40027	16	0	0	25	80100	100	80000	100	80006	500	1839474	1	49	36962	0	40042	40042	29961	7	29995	80106	200	80016	200	240048	40042	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	2	80002	2	0	1	1	1	5118	0	16	0	1	40040	80000	100	40041	40043	40043	40043	40055
80204	40040	300	0	0	3	0	0	0	40027	16	0	1	25	80100	100	80000	100	80006	500	1839474	1	49	36962	0	40042	40042	29967	3	30000	80100	200	80000	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	80002	0	0	80002	2	42	0	0	0	5110	1	16	1	2	40037	80000	100	40043	40044	40044	40043	40044
80204	40042	299	0	0	3	0	0	0	40027	16	0	0	25	80100	100	80000	100	80000	500	1839448	1	49	36962	0	40042	40042	29953	3	29998	80100	200	80000	200	240000	40040	32007	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80000	0	2	80000	2	42	0	0	0	5110	1	16	1	2	40040	80000	100	40041	40055	40041	40043	40043
80204	40040	300	0	0	3	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839448	1	49	36962	0	40042	40042	29956	3	30000	80230	200	80000	200	240000	40043	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	6	80000	0	42	0	0	0	5110	1	16	1	2	40040	80000	100	40043	40044	40044	40043	40041
80204	40042	300	0	0	3	1	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839352	1	49	36962	0	40043	40042	29955	3	30000	80100	200	80000	200	240000	40043	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	2	42	0	0	0	5110	1	16	1	2	40037	80000	100	40043	40041	40043	40043	40043
80204	40042	300	0	12	3	0	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1839448	1	49	36962	0	40040	40040	29955	3	29998	80100	200	80000	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	42	0	80002	0	2	80002	2	42	0	0	0	5110	1	16	1	2	40037	80000	100	40041	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	299	0	0	0	0	0	9	18	1	0	0	40027	0	0	0	25	80010	10	80000	10	80000	50	1839448	49	36960	40042	40043	29977	3	30020	80010	20	80000	20	240000	40043	40043	1	1	80021	10	9	10	80000	10	80000	10	80015	15	44	0	0	80016	0	0	16	80002	14	44	14	2	0	5020	0	14	16	3	2	40050	0	80000	10	40052	40048	40052	40055	40064
80024	40054	300	1	1	1	0	0	0	20	0	0	0	40028	0	16	0	25	80010	10	80000	10	80000	50	1839448	49	36960	40043	40043	29977	3	30034	80010	20	80000	20	240000	40053	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	15	44	0	1	80016	0	0	16	80002	14	44	14	0	0	5020	0	2	16	2	2	40039	0	80000	10	40043	40043	40041	40041	40041
80024	40040	299	0	0	0	0	0	0	3	0	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	49	36963	40043	40043	29977	3	30022	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	0	80000	2	42	0	0	0	5020	0	3	16	2	2	40039	0	80000	10	40043	40043	40041	40043	40043
80024	40042	300	0	0	0	0	0	0	3	1	0	0	40025	0	16	0	25	80010	10	80000	10	80000	50	1840000	49	36962	40042	40042	29977	3	30024	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	2	80002	2	0	0	0	0	5020	0	3	16	3	2	40037	0	80000	10	40041	40041	40044	40043	40044
80024	40042	300	0	0	0	0	0	0	22	1	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839448	49	36960	40042	40040	29977	3	30020	80010	20	80000	20	240000	40043	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	80002	0	42	0	0	0	5020	0	2	16	2	6	40037	0	80000	10	40044	40044	40043	40043	40044
80024	40040	300	0	0	0	0	0	0	19	1	0	0	40039	16	16	1	25	80010	10	80000	10	80000	55	1839448	49	36960	40042	40040	29977	3	30020	80442	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	0	0	2	80000	2	0	0	0	0	5020	0	2	16	6	2	40037	0	80000	10	40044	40043	40043	40044	40043
80024	40043	300	0	0	0	0	0	0	3	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839352	49	36962	40040	40042	29978	3	30023	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	5	80000	2	42	0	0	1	5020	0	2	16	2	2	40050	0	80000	10	40053	40048	40053	40048	40064
80024	40054	300	1	1	0	0	0	0	18	1	0	1	40039	16	0	2	25	80010	10	80000	10	80000	50	1840508	49	36974	40047	40054	29982	3	30027	80010	20	80000	20	240000	40054	40052	1	1	80021	10	9	10	80000	10	80000	10	80015	14	43	0	1	80016	0	0	14	80002	16	44	14	0	0	5020	0	6	16	2	6	40039	0	80000	10	40041	40041	40043	40043	40044
80024	40042	300	0	0	0	0	0	12	17	0	0	1	40039	15	16	1	25	80010	10	80000	10	80000	50	1839956	49	36983	40054	40054	29989	3	30043	80010	20	80000	20	240000	40054	40055	1	1	80021	10	9	10	80000	10	80000	10	80015	15	44	0	2	80016	1	1	19	80002	14	44	14	0	0	5020	0	2	16	2	2	40039	0	80000	10	40044	40043	40041	40041	40043
80024	40043	300	0	0	0	0	0	0	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	49	36974	40042	40043	29977	3	30034	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	1	0	0	80000	2	0	0	0	0	5020	0	2	16	2	2	40039	0	80000	10	40043	40041	40041	40043	40041

STP (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations