Firestorm: STR (64-bit) measurements

Code:

  str x0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	0	3	1	527	16	16	0	25	1000	1000	1000	22472	542	542	355	3	400	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	2	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	3	0	527	16	16	1	25	1000	1000	1000	22472	542	542	356	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	540	1000	544	544	544	544	543
1004	542	4	0	0	3	0	527	16	16	1	25	1000	1000	1000	22472	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	3	0	528	16	16	0	25	1000	1000	1000	22472	542	543	356	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	544	544	543	543	543
1004	542	4	0	0	3	1	528	16	16	0	25	1000	1000	1000	22448	554	542	355	3	400	1000	1000	2000	554	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	3	0	528	16	16	0	25	1000	1000	1000	22448	542	543	356	3	400	1000	1000	2000	554	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	3	0	0	3	0	527	16	16	6	25	1000	1000	1000	22448	543	543	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	541	543	555	543	543
1004	542	4	0	0	3	0	527	16	16	1	25	1000	1000	1000	22448	543	543	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	1	2	1002	2	42	73	1	16	1	1	539	1000	544	544	544	544	544
1004	543	4	0	0	3	1	527	16	16	1	25	1000	1000	1000	22448	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	42	0	1002	2	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543
1004	554	4	0	0	3	0	527	16	16	0	25	1000	1000	1000	22472	542	543	356	3	400	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	42	0	1002	0	2	1002	2	42	73	1	16	1	1	539	1000	543	543	543	543	543

Count: 8

Code:

  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]
  str x0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40057	300	1	1	1	0	0	3	1	0	1	40038	16	16	1	25	80100	100	80000	100	80000	500	1840316	0	49	36978	40047	40058	29972	3	30016	80100	200	80000	200	160000	40049	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80000	0	0	2	80000	2	34	0	0	5110	14	16	12	7	40039	80000	100	40043	40041	40043	40043	40041
80204	40049	300	0	0	0	0	0	0	1	0	1	40044	16	0	3	25	80100	100	80000	100	80000	500	1840316	0	49	36978	40053	40047	29960	3	30006	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80000	0	0	2	80002	0	0	0	0	5110	10	16	12	11	40037	80000	100	40041	40043	40050	40043	40043
80204	40040	300	0	0	0	0	0	0	1	0	1	40043	0	16	5	25	80100	100	80000	100	80000	500	1839908	0	49	36979	40052	40059	29965	3	30017	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80002	0	0	2	80000	2	34	0	0	5110	8	16	10	12	40037	80000	100	40043	40041	40043	40043	40043
80204	40050	300	0	0	0	0	0	3	1	0	1	40045	16	16	6	25	80100	100	80000	100	80000	500	1839693	0	49	36979	40052	40052	29966	3	30017	80208	200	80000	200	160000	40050	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	0	80062	0	0	8	80002	2	0	0	0	5110	12	16	11	11	40056	80000	100	40054	40058	40053	40059	40052
80204	40047	300	1	1	0	0	0	19	1	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36960	40042	40040	29953	3	29998	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80000	1	0	0	80002	2	0	0	0	5110	12	16	12	13	40044	80000	100	40048	40053	40049	40054	40060
80204	40051	299	1	1	1	0	0	14	1	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839352	0	49	36962	40042	40051	29953	3	30000	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80000	0	0	0	80002	0	0	0	0	5110	12	16	12	12	40044	80000	100	40053	40060	40054	40058	40051
80204	40058	300	1	1	0	0	3	19	1	0	0	40025	16	16	0	25	80100	100	80000	100	80000	500	1839352	0	49	36960	40040	40042	29955	3	29998	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80002	0	0	0	80002	0	34	0	0	5110	13	16	12	11	40056	80000	100	40060	40051	40059	40051	40053
80204	40060	300	1	0	0	0	6	18	1	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839424	0	49	36970	40040	40040	29955	3	30000	80100	200	80000	200	160000	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	0	80000	0	0	2	80000	0	34	0	0	5110	12	16	12	10	40039	80000	100	40041	40043	40043	40041	40041
80204	40042	300	0	0	0	0	0	3	1	0	0	40027	0	16	0	25	80100	100	80000	100	80000	500	1839352	0	49	36969	40040	40040	29953	3	29998	80100	200	80000	200	160000	40047	32006	1	1	80201	100	99	100	80000	100	80000	100	80015	14	36	0	0	80016	0	0	16	80000	16	36	14	0	5110	11	16	11	11	40397	80000	100	40041	40051	40043	40043	40041
80204	40051	300	0	0	0	0	0	3	1	0	0	40025	16	0	0	25	80100	100	80000	100	80000	500	1839424	0	49	36971	40040	40040	29953	3	30008	80100	200	80000	200	160000	40047	32011	1	1	80201	100	99	100	80000	100	80000	100	80015	15	36	0	0	80016	0	1	14	80002	14	0	14	0	5110	11	16	12	12	40048	80000	100	40043	40041	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	22	24	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40050	300	0	0	0	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	0	0	49	36971	40042	40040	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	1	2	80000	2	34	0	5020	5	0	3	16	4	6	40046	0	80000	10	40041	40043	40051	40043	40043
80024	40049	299	0	0	0	0	1	0	40025	16	16	83	55	80130	10	80060	10	80000	50	1839760	0	0	0	49	36962	40051	40042	29985	3	30022	80010	20	80000	20	160000	40339	40272	3	1	80021	10	9	10	80000	10	80000	10	80122	34	80060	2	8	80000	2	0	0	5020	0	0	5	16	5	3	40047	0	80000	10	40043	40041	40043	40041	40041
80024	40051	300	0	0	0	3	1	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	0	0	49	36962	40051	40050	29985	3	30022	80010	20	80000	20	160000	40051	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	0	2	80000	2	0	0	5020	0	0	3	16	3	5	40039	0	80000	10	40043	40050	40043	40041	40043
80024	40042	300	0	0	0	9	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	0	0	49	36962	40042	40040	29975	3	30031	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	0	2	80000	2	34	0	5020	0	0	5	16	3	5	40037	0	80000	10	40041	40043	40052	40043	40043
80024	40050	300	0	0	0	3	1	0	40034	16	16	0	25	80010	10	80000	10	80000	50	1845205	0	0	5	49	36970	40042	40051	29977	3	30022	80010	20	80000	20	160000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80000	0	5	80002	2	34	0	5020	0	0	3	16	3	5	40039	0	80000	10	40041	40043	40041	40050	40043
80024	40058	300	0	0	0	0	1	0	40027	16	16	3	25	80010	10	80000	10	80000	50	1839352	0	0	0	49	36962	40051	40050	29985	3	30022	80010	20	80000	20	160000	40051	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	0	2	80002	2	34	0	5020	0	0	3	16	5	3	40039	0	80000	10	40043	40050	40041	40051	40043
80024	40042	299	0	0	0	3	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	0	0	49	36962	40042	40040	29977	3	30031	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	80002	0	2	80002	2	0	0	5020	0	0	3	16	3	5	40037	0	80000	10	40043	40043	40043	40041	40041
80024	40042	300	0	0	0	3	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	0	0	49	36960	40040	40042	29975	3	30029	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80000	0	8	80000	2	34	0	5020	0	0	3	16	7	4	40037	0	80000	10	40043	40043	40043	40041	40043
80024	40042	300	0	0	0	3	1	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839472	0	0	0	49	36960	40051	40040	29975	3	30020	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80000	0	2	80002	2	34	0	5020	0	0	3	16	3	5	40039	0	80000	10	40041	40050	40043	40051	40043
80024	40042	300	0	1	6	0	0	0	40027	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	0	0	49	36962	40040	40040	29977	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	34	80002	0	179	80000	2	34	0	5020	0	0	5	16	5	5	40037	0	80000	10	40041	40041	40043	40041	40043

STR (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations