Firestorm: UMULH measurements

Code:

  umulh x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	23	1	1	0	2	69	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	1	1	0	2	90	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	24	1	1	0	2	69	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1061	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	24	1	1	0	2	178	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	12	3	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	1	1	0	2	68	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3078
1004	3077	23	1	1	0	2	68	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	1	1	0	2	68	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	1	1	3	2	68	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	1	1	0	2	174	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	1	1	0	2	68	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	76	4	16	4	4	2863	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  umulh x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	549	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	474	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	435	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	471	536	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	4	2	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	420	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	414	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	9	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	432	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	501	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30076	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	411	61	29809	25	10100	10100	10100	1665186	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30509	227	0	0	12	11	1584	942	4383	29710	260	10092	10033	10680	1668745	0	49	27464	30511	30508	28664	48	28947	10686	10829	21636	30511	296	12	1	10021	10	9	10	10010	10	0	1	4613	2	670	5	33	5	3	30022	10053	10010	30249	30359	30120	30336	30337
10024	30077	227	1	1	4	8	1056	352	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29960	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28814	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30063	30034	30034
10024	30033	224	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	12	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10022	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	224	0	0	0	0	429	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	3	16	3	3	29864	10000	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  umulh x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	348	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	204	61	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	42	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	6	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	12	61	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	775	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	103	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	3	61	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	12	61	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30207
10204	30033	224	0	441	29809	25	10100	10100	10372	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	441	29809	25	10100	10100	10100	1665186	1	5	49	26953	0	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	5	0	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	0	0	0	0	0	0	1154	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	104	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10166	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	29809	25	10010	10010	10073	1665109	1	49	26953	30033	30033	28548	3	28788	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	1	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30076	225	0	0	0	0	0	0	0	61	29809	25	10010	10010	10317	1669102	0	49	27171	30466	30511	28651	58	29048	10441	10836	21352	30502	296	12	1	10021	10	9	10	10010	10	2	2	0	0	2	15818	2	824	4	105	2	3	30259	10088	10010	30510	30249	30510	30555	30290
10024	30513	228	0	1	0	11	6	1584	968	4222	29701	282	10091	10089	10503	1669460	0	49	27385	30294	30375	28655	44	28841	10621	10714	21348	30464	296	10	1	10021	10	9	10	10010	10	2	0	2	0	2	14633	2	772	3	89	2	3	29895	10025	10010	30162	30339	30123	30337	30335
10024	30337	226	0	0	1	2	8	1056	264	1210	29755	89	10061	10034	10317	1667292	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	29809	46	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	0	0	0	0	0	0	0	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034

Test 4: throughput

Count: 8

Code:

  umulh x0, x8, x9
  umulh x1, x8, x9
  umulh x2, x8, x9
  umulh x3, x8, x9
  umulh x4, x8, x9
  umulh x5, x8, x9
  umulh x6, x8, x9
  umulh x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	300	0	0	0	0	144	0	40	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	2	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	299	0	0	0	0	405	0	147	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	299	0	0	0	0	66	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	40	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	48	0	40	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40077	40036
80204	40035	300	0	0	0	0	54	0	40	48	80100	80100	80100	400500	1	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	12	0	40	25	80100	80100	80100	400500	0	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	299	0	0	0	0	42	0	40	25	80100	80100	80100	400500	0	49	33928	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	54	0	40	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	54	0	40	25	80100	80100	80100	400500	1	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40042	299	0	0	0	0	40	25	80010	80010	80010	400050	1	0	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	3	0	5020	0	0	18	16	0	0	17	17	40032	80000	80010	40036	40036	40036	40036	40074
80024	40035	300	0	0	0	0	135	25	80010	80010	80010	400050	1	6	49	36955	40035	40086	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	39	0	5020	6	0	7	16	0	0	7	17	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	40	25	80010	80010	80010	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	105	0	5020	6	0	6	16	0	0	8	17	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	40	25	80052	80010	80010	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	75	0	5020	0	0	17	16	0	0	17	17	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	40	25	80010	80010	80010	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	0	15	16	0	0	17	17	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	177	0	40	25	80010	80010	80010	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	0	17	16	0	0	17	6	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	21	0	40	25	80010	80010	80010	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	0	14	16	2	0	17	8	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	40	25	80010	80010	80010	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	0	7	16	0	0	17	17	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	299	0	0	0	0	40	25	80010	80010	80056	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	0	8	16	0	0	17	6	40032	80000	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	40	25	80010	80010	80010	400050	1	6	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	5020	6	0	8	16	0	0	17	8	40032	80000	80010	40036	40036	40036	40036	40036

UMULH

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations