Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMULH

Test 1: uops

Code:

  umulh x0, x0, x1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004303323110269280925100010001000161686140303330332676328911000100020003033296111001100000764164428631000100030343034303430343034
1004303323110290280925100010001000161686040303330332676328911000100020003033296111001100000764164428631000100030343034303430343034
1004303324110269280925100010001000161686040303330332676328911061100020003033296111001100000764164428631000100030343034303430343034
100430332411021782809251000100010001616861403033303326763289110001000200030332961110011000123764164428631000100030343034303430343034
1004303323110268280925100010001000161686140303330332676328911000100020003033296111001100000764164428631000100030343034303430343078
1004307723110268280925100010001000161686140303330332676328911000100020003033296111001100000764164428631000100030343034303430343034
1004303322110268280925100010001000161686140303330332676328911000100020003033296111001100000764164428631000100030343034303430343034
1004303323113268280925100010001000161686140303330332676328911000100020003033296111001100000764164428631000100030343034303430343034
10043033231102174280925100010001000161686140303330332676328911000100020003033296111001100000764164428631000100030343034303430343034
1004303322110268280925100010001000161686140303330332676328911000100020003033296111001100000764164428631000100030343034303430343034

Test 2: Latency 1->2

Code:

  umulh x0, x0, x1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102043003322505496129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034
102043003322504746129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034
102043003322504356129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034
1020430033225047153629809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100004200710116112986310000101003003430034300343003430034
102043003322504206129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034
102043003322504146129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034
1020430033225096129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034
102043003322504326129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034
102043003322505016129809251010010100101001665186492695303003330033285263287411010010200202003007629011102011009910010100100000000710116112986310000101003003430034300343003430034
102043003322504116129809251010010100101001665186492695303003330033285263287411010010200202003003329011102011009910010100100000000710116112986310000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fst unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024305092270012111584942438329710260100921003310680166874504927464305113050828664482894710686108292163630511296121100211091010010100146132670533533002210053100103024930359301203033630337
1002430077227114810563526129809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100000640316332996010000100103003430034300343003430034
10024300332250000006129809251001010010100101664736149269533003330033285483288141001010020200203003329611100211091010010100000640316332986410000100103003430034300633003430034
10024300332240000006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100000640316332986410000100103003430034300343003430034
10024300332250000006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100000640316332986410000100103003430034300343003430034
10024300332250000006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100000640316332986410000100103003430034300343003430034
10024300332250000006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100000640316332986410000100103003430034300343003430034
10024300332250000006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100000640316332986410000100103003430034300343003430034
100243003322500001206129809251001010010100101664736149269533003330033285483287631001010020200203003329611100221091010010100000640316332986410000100103003430034300343003430034
1002430033224000042906129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100000640316332986410000100103003430034300343003430034

Test 3: Latency 1->3

Code:

  umulh x0, x1, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204300332250612980925101001010010100166518615492695303003330033285263287411010010200202003003334811102011009910010100100000071050116112986310000101003003430034300343003430034
1020430033225204612980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100000071050142112986310000101003003430034300343003430034
10204300332250612980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100060071050116112986310000101003003430034300343003430034
102043003322512612980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100000077550116112986310000101003003430034300343003430034
102043003322501032980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100000071050116112986310000101003003430034300343003430034
10204300332253612980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100000071050116112986310000101003003430034300343003430034
10204300332250612980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100000071050116112986310000101003003430034300343003430034
102043003322412612980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100000071050116112986310000101003003430034300343003430207
102043003322404412980925101001010010372166518615492695303003330033285263287411010010200202003003329011102011009910010100100000071050116112986310000101003003430034300343003430034
102043003322504412980925101001010010100166518615492695303003330033285263287411010010200202003003329011102011009910010100100000071050116112986310000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250000000115429809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100000000640216222986410000100103003430034300343003430034
10024300332250000001046129809251001010010100101664736049269533003330033285483287631001010166200203003329611100211091010010100000000640216222986410000100103003430034300343003430034
100243003322500000006129809251001010010100731665109149269533003330033285483287881001010020200203003329611100211091010010100001000640216222986410000100103003430034300343003430034
1002430076225000000061298092510010100101031716691020492717130466305112865158290481044110836213523050229612110021109101001010220021581828244105233025910088100103051030249305103055530290
100243051322801011615849684222297012821009110089105031669460049273853029430375286554428841106211071421348304642961011002110910100101020202146332772389232989510025100103016230339301233033730335
1002430337226001281056264121029755891006110034103171667292049269533003330033285483287631001010020200203003329611100211091010010100000000640216222986410000100103003430034300343003430034
100243003322500000006129809251001010010100101664736149269533003330033285483287631001010020200203003329611100211091010010100000000640216222986410000100103003430034300343003430034
100243003322500000006129809461001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100000000640216222986410000100103003430034300343003430034
100243003322500000006129809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100000000640216222986410000100103003430034300343003430034
100243003322500000006129809251001010010100101664736049269533003330033285483287631001010020200203003329611100211091010010100000000640216222986410000100103003430034300343003430034

Test 4: throughput

Count: 8

Code:

  umulh x0, x8, x9
  umulh x1, x8, x9
  umulh x2, x8, x9
  umulh x3, x8, x9
  umulh x4, x8, x9
  umulh x5, x8, x9
  umulh x6, x8, x9
  umulh x7, x8, x9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204400513000000144040258010080100801004005001493695540035400352997032999380100802001602004003590118020110099100801001000000005110216114003280000801004003640036400364003640036
802044003529900004050147258010080100801004005001493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036
8020440035299000066040258010080100801004005000493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036
802044003530000000040258010080100801004005001493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036
8020440035300000048040258010080100801004005001493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364007740036
8020440035300000054040488010080100801004005001493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036
8020440035300000012040258010080100801004005000493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036
8020440035299000042040258010080100801004005000493392840035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036
8020440035300000054040258010080100801004005001493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036
8020440035300000054040258010080100801004005001493695540035400352997032999380100802001602004003590118020110099100801001000000005110116114003280000801004003640036400364003640036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)0318191e3a3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d2d5map dispatch bubble (d6)dadbddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024400422990000402580010800108001040005010493695540035400352999233001580010800201600204003590118002110910800101003050200018160017174003280000800104003640036400364003640074
80024400353000000135258001080010800104000501649369554003540086299923300158001080020160020400359011800211091080010100390502060716007174003280000800104003640036400364003640036
80024400353000000402580010800108001040005016493695540035400352999233001580010800201600204003590118002110910800101001050502060616008174003280000800104003640036400364003640036
800244003530000004025800528001080010400050164936955400354003529992330015800108002016002040035901180021109108001010075050200017160017174003280000800104003640036400364003640036
80024400353000000402580010800108001040005016493695540035400352999233001580010800201600204003590118002110910800101000050206015160017174003280000800104003640036400364003640036
800244003530000177040258001080010800104000501649369554003540035299923300158001080020160020400359011800211091080010100005020601716001764003280000800104003640036400364003640036
80024400353000021040258001080010800104000501649369554003540035299923300158001080020160020400359011800211091080010100005020601416201784003280000800104003640036400364003640036
8002440035300000040258001080010800104000501649369554003540035299923300158001080020160020400359011800211091080010100005020607160017174003280000800104003640036400364003640036
800244003529900004025800108001080056400050164936955400354003529992330015800108002016002040035901180021109108001010000502060816001764003280000800104003640036400364003640036
800244003530000004025800108001080010400050164936955400354003529992330015800108002016002040035901180021109108001010000502060816001784003280000800104003640036400364003640036