Firestorm: PRFM (register, PLIL2KEEP) measurements

Code:

  prfm plil2keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	61	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1617	12	30	15	30	2370	1603	874	25	1000	1000	1000	69643	5	1591	1571	1314	3	1480	1000	1000	1000	1585	1582	1	1	1001	266	2240	2203	3225	0	2389	2211	1000	73	5	1	16	1	1	1494	1000	1587	1622	1595	1615	1619
1004	1592	12	29	15	29	2388	1585	915	25	1000	1000	1000	70156	0	1591	1605	1318	3	1461	1000	1000	1000	1572	1599	1	1	1001	255	2204	2217	3234	0	2389	2198	1000	73	5	1	16	1	1	1528	1000	1620	1606	1617	1616	1609
1004	1600	12	29	15	30	2402	1600	901	25	1000	1000	1000	69710	0	1592	1601	1275	3	1447	1000	1000	1000	1593	1598	1	1	1001	265	2217	2208	3218	0	2404	2197	1000	73	5	1	16	1	1	1495	1000	1617	1614	1622	1610	1633
1004	1589	12	30	15	30	2402	1599	888	25	1000	1000	1000	69287	0	1600	1563	1303	3	1476	1000	1000	1000	1581	1592	1	1	1001	242	2210	2224	3207	0	2393	2225	1000	73	5	1	16	1	1	1512	1000	1589	1627	1613	1620	1629
1004	1619	12	30	15	30	2395	1590	875	25	1000	1000	1000	68885	0	1592	1589	1300	3	1435	1000	1000	1000	1602	1585	1	1	1001	290	2199	2230	3202	0	2376	2223	1000	73	5	1	16	1	1	1480	1000	1595	1603	1586	1624	1622
1004	1579	12	30	14	30	2386	1621	921	25	1000	1000	1000	69670	0	1604	1614	1297	3	1449	1000	1000	1000	1590	1600	1	1	1001	260	2202	2204	3219	0	2387	2211	1000	73	5	1	16	1	1	1506	1000	1619	1625	1619	1579	1608
1004	1608	12	30	15	29	2394	1611	907	25	1000	1000	1000	69738	0	1591	1598	1341	3	1483	1000	1000	1000	1594	1564	1	1	1001	254	2205	2187	3198	0	2365	2219	1000	73	5	1	16	1	1	1519	1000	1619	1621	1597	1615	1599
1004	1568	12	30	15	30	2387	1568	908	25	1000	1000	1000	69570	0	1597	1616	1309	3	1459	1000	1000	1000	1586	1599	1	1	1001	245	2220	2239	3239	0	2388	2249	1000	73	5	1	16	1	1	1511	1000	1606	1572	1599	1607	1591
1004	1625	13	30	14	28	2398	1600	904	25	1000	1000	1000	70244	0	1597	1623	1301	3	1445	1000	1000	1000	1595	1583	1	1	1001	235	2228	2237	3218	0	2396	2223	1000	73	5	1	16	1	1	1493	1000	1627	1624	1598	1637	1586
1004	1581	12	30	15	28	2390	1629	893	25	1000	1000	1000	71014	0	1592	1636	1344	3	1478	1000	1000	1000	1594	1587	1	1	1001	243	2230	2218	3216	0	2373	2207	1000	73	0	1	16	1	1	1490	1000	1685	1651	1568	1616	1614

Test 2: throughput

Code:

  prfm plil2keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5514

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15500	116	379	212	379	24913	15450	9517	25	20217	10202	10000	10100	10000	129766	728094	0	38	49	12377	15452	15545	12764	3	13033	20100	10200	10000	10200	10000	15532	155	1	1	20201	100	99	2067	100	10100	100	23405	23196	33073	0	24974	23338	10000	0	1310	1	16	1	1	15326	10108	10000	10100	15419	15499	15557	15527	15494
20204	15551	117	386	205	384	24999	15487	9580	25	20214	10205	10000	10100	10000	127937	721569	0	35	49	12459	15513	15459	12858	3	12966	20100	10200	10000	10200	10000	15511	155	1	1	20201	100	99	1886	100	10100	100	23347	23086	33433	0	24910	23112	10000	0	1310	1	16	1	1	15291	10099	10000	10100	15492	15462	15417	15549	15643
20204	15584	116	385	206	387	24930	15601	9388	25	20205	10211	10000	10100	10000	130285	724019	0	37	49	12346	15654	15607	12704	3	12903	20100	10200	10000	10200	10000	15425	156	1	1	20201	100	99	1959	100	10100	100	23250	23306	33121	0	24845	23298	10000	0	1310	1	16	1	1	15558	10093	10000	10100	15520	15582	15511	15496	15413
20204	15485	116	387	213	390	24841	15557	9472	25	20205	10226	10000	10100	10000	128302	722794	0	46	49	12377	15679	15433	12695	7	13030	20327	10200	10000	10200	10000	15450	156	1	1	20201	100	99	2162	100	10100	100	23474	23539	33269	0	26231	23516	10000	0	1311	1	16	1	1	15371	10111	10000	10100	15534	15682	15613	15742	15658
20204	15655	117	379	209	386	25016	15385	9639	25	20235	10223	10000	10100	10000	128016	726921	0	26	49	12417	15442	15389	12813	3	12954	20100	10200	10000	10200	10000	15585	154	1	1	20201	100	99	2104	100	10100	100	23407	23382	33327	1	24967	23417	10000	2	1310	1	16	1	1	15414	10129	10000	10100	15383	15510	15508	15434	15526
20204	15584	115	385	210	389	25137	15557	9437	25	20199	10196	10000	10100	10000	128000	727248	0	33	49	12364	15472	15278	12756	3	12896	20100	10200	10000	10200	10000	15374	154	1	1	20201	100	99	2008	100	10100	100	23389	23166	33533	0	24917	23436	10000	0	1310	1	16	1	1	15370	10105	10000	10100	15446	15549	15414	15519	15435
20204	15488	116	379	213	381	24842	15481	9415	25	20205	10238	10000	10100	10000	128102	728242	0	37	49	12358	15525	15539	12817	3	12916	20100	10200	10000	10200	10000	15386	156	1	1	20201	100	99	1959	100	10100	100	23277	23174	33517	0	24959	23288	10000	0	1310	1	16	1	1	15361	10099	10000	10100	15558	15392	15543	15384	15680
20204	15613	116	390	209	381	24871	15486	9545	25	20187	10199	10000	10100	10000	130396	726772	1	35	49	12498	15561	15409	12710	3	12929	20100	10200	10000	10200	10000	15485	156	1	1	20201	100	99	2034	100	10100	100	23077	23565	33293	0	25080	23107	10000	0	1310	1	16	1	1	15357	10120	10000	10100	15485	15547	15401	15526	15538
20204	15541	116	379	206	386	25193	15585	9542	25	20199	10214	10000	10100	10000	129475	728439	1	35	49	12421	15501	15553	12986	3	12994	20100	10200	10000	10200	10000	15594	156	1	1	20201	100	99	2043	100	10100	100	23410	23124	33151	0	25077	23172	10000	0	1310	1	16	1	1	15419	10111	10000	10100	15490	15494	15430	15548	15506
20204	15512	115	380	199	378	25275	15535	9598	25	20190	10214	10000	10100	10000	130518	725080	1	31	49	12347	15451	15487	12898	3	13043	20100	10200	10000	10200	10000	15451	155	1	1	20201	100	99	2070	100	10100	100	23557	23111	33269	0	24895	23324	10000	0	1310	1	16	1	1	15302	10102	10000	10100	15460	15528	15541	15390	15673

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5704

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0f	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15713	117	352	186	355	0	24695	15653	9797	25	20154	10151	10000	10010	10000	132113	728981	34	49	12599	15460	15659	13134	3	13168	20010	10020	10000	10020	10116	15852	146	1	1	20021	10	9	2335	10	10010	10	22873	22847	32933	0	24466	22742	10000	1271	2	15	2	2	15622	10110	10000	10010	15761	15699	15699	15728	15754
20024	15701	117	357	180	354	0	24584	15676	9686	25	20136	10136	10000	10010	10000	132952	732799	41	49	12620	15662	15653	12935	3	13255	20010	10020	10000	10020	10000	15729	153	1	1	20021	10	9	2412	10	10010	10	22948	22990	32748	0	24632	22878	10000	1270	2	16	2	2	15423	10150	10000	10010	15802	15621	15711	15659	15815
20024	15695	118	361	188	356	0	24646	15745	9680	25	20142	10139	10000	10010	10000	131891	739968	46	49	12545	15668	15607	13002	3	13099	20010	10020	10000	10020	10000	15686	147	1	1	20021	10	9	2381	10	10010	10	22895	22887	32797	0	24753	22868	10000	1270	2	16	2	3	15586	10117	10000	10010	15752	15685	15699	15745	15802
20024	15688	117	354	190	359	0	24492	15602	9758	25	20148	10136	10000	10010	10000	131815	733114	44	49	12547	15735	15831	12976	3	13290	20010	10020	10000	10020	10000	15669	151	1	1	20021	10	9	2347	10	10010	10	22831	22870	32768	0	24590	22985	10000	1270	2	16	2	2	15687	10165	10000	10010	15689	15697	15715	15630	15716
20024	15705	118	355	182	354	0	24735	15611	9712	25	20130	10163	10000	10010	10000	132299	737444	35	49	12634	15780	15693	13017	3	13212	20010	10020	10000	10020	10000	15617	153	1	1	20021	10	9	2535	10	10010	10	22966	22688	32820	0	24669	22861	10000	1270	2	16	2	2	15707	10138	10000	10010	15700	15631	15483	15769	15781
20024	15561	118	355	185	356	0	24556	15656	9715	25	20139	10121	10000	10010	10000	131159	737630	40	49	12624	15658	15739	13007	3	13186	20010	10020	10000	10020	10000	16054	158	1	1	20021	10	9	2353	10	10010	10	22909	23053	32924	0	24694	22863	10000	1270	2	16	2	2	15637	10120	10000	10010	15821	15606	15774	15762	15595
20024	15671	118	358	190	353	0	24559	15638	9802	25	20181	10154	10000	10010	10000	134583	735037	41	49	12655	15808	15633	12943	3	13298	20010	10020	10000	10020	10000	15613	176	1	1	20021	10	9	2408	10	10010	10	22858	23141	32935	0	24690	22959	10000	1270	2	16	2	2	15556	10135	10000	10010	15749	15744	15704	15846	15844
20024	15717	117	357	188	353	0	24580	15615	9786	25	20133	10121	10000	10010	10000	132524	735649	48	49	12545	15765	15755	12988	3	13274	20010	10020	10000	10020	10000	15655	153	1	1	20021	10	9	2395	10	10010	10	22856	22878	32965	0	24486	22771	10000	1270	2	16	2	2	15501	10138	10000	10010	15610	15727	15815	15712	15702
20024	15555	117	352	187	353	0	24399	15710	9707	25	20136	10145	10000	10010	10000	131684	733832	44	49	12603	15683	15659	12931	3	13145	20010	10020	10000	10020	10000	15643	147	1	1	20021	10	9	2448	10	10010	10	22901	22838	32844	0	24869	22935	10000	1270	2	16	2	2	15518	10123	10000	10010	15632	15649	15667	15631	15942
20024	15704	119	361	184	356	0	24614	15586	9716	25	20115	10112	10000	10010	10000	133577	734017	44	49	12564	15785	15693	13046	3	13113	20010	10020	10000	10020	10000	15766	160	1	1	20021	10	9	2405	10	10010	10	22933	22845	32770	0	24599	22897	10000	1270	2	16	2	3	15608	10174	10000	10010	15673	15841	15600	15767	15674

Test 3: throughput

Code:

  prfm plil2keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15548	116	311	156	309	24292	15510	9495	25	10100	100	10000	100	10006	500	727975	49	12475	15548	15437	14071	6	14262	10100	200	10000	200	10008	15444	12229	1	1	10201	100	99	2643	100	100	100	22552	22580	32575	0	0	0	24374	22573	10000	1	1	1	717	16	0	15341	10000	100	15386	15427	15521	15467	15480
10204	15576	120	311	155	312	24285	15387	9510	25	10100	100	10000	100	10000	500	721985	49	12372	15524	15507	13996	6	14205	10100	200	10016	200	10008	15503	12244	1	1	10201	100	99	2727	100	100	100	22437	22545	32602	0	0	0	24269	22512	10000	1	1	1	717	16	0	15426	10000	100	15509	15683	15563	15412	15532
10204	15441	115	310	157	306	24336	15458	9543	25	10100	100	10000	100	10004	500	720828	49	12514	15501	15418	14105	7	14380	10100	200	10016	200	10024	15382	12154	1	1	10201	100	99	2714	100	100	100	22509	22505	32537	0	0	0	24334	22525	10000	1	1	1	717	16	0	15359	10000	100	15560	15508	15487	15466	15622
10204	15508	116	308	157	309	24339	15524	9561	25	10100	100	10000	100	10000	500	722883	49	12436	15490	15486	13978	6	14160	10100	200	10016	200	10008	15437	12224	1	1	10201	100	99	2667	100	100	100	22513	22555	32441	0	0	0	24324	22505	10000	1	1	1	718	16	0	15358	10000	100	15462	15504	15488	15521	15451
10204	15462	115	311	159	309	24293	15571	9624	25	10100	100	10000	100	10000	500	728585	49	12417	15433	15486	14035	7	14268	10103	200	10016	200	10016	15463	12185	1	1	10201	100	99	2718	100	100	100	22490	22540	32557	0	0	0	24271	22564	10000	1	1	1	717	16	0	15437	10000	100	15558	15476	15481	15395	15461
10204	15433	117	312	155	315	24268	15479	9561	25	10100	100	10000	100	10000	500	722704	49	12327	15545	15498	14046	7	14222	10100	200	10008	200	10008	15467	12292	1	1	10201	100	99	2595	100	100	100	22541	22556	32555	0	0	0	24292	22531	10000	1	1	1	719	16	0	15334	10000	100	15447	15489	15543	15488	15477
10204	15493	116	315	153	311	24244	15467	9608	25	10100	100	10000	100	10000	500	724291	49	12482	15449	15521	14013	7	14156	10100	200	10359	200	10016	15429	12155	1	1	10201	100	99	2711	100	100	100	22555	22500	32483	0	0	0	24288	22470	10000	1	1	1	717	16	0	15365	10000	100	15466	15544	15522	15470	15595
10204	15579	116	307	157	313	24334	15479	9482	25	10100	100	10000	100	10004	500	727668	49	12441	15378	15496	13984	6	14132	10100	200	10008	200	10008	15390	12173	1	1	10201	100	99	2620	100	100	100	22553	22592	32565	0	0	0	24226	22602	10000	1	1	1	717	16	0	15369	10000	100	15463	15474	15477	15394	15454
10204	15533	116	311	157	311	24225	15543	9627	25	10100	100	10000	100	10000	500	723040	49	12421	15440	15439	14105	7	14283	10101	200	10008	200	10008	15509	12200	1	1	10201	100	99	2625	100	100	100	22578	22510	32501	0	0	0	24282	22622	10000	1	1	1	719	16	0	15417	10000	100	15477	15481	15462	15496	15430
10204	15564	115	315	159	308	24290	15456	9561	25	10100	100	10000	100	10000	500	724292	49	12353	15456	15389	14039	6	14169	10101	200	10008	200	10016	15502	12278	1	1	10201	100	99	2639	100	100	100	22510	22543	32547	0	0	0	24309	22532	10000	1	1	1	719	16	0	15552	10000	100	15490	15517	15539	15519	15510

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5459

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15479	116	334	173	334	0	24526	15444	9463	25	10010	10	10000	10	10000	50	723248	1	49	12396	15447	15463	14083	3	14263	10010	20	10000	20	10000	15445	15525	1	1	10021	10	9	2622	10	10	10	22773	22761	32760	0	0	24571	22677	10000	640	3	16	2	2	15415	10000	10	15497	15474	15441	15486	15447
10024	15441	115	336	167	334	0	24587	15429	9425	25	10010	10	10000	10	10000	50	721024	1	49	12427	15395	15514	14031	3	14164	10010	20	10000	20	10000	15550	15446	1	1	10021	10	9	2594	10	10	10	22755	22765	32688	0	0	24531	22813	10000	640	2	16	2	2	15342	10000	10	15490	15487	15520	15480	15463
10024	15402	115	336	171	337	0	24651	15519	9490	25	10010	10	10000	10	10000	50	721425	1	49	12315	15420	15484	13890	3	14220	10010	20	10000	20	10000	15469	15382	1	1	10021	10	9	2591	10	10	10	22897	22717	32687	0	0	24582	22797	10000	640	2	16	2	2	15383	10000	10	15432	15533	15456	15435	15424
10024	15538	116	336	176	336	0	24644	15358	9420	25	10010	10	10000	10	10000	50	720631	1	49	12420	15476	15482	14037	3	14208	10010	20	10000	20	10000	15391	15563	1	1	10021	10	9	2613	10	10	10	22743	22745	32794	0	0	24526	22718	10000	640	2	16	2	2	15327	10000	10	15480	15469	15461	15425	15446
10024	15440	115	333	168	333	0	24458	15519	9533	25	10010	10	10000	10	10000	50	726377	1	49	12361	15471	15389	14072	3	14168	10010	20	10000	20	10000	15323	15445	1	1	10021	10	9	2597	10	10	10	22728	22805	32763	0	0	24593	22882	10000	640	2	16	2	2	15315	10000	10	15499	15472	15514	15457	15404
10024	15519	116	337	170	329	0	24528	15409	9506	25	10010	10	10000	10	10000	50	720281	1	49	12340	15501	15347	14057	3	14282	10010	20	10000	20	10000	15404	15400	1	1	10021	10	9	2571	10	10	10	22788	22765	32745	0	0	24534	22756	10000	640	2	16	2	2	15238	10000	10	15417	15382	15550	15427	15421
10024	15427	115	336	169	334	0	24527	15414	9536	25	10010	10	10000	10	10000	50	722422	1	49	12384	15385	15478	13996	3	14177	10010	20	10000	20	10000	15467	15514	1	1	10021	10	9	2607	10	10	10	22699	22773	32744	0	0	24603	22765	10000	640	2	16	2	2	15608	10000	10	15484	15459	15423	15417	15471
10024	15464	116	337	174	338	0	24607	15411	9445	25	10010	10	10000	10	10000	50	723614	1	49	12334	15384	15501	13997	3	14160	10010	20	10000	20	10000	15452	15487	1	1	10021	10	9	2594	10	10	10	22732	22742	32735	0	0	24419	22715	10000	640	2	16	2	2	15360	10000	10	15466	15452	15425	15498	15398
10024	15432	115	335	175	340	0	24548	15460	9494	25	10010	10	10000	10	10000	50	726908	1	49	12405	15410	15468	14059	3	14105	10010	20	10000	20	10000	15442	15448	1	1	10021	10	9	2538	10	10	10	22799	22795	32712	0	0	24571	22731	10000	640	2	16	2	2	15377	10000	10	15394	15433	15372	15494	15434
10024	15482	116	337	174	332	0	24588	15423	9439	25	10010	10	10000	10	10000	50	725284	1	49	12397	15486	15550	14062	3	14163	10010	20	10000	20	10000	15423	15515	1	1	10021	10	9	2607	10	10	10	22718	22742	32840	0	0	24579	22726	10000	640	2	16	2	2	15353	10000	10	15448	15539	15458	15505	15434

PRFM (register, PLIL2KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations