Firestorm: LDRB (unsigned offset) measurements

Code:

  ldrb w0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	0	0	0	0	0	1	0	0	41	1	0	1	376	2	18	18	16	25	1000	1000	1000	15362	0	399	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1020	21	42	1057	1	0	0	59	1039	6	1	57	42	19	1	73	2	16	1	1	399	9	9	2	1000	400	399	400	400	400
1004	399	3	1	1	0	1	0	1	0	0	65	1	0	3	384	2	18	12	12	25	1000	1000	1000	14838	0	389	389	212	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1019	19	42	1019	1	0	0	59	1038	6	1	57	42	19	0	73	1	16	1	1	396	9	9	2	1000	395	390	390	390	390
1004	389	3	0	0	0	0	0	0	0	0	41	1	0	1	374	2	18	18	12	25	1000	1000	1000	14838	0	389	389	212	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	35	1035	6	1	35	39	0	0	73	1	16	1	1	388	6	9	2	1000	390	395	392	390	390
1004	389	3	0	0	0	0	0	1	0	0	41	0	0	2	379	2	18	18	12	25	1000	1000	1000	14838	0	389	389	212	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	1	1019	19	42	1057	1	0	0	59	1038	6	1	57	42	19	1	73	1	16	1	1	396	9	9	0	1000	391	390	392	390	390
1004	389	3	0	0	0	0	0	1	0	0	41	0	0	1	374	2	18	18	16	25	1000	1000	1000	15362	0	399	399	222	3	256	1000	1000	1000	399	81	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	35	1035	6	1	39	39	0	0	73	1	16	1	1	386	6	9	2	1000	400	400	400	400	400
1004	399	3	1	1	0	1	0	0	0	0	65	1	0	3	384	2	18	18	12	25	1000	1000	1000	14838	0	389	391	212	3	247	1000	1000	1000	391	71	1	1	1001	1000	1000	0	1000	0	39	1035	0	0	0	35	1035	6	1	35	43	0	0	73	1	16	1	1	386	6	9	2	1000	390	390	390	390	390
1004	389	3	0	0	0	0	0	0	0	0	41	1	0	1	374	1	18	18	15	25	1000	1000	1000	15334	0	398	399	221	3	257	1000	1000	1000	399	81	1	1	1001	1000	1000	1	1000	0	39	1035	0	0	0	35	1035	6	1	35	39	0	0	73	1	16	1	1	386	6	9	2	1000	390	390	390	390	390
1004	391	3	0	0	0	0	0	0	0	0	41	1	0	1	374	2	18	18	12	25	1000	1000	1000	14774	0	389	389	212	3	247	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1021	20	42	1057	0	0	2	59	1038	6	1	59	42	19	0	73	1	16	1	1	396	9	9	2	1000	390	390	390	390	390
1004	389	2	0	0	0	0	0	1	0	0	41	1	0	1	379	2	18	18	15	25	1000	1000	1000	15334	0	399	399	221	3	256	1000	1000	1000	399	82	1	1	1001	1000	1000	1	1000	0	39	1035	0	0	0	35	1035	6	1	35	39	0	0	73	1	16	1	1	386	6	9	2	1000	390	390	390	390	390
1004	389	3	0	0	0	0	0	1	0	0	41	1	0	1	374	2	18	18	16	25	1000	1000	1000	15315	0	398	398	221	3	257	1000	1000	1000	398	81	1	1	1001	1000	1000	1	1000	0	39	1035	0	0	0	35	1035	6	1	35	39	0	0	73	1	16	1	1	386	6	9	2	1000	400	400	400	401	400

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	0	1	1	1	1	0	0	1	1	70042	69788	59719	25	40108	30106	10002	30100	10000	616175	3342398	1	49	66974	70060	70060	64656	3	64960	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	0	0	0	1	10000	1	1	0	1	0	0	2615	6	71	5	5	69820	30006	10	10	0	10000	30100	70061	70042	70061	70058	70061
40204	70041	524	1	1	1	0	0	0	1	0	1	70042	69791	59716	25	40108	30106	10001	30100	10000	616095	3342686	1	49	66977	70060	70057	64637	3	64963	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	1	0	1	10000	1	1	1	1	1	0	2613	5	71	5	3	69823	30006	13	13	13	10000	30100	70058	70061	70042	70042	70061
40204	70060	524	1	1	1	0	0	0	1	1	2	70026	69791	59716	25	40112	30106	10002	30100	10000	616095	3341769	1	49	66961	70060	70041	64656	3	64963	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	0	10001	0	0	0	1	10000	1	1	0	1	2	0	2613	5	71	5	4	69804	30006	13	13	13	10000	30100	70061	70042	70042	70042	70058
40204	70060	525	1	1	1	0	0	0	2	1	1	70042	69702	59719	25	40104	30106	10002	30100	10000	616095	3342686	0	49	66980	70060	70041	64637	3	64963	40100	30200	10000	60200	10000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	0	1	1	1	10000	1	1	1	1	0	0	2613	5	71	5	5	69828	30003	0	13	13	10000	30100	70058	70061	70042	70058	70061
40204	70060	524	1	1	0	1	0	0	1	0	1	70045	69702	59719	25	40104	30103	10001	30100	10000	616078	3342542	1	49	66977	70057	70057	64656	3	64944	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	0	1	10000	0	1	1	1	0	0	2613	5	71	3	5	69820	30006	13	13	13	10000	30100	70058	70058	70061	70042	70042
40204	70060	525	1	1	1	0	0	0	2	0	1	70045	69791	59719	25	40104	30106	10002	30100	10000	616068	3342542	0	49	66980	70060	70057	64656	3	64963	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10001	0	0	1	1	10000	1	1	0	1	2	0	2615	3	71	3	4	69820	30003	13	0	13	10000	30100	70061	70042	70058	70058	70058
40204	70070	524	1	1	0	1	0	0	1	0	1	70045	69791	59716	25	40104	30106	10002	30100	10000	616095	3342686	0	49	66977	70060	70060	64656	3	64944	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10003	0	0	2	4	10000	0	1	0	1	0	0	2615	5	71	5	3	69804	30006	13	13	0	10000	30100	70042	70061	70061	70061	70058
40204	70060	524	1	1	1	1	0	0	1	1	2	70042	69702	59716	25	40108	30106	10002	30100	10000	616095	3342686	0	49	66980	70060	70060	64656	3	64963	40100	30200	10000	60200	10000	70060	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10002	0	0	1	1	10000	1	1	1	1	0	0	2613	6	71	5	3	69823	30006	13	0	10	10000	30100	70042	70061	70061	70061	70058
40204	70041	524	1	1	0	0	0	0	2	1	2	70045	69788	59701	25	40104	30106	10001	30100	10000	616095	3342686	0	49	66980	70060	70060	64656	3	64963	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	0	2	1	10000	1	1	1	1	0	0	2615	5	71	5	6	69804	30003	0	13	13	10000	30100	70061	70128	70057	70067	70061
40204	70060	525	1	1	1	0	0	0	1	0	1	70042	69791	59716	25	40108	30106	10002	30100	10000	616078	3342686	0	49	66977	70060	70057	64656	3	64944	40100	30200	10000	60200	10000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10002	0	0	1	1	10000	0	1	0	1	0	0	2613	5	71	5	5	69823	30006	10	10	10	10000	30100	70061	70061	70061	70058	70042

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	525	1	0	1	0	0	0	1	0	70042	69743	59710	25	40014	30013	10001	30010	10000	616991	3341470	0	49	66955	0	70035	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	2	71	1	1	69814	30003	10	10	10	10000	30010	70036	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	1	0	70036	69775	59710	25	40010	30013	10001	30010	10000	616991	3341470	1	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	2	69814	30003	10	10	10	10000	30010	70036	70036	70052	70052	70052
40024	70035	525	0	0	0	1	0	0	1	0	70062	69775	59710	25	40014	30013	10001	30010	10000	617068	3342254	0	49	66955	0	70051	70035	64653	3	64960	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69802	30006	0	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	6	0	70042	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69814	30006	10	11	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	1	0	0	0	1	1	70042	69777	59710	25	40014	30010	10001	30010	10000	617068	3342254	0	49	66971	0	70036	70038	64669	3	64960	40010	30020	10000	60020	10066	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69798	30006	10	10	10	10000	30010	70036	70036	70036	70036	70052
40024	70051	524	0	0	0	1	0	0	1	1	70042	69775	59710	25	40014	30013	10001	30010	10000	617068	3341470	0	49	66971	0	70051	70051	64653	3	64976	40010	30020	10000	60020	10000	70051	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69814	30006	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70035	525	0	0	0	0	0	0	1	1	70042	69775	59695	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	0	70051	70035	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	0	1	0	0	2520	1	71	1	1	69798	30006	10	10	10	10000	30010	70036	70052	70036	70052	70052
40024	70035	524	0	0	1	0	0	0	1	1	70042	69743	59695	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69798	30006	0	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	0	0	0	0	0	0	70042	69743	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	0	70051	70051	64669	3	64976	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	1	0	10000	1	1	0	0	2520	1	71	1	1	69814	30003	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	525	0	0	1	0	0	0	1	0	70042	69743	59710	25	40010	30013	10000	30010	10000	616991	3341470	0	49	66972	0	70051	70076	64669	3	65026	40010	30020	10000	60020	10000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	3	69814	30006	0	10	10	10000	30010	70036	70036	70036	70052	70052

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]
  ldrb w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26738	200	1	1	1	0	0	0	0	138	0	0	3	26699	0	7	0	20	25	80100	100	80000	100	80000	500	1166758	49	23657	26743	26861	16665	3	16694	80100	200	80000	200	80000	26714	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80018	20	43	80058	0	1	0	60	80000	6	0	19	43	19	1	0	5110	1	16	1	1	26733	0	0	13	0	80000	100	26715	26715	26737	26715	26737
80204	26714	200	1	1	1	0	1	0	0	67	0	0	3	26721	2	0	7	0	25	80100	100	80000	100	80000	500	1167316	49	23656	26746	26877	16667	3	16694	80100	200	80000	200	80000	26737	85	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	19	43	80019	1	0	1	61	80040	6	0	58	0	19	0	0	5110	1	16	1	1	26733	0	13	13	0	80000	100	26715	26715	26737	26715	26715
80204	26736	200	1	0	0	0	0	0	0	105	1	0	2	26725	0	7	0	1	25	80100	100	80000	100	80000	500	1167555	49	23634	26739	26740	16639	3	16694	80100	200	80000	200	80000	26714	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	0	80060	2	0	2	60	80000	6	1	58	43	19	1	0	5110	1	16	1	1	26733	0	0	0	0	80000	100	26716	26715	26737	26737	26737
80204	26736	201	1	1	1	1	0	0	0	54	1	0	2	26699	2	0	0	20	25	80100	100	80000	100	80000	500	1166519	49	23656	26722	26885	16667	3	16694	80100	200	80000	200	80224	26721	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	0	80019	0	0	1	61	80039	0	1	19	0	19	1	0	5110	1	16	1	1	26733	0	13	13	5	80000	100	26737	26737	26737	26737	26715
80204	26714	200	1	1	0	0	0	0	1	40	0	0	2	26721	0	7	7	19	25	80100	100	80000	100	80000	500	1167555	49	23656	26726	26823	16663	3	16694	80100	200	80000	200	80000	26736	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	0	80019	1	0	0	61	80040	0	1	59	43	19	1	0	5110	1	16	1	1	26734	0	13	13	0	80000	100	26738	26737	26737	26737	26737
80204	26736	200	1	1	1	0	0	0	0	66	0	0	1	26699	3	7	7	20	25	80100	100	80000	100	80000	500	1166758	49	23657	26721	26888	16663	3	16672	80100	200	80000	200	80000	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80021	20	43	80059	1	0	2	61	80040	6	0	58	43	19	1	0	5110	1	16	1	1	26711	0	0	13	5	80000	100	26737	26737	26737	26737	26715
80204	26736	200	1	0	1	1	1	1	0	67	1	0	1	26699	3	7	7	20	25	80100	100	80000	100	80000	500	1167316	49	23656	26719	26716	16667	3	16694	80100	200	80000	200	80000	26737	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	80058	1	0	0	60	80040	6	1	60	43	19	1	0	5110	1	16	1	1	26733	0	13	13	0	80000	100	26737	26715	26738	26738	26737
80204	26736	200	1	0	1	1	0	0	0	21	0	0	1	26722	3	7	7	0	25	80100	100	80000	100	80000	500	1166519	49	23635	26747	26823	16670	3	16694	80100	200	80000	200	80000	26736	64	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	18	0	80059	0	0	0	64	80039	0	1	59	43	19	1	0	5110	1	16	1	1	26711	0	13	13	0	80000	100	26737	26715	26737	26715	26715
80204	26714	200	1	1	1	1	0	0	0	67	0	0	3	26721	3	7	0	20	25	80100	100	80000	100	80000	500	1166519	49	23634	26745	26738	16667	3	16672	80100	200	80000	200	80000	26714	85	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	43	80058	1	0	1	21	80039	6	0	59	43	19	1	0	5110	1	16	1	1	26734	0	0	0	0	80000	100	26715	26737	26738	26826	26715
80204	26737	200	1	1	1	1	0	0	0	88	0	0	2	26699	2	9	7	19	25	80100	100	80000	100	80000	500	1169868	49	23656	26724	26743	16667	3	16672	80100	200	80000	200	80000	26714	64	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	21	0	80059	1	0	0	61	80000	6	1	59	43	19	0	0	5110	1	16	1	1	26711	0	13	13	5	80000	100	26715	26715	26737	26737	26738

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26724	200	1	0	0	41	0	1	26764	2	0	12	11	25	80010	10	80000	10	80000	50	1167605	49	23628	26722	26728	16667	3	16688	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80035	0	0	80000	6	1	0	0	5020	5	16	2	4	26719	6	6	0	80000	10	26709	26709	26723	26723	26709
80024	26722	200	0	1	0	0	1	2	26718	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	49	23628	26708	26722	16652	3	16688	80010	20	80000	20	80000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	80039	6	0	0	0	5020	4	16	4	2	26719	10	0	4	80000	10	26728	26729	26729	26709	26723
80024	26727	200	0	0	0	0	0	0	26707	0	18	18	12	25	80010	10	80000	10	80000	50	1168843	49	23628	26722	26722	16667	3	16688	80010	20	80000	20	80000	26728	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	80035	0	39	80035	6	1	35	39	5020	4	16	4	2	26705	10	10	0	80000	10	26709	26709	26728	26728	26729
80024	26728	200	0	0	1	45	1	1	26710	2	12	12	0	25	80010	10	80000	10	80000	50	1167605	49	23648	26728	26727	16672	3	16707	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80000	0	0	80000	6	1	35	43	5020	2	16	4	2	26719	0	0	0	80000	10	26728	26728	26728	26728	26709
80024	26708	200	0	0	0	0	1	0	26709	2	12	12	0	25	80010	10	80000	10	80000	50	1166750	49	23628	26708	26722	16667	3	16708	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80000	0	39	80039	6	1	0	43	5020	2	16	2	4	26725	6	6	0	80000	10	26709	26723	26723	26729	26729
80024	26727	200	0	1	0	45	0	1	26710	2	18	18	12	25	80010	10	80000	10	80000	50	1166886	49	23648	26728	26722	16667	3	16702	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	39	80035	6	1	35	43	5020	3	16	4	3	26719	10	0	0	80000	10	26728	26729	26729	26729	26728
80024	26727	200	0	1	0	45	1	2	26715	2	18	0	12	25	80010	10	80000	10	80000	50	1166886	49	23647	26708	26728	16672	3	16688	80010	20	80000	20	80000	26728	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80035	1	0	80035	6	1	0	0	5020	4	16	2	4	26705	6	0	0	80000	10	26709	26723	26723	26723	26723
80024	26708	200	0	0	0	45	0	0	26707	0	18	18	0	25	80010	10	80000	10	80000	50	1166886	49	23628	26728	26708	16652	3	16688	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80000	1	39	80000	6	1	35	39	5020	2	16	2	4	26705	6	6	0	80000	10	26723	26729	26709	26709	26723
80024	26708	200	0	0	0	45	0	2	26708	2	0	12	16	25	80010	10	80000	10	80000	50	1167545	49	23647	26728	26708	16672	3	16708	80010	20	80000	20	80000	26728	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80039	0	0	80039	0	1	35	43	5020	4	16	4	4	26705	10	0	0	80000	10	26709	26709	26723	26709	26729
80024	26728	200	0	0	0	0	0	0	26715	2	12	0	16	25	80010	10	80000	11	80000	50	1166750	49	23647	26728	26727	16652	3	16688	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80035	0	0	80000	6	1	35	39	5020	4	16	4	3	26705	0	6	2	80000	10	26723	26723	26723	26728	26709

LDRB (unsigned offset)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations