Firestorm: STUR (64-bit) measurements

Code:

  stur x0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	554	5	1	1	1	1	0	21	1	0	1	537	16	16	2	25	1000	1000	1000	22448	1	542	542	355	3	412	1000	1000	2000	553	554	1	1	1001	1000	1000	1014	15	44	0	0	1002	1	2	1002	16	44	14	2	73	1	16	1	1	549	1000	555	553	553	565	543
1004	542	4	0	0	0	0	0	3	1	0	0	527	16	16	1	25	1000	1000	1000	22448	1	542	542	356	3	401	1000	1000	2000	543	543	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	5	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	0	0	0	3	1	0	0	527	16	16	0	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	3	8	1002	2	42	0	0	73	1	16	1	1	539	1000	555	543	543	543	544
1004	543	4	0	0	0	0	0	3	1	0	0	527	16	16	0	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	0	0	0	3	1	0	0	527	16	16	1	25	1000	1000	1000	22472	1	543	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	1	0	1016	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	544
1004	543	4	0	0	0	0	0	3	1	0	0	527	16	16	5	25	1000	1000	1000	22448	1	542	542	356	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	554	4	0	0	0	0	9	3	1	0	0	527	16	16	1	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	1	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	0	0	0	3	1	0	0	527	16	16	1	25	1000	1000	1000	22448	1	543	542	355	3	401	1000	1000	2000	542	543	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	2	1002	2	42	0	0	73	1	16	1	1	551	1000	543	543	543	543	543
1004	542	4	0	0	0	0	0	3	1	0	0	527	16	16	1	25	1000	1000	1000	22448	1	542	542	355	3	412	1000	1000	2000	543	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	2	1002	2	42	0	0	73	1	16	1	1	540	1000	543	543	543	544	543
1004	542	3	0	0	0	0	0	3	1	0	0	527	16	16	1	25	1000	1000	1000	22472	1	542	554	355	3	400	1000	1000	2000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1016	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	544	543	543	543	544

Count: 8

Code:

  stur x0, [x6, #1]
  stur x0, [x6, #1]
  stur x0, [x6, #1]
  stur x0, [x6, #1]
  stur x0, [x6, #1]
  stur x0, [x6, #1]
  stur x0, [x6, #1]
  stur x0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40054	300	1	0	1	1	0	12	3	1	0	1	40048	16	0	4	25	80100	100	80000	100	80000	500	1840508	1	49	36972	0	40054	40064	29967	3	30005	80100	200	80000	200	160000	40054	32007	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	1	0	2	80002	2	42	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40041	40076	40044	40043
80204	40042	300	0	0	0	0	0	6	0	1	0	0	40025	16	16	3	25	80100	100	80000	100	80000	500	1839448	0	49	36960	0	40040	40042	29955	3	29998	80100	200	80000	200	160000	40043	31996	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	0	0	2	80002	0	42	0	0	0	5110	1	16	1	1	40037	80000	100	40043	40041	40043	40041	40043
80204	40040	300	0	0	0	0	0	0	0	0	0	0	40027	16	16	1	25	80100	100	80000	100	80000	500	1840004	0	49	36972	0	40054	40047	29967	3	30009	80100	200	80000	200	160000	40054	32016	1	1	80201	100	99	100	80000	100	80000	100	80014	15	44	0	1	80014	2	1	17	80002	16	44	14	0	0	5110	1	16	1	1	40044	80000	100	40055	40053	40053	40044	40043
80204	40042	300	0	0	0	0	0	0	3	1	0	0	40027	0	16	1	25	80100	100	80000	100	80000	500	1839448	0	49	36962	0	40042	40042	29955	3	30000	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	3	0	6	80000	0	0	0	0	0	5110	1	16	1	1	40037	80000	100	40043	40041	40044	40043	40041
80204	40042	300	0	0	0	0	1	6	192	1	0	0	40165	16	16	1	25	80100	100	80000	100	80000	500	1839472	0	49	36962	0	40326	40325	29955	16	30000	80208	200	80361	200	160238	40043	31996	3	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80002	1	0	3	80002	2	42	0	0	0	5110	1	16	1	1	40037	80000	100	40041	40041	40048	40041	40041
80204	40043	300	0	0	0	0	0	6	3	1	0	0	40028	16	16	0	25	80100	100	80000	100	80000	500	1839472	0	49	36963	0	40040	40043	29955	3	30012	80100	200	80000	200	160000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	42	0	0	80000	35	0	2	80002	2	42	0	0	0	5110	1	16	1	1	40051	80000	100	40041	40043	40055	40055	40055
80204	40054	300	1	0	1	1	0	0	21	0	0	1	40039	0	16	0	25	80100	100	80000	100	80000	500	1839448	1	49	36960	0	40042	40042	29955	3	30000	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	44	0	0	80002	28	0	12	80002	2	0	0	0	0	5110	1	16	1	1	40039	80000	100	40043	40043	40048	40050	40052
80204	40054	300	1	1	0	1	0	0	18	1	0	1	40032	16	16	2	25	80100	100	80000	100	80000	500	1839448	1	49	36960	0	40042	40040	29956	3	30001	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	44	0	0	80002	0	0	2	80002	2	42	0	0	0	5110	1	16	1	1	40040	80000	100	40043	40044	40064	40058	40056
80204	40047	300	1	1	0	0	0	0	14	0	0	1	40039	0	16	1	25	80100	100	80000	100	80000	500	1839448	0	49	36962	0	40054	40042	29953	3	30000	80100	200	80000	200	160000	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	44	0	0	80002	2	0	2	80002	2	42	0	0	0	5110	1	16	1	1	40039	80000	100	40041	40043	40055	40055	40055
80204	40054	300	1	0	0	1	0	0	17	0	0	1	40039	16	16	1	25	80100	100	80000	100	80000	500	1839692	1	49	36974	0	40054	40054	29960	3	30012	80100	200	80000	200	160000	40054	32007	1	1	80201	100	99	100	80000	100	80000	100	80015	15	42	0	0	80002	2	0	14	80002	2	42	0	0	0	5110	1	16	1	1	40040	80000	100	40041	40043	40055	40044	40055

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	cf	d0	d2	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40042	300	0	3	0	3	40027	16	0	0	25	80010	10	80000	10	80000	50	1839352	0	1	49	36962	40042	40042	29977	3	30022	80010	20	80000	20	160000	40050	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	36	0	0	80002	1	5	80002	2	34	0	5026	0	0	2	16	0	0	0	4	4	3	40049	0	80000	10	40043	40043	40041	40044	40043
80024	40050	300	0	3	0	3	40035	0	16	0	25	80190	10	80000	10	80000	50	1839808	0	1	49	36962	40040	40123	29977	3	30029	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	2	34	29	0	80002	0	2	80002	2	34	0	5026	4	0	6	16	0	0	0	4	2	3	40047	0	80000	10	40052	40043	40041	40041	40041
80024	40049	299	0	0	0	3	40027	0	16	0	25	80010	10	80000	10	80000	50	1839808	0	1	49	36962	40051	40040	29975	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	4	2	80000	0	34	0	5026	4	0	4	16	0	0	0	4	2	3	40037	0	80000	10	40043	40050	40043	40041	40043
80024	40050	300	0	3	1	3	40036	16	16	0	25	80010	10	80000	10	80000	50	1839352	0	1	49	36962	40042	40042	29975	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	2	2	80002	2	34	0	5026	4	0	4	16	0	0	0	4	2	3	40037	0	80000	10	40043	40052	40043	40059	40041
80024	40042	300	0	9	0	3	40027	0	16	0	25	80010	10	80000	10	80000	50	1839424	0	1	49	36962	40050	40042	29984	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	1	2	80002	2	34	0	5026	4	0	4	16	0	0	0	4	2	3	40039	0	80000	10	40051	40043	40043	40043	40043
80024	40042	299	0	3	0	3	40025	16	0	0	25	80010	10	80000	10	80000	50	1839760	0	0	49	36962	40051	40042	29985	3	30020	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	6	2	80002	2	34	0	5057	4	0	4	16	0	1	0	6	3	3	40037	0	80000	10	40043	40041	40043	40044	40043
80024	40040	300	0	6	1	3	40025	0	16	0	25	80190	10	80000	10	80000	50	1839424	0	0	49	36962	40042	40040	29977	3	30022	80010	20	80000	20	160000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	36	0	0	80002	0	0	80002	2	0	0	5026	4	0	2	16	0	0	0	4	2	3	40048	0	80000	10	40043	40043	40043	40044	40043
80024	40040	299	0	3	0	3	40027	16	16	0	25	80010	10	80000	10	80000	50	1839424	0	0	49	36962	40040	40040	29977	3	30022	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	3	2	80002	2	34	0	5026	4	0	4	16	0	0	0	4	2	3	40039	0	80000	10	40051	40043	40052	40049	40041
80024	40042	300	0	0	0	3	40027	0	16	0	25	80010	10	80000	10	80000	50	1839856	0	1	49	36962	40040	40051	29975	3	30020	80010	20	80000	20	160000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	2	2	80002	2	34	0	5026	4	0	4	16	0	0	0	2	4	3	40047	0	80000	10	40043	40043	40043	40041	40043
80024	40042	300	0	0	1	3	40025	16	0	0	25	80010	10	80000	10	80000	50	1839424	0	0	49	36962	40051	40042	29985	3	30022	80010	20	80000	20	160000	40051	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	34	0	0	80002	3	2	80002	2	34	0	5026	4	0	4	16	0	0	0	2	4	3	40037	0	80000	10	40041	40050	40043	40051	40043

STUR (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations