Firestorm: PRFM (register, PSTL3STRM) measurements

Code:

  prfm pstl3strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1583	12	29	15	30	2376	1600	874	25	1000	1000	1000	70689	1594	1607	1302	3	1480	1000	1000	1000	1595	1592	1	1	1001	248	2221	2215	3224	0	2397	2198	1000	73	1	16	1	1	1494	1000	1608	1620	1581	1594	1616
1004	1623	12	28	15	30	2363	1606	892	25	1000	1000	1000	69713	1607	1619	1302	3	1487	1000	1000	1000	1581	1567	1	1	1001	251	2227	2230	3226	0	2383	2224	1000	73	1	16	1	1	1505	1000	1581	1572	1621	1603	1618
1004	1571	12	29	16	30	2390	1555	884	25	1000	1000	1000	69492	1594	1562	1301	3	1472	1000	1000	1000	1584	1587	1	1	1001	251	2219	2218	3214	0	2385	2211	1000	73	1	16	1	1	1502	1000	1589	1592	1618	1618	1594
1004	1627	12	30	15	30	2421	1554	883	25	1000	1000	1000	70512	1585	1627	1315	3	1480	1000	1000	1000	1583	1589	1	1	1001	232	2249	2226	3216	0	2371	2237	1000	73	1	16	1	1	1502	1000	1562	1604	1588	1608	1628
1004	1621	12	30	15	30	2370	1608	872	25	1000	1000	1000	70557	1589	1605	1313	3	1473	1000	1000	1000	1584	1578	1	1	1001	234	2221	2216	3196	0	2394	2220	1000	73	1	16	1	1	1519	1000	1620	1637	1598	1562	1613
1004	1612	12	30	15	30	2360	1608	927	25	1000	1000	1000	69751	1597	1612	1318	3	1476	1000	1000	1000	1585	1588	1	1	1001	248	2220	2209	3219	0	2401	2212	1000	73	1	16	1	1	1514	1000	1632	1578	1615	1637	1637
1004	1605	12	29	15	30	2390	1592	889	25	1000	1000	1000	70168	1571	1590	1305	3	1489	1000	1000	1000	1581	1587	1	1	1001	243	2207	2242	3225	0	2451	2237	1000	73	1	16	1	1	1500	1000	1618	1605	1592	1621	1614
1004	1654	12	30	15	30	2371	1620	929	25	1000	1000	1000	69537	1600	1588	1323	3	1472	1000	1000	1000	1610	1596	1	1	1001	224	2239	2234	3225	0	2392	2232	1000	73	1	16	1	1	1510	1000	1609	1580	1633	1628	1627
1004	1606	11	29	16	30	2381	1575	866	25	1000	1000	1000	69015	1580	1630	1332	3	1448	1000	1000	1000	1617	1581	1	1	1001	235	2218	2229	3208	0	2374	2219	1000	73	1	16	1	1	1488	1000	1588	1615	1617	1625	1624
1004	1619	12	30	15	30	2378	1591	886	25	1000	1000	1000	69390	1561	1598	1327	3	1477	1000	1000	1000	1588	1594	1	1	1001	274	2249	2206	3226	0	2404	2201	1000	73	1	16	1	1	1507	1000	1605	1618	1618	1629	1596

Test 2: throughput

Code:

  prfm pstl3strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5776

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15819	118	335	181	338	24213	15762	9817	25	20220	10244	10000	10100	10000	131217	737059	0	40	49	12577	15786	15769	13041	3	13112	20100	10200	10000	10200	10000	15669	155	1	1	20201	100	99	2547	100	10100	100	22662	22696	32765	0	2	24443	22619	10000	1310	2	16	1	1	15620	10117	10000	10100	15850	15791	15770	15623	15719
20204	15839	118	335	184	336	24354	15830	9829	25	20217	10217	10000	10100	10000	132266	737179	0	42	49	12857	15695	15678	13050	3	13238	20100	10200	10000	10200	10000	15759	156	1	1	20201	100	99	2430	100	10100	100	22540	22676	32775	0	24	24537	22578	10000	1310	1	17	1	1	15603	10093	10000	10100	15775	15781	15737	15874	15913
20204	15846	118	337	180	334	24497	15858	9793	25	20187	10205	10000	10100	10000	133966	738815	0	39	49	12728	15738	15837	13065	3	13170	20100	10200	10000	10200	10000	15730	163	1	1	20201	100	99	2534	100	10100	100	22583	22682	32569	0	0	24459	22700	10000	1310	1	16	1	1	15673	10138	10000	10100	15703	15735	15838	15804	15704
20204	15646	118	334	183	334	24486	15686	9828	25	20217	10223	10000	10100	10000	131671	736427	0	41	49	12694	15830	15689	13006	3	13183	20100	10200	10000	10332	10000	15708	155	1	1	20201	100	99	2521	100	10100	100	22748	22754	32565	0	1	24364	22679	10000	1310	1	16	1	1	15621	10111	10000	10100	15749	15711	15870	15818	15845
20204	15800	117	342	186	338	24316	15806	9773	25	20187	10196	10000	10100	10000	131950	736586	0	30	49	12778	15784	15672	12958	3	13059	20100	10200	10000	10200	10000	15681	155	1	1	20201	100	99	2415	100	10100	100	22821	22523	32704	0	0	24238	22596	10000	1310	1	16	1	1	15638	10117	10000	10100	15886	15627	15804	15938	15807
20204	15803	118	344	181	335	24443	15751	9842	25	20181	10208	10000	10100	10000	131072	739793	0	43	49	12712	15724	15906	13033	3	13275	20100	10200	10000	10200	10000	15757	154	1	1	20201	100	99	2359	100	10100	100	22753	22661	32681	0	0	24378	22618	10000	1310	1	16	1	1	15522	10111	10000	10100	15761	15896	15782	15799	15673
20204	15922	118	337	183	337	24248	15683	9806	25	20196	10238	10000	10100	10000	132859	738360	0	30	49	12724	15868	15739	12997	3	13257	20100	10200	10000	10200	10000	15754	155	1	1	20201	100	99	2523	100	10100	100	22667	22522	32688	0	6	24303	22700	10000	1310	1	16	1	1	15558	10102	10000	10100	15643	15848	15765	15665	15729
20204	15687	118	340	180	346	24279	15897	9784	25	20178	10223	10000	10100	10000	133578	736865	0	38	49	12801	15765	15759	13004	3	13150	20100	10200	10000	10200	10000	15821	155	1	1	20201	100	99	2496	100	10100	100	22803	22808	32704	0	0	24386	22642	10000	1310	1	16	1	1	15641	10117	10000	10100	15804	15778	15835	15813	15763
20204	15754	118	335	180	336	24233	15742	9771	25	20215	10196	10000	10100	10000	132166	736594	0	43	49	12882	15787	15739	13013	3	13128	20100	10200	10000	10200	10000	15836	155	1	1	20201	100	99	2548	100	10100	100	22776	22867	32709	0	0	24353	22610	10000	1310	1	17	1	1	15695	10081	10000	10100	15797	15793	15740	15735	15763
20204	15796	119	333	186	339	24386	15702	9830	25	20208	10214	10000	10100	10000	132427	736818	0	37	49	12686	15762	15678	13087	3	13118	20100	10200	10000	10200	10000	15639	155	1	1	20201	100	99	2564	100	10100	100	22701	22718	32697	0	0	24141	22598	10000	1310	1	16	1	1	15688	10102	10000	10100	15882	15775	15718	15737	15610

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5577

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15479	117	1	376	194	1	374	24875	1	15587	9658	25	20142	10169	10000	10010	10000	128726	728634	0	1	48	49	12548	15605	15738	12991	3	13107	20010	10020	10000	10020	10000	15531	154	1	1	20021	10	9	2253	10	10010	10	23116	23273	33115	0	0	24855	23188	10000	0	1272	0	0	2	16	2	3	15457	10111	0	10000	10010	15713	15709	15614	15582	15646
20024	15579	117	1	378	194	1	373	24940	1	15546	9565	25	20154	10127	10000	10010	10000	129894	730270	0	1	45	49	12534	15545	15608	12956	3	13105	20010	10020	10000	10020	10000	15473	163	1	1	20021	10	9	2197	10	10010	10	23031	23255	33168	0	0	24854	23101	10000	0	1272	0	0	3	16	3	3	15424	10105	0	10000	10010	15480	15641	15543	15559	15613
20024	15600	117	1	367	194	1	378	25091	1	15525	9561	25	20181	10181	10000	10010	10000	130098	727853	0	1	47	49	12538	15700	15567	12984	3	13011	20010	10020	10000	10020	10000	15588	163	1	1	20021	10	9	2211	10	10010	10	23159	23034	33230	0	0	24624	23051	10000	0	1272	0	0	3	16	2	3	15540	10126	0	10000	10010	15621	15571	15501	15487	15516
20024	15445	118	1	374	194	1	376	24817	1	15472	9744	25	20154	10187	10000	10010	10000	131361	733423	0	1	48	49	12498	15530	15460	13069	3	13010	20010	10020	10000	10020	10000	15570	164	1	1	20021	10	9	2085	10	10010	10	23036	23264	33197	0	0	24938	23035	10000	0	1272	0	0	3	16	3	2	15442	10147	0	10000	10010	15584	15477	15582	15604	15604
20024	15630	118	1	379	199	1	369	24866	1	15564	9641	25	20151	10127	10000	10010	10000	130144	736888	0	1	39	49	12564	15575	15497	12772	3	13053	20010	10020	10000	10020	10000	15565	154	1	1	20021	10	9	2161	10	10010	10	22933	23309	33122	0	4	24804	23062	10000	0	1272	0	0	3	16	3	2	15378	10120	0	10000	10010	15634	15576	15532	15672	15582
20024	15537	117	1	376	195	1	378	24740	1	15589	9582	25	20154	10115	10000	10010	10000	135855	726575	0	1	46	49	12547	15559	15535	12959	3	13205	20010	10020	10000	10020	10000	15468	155	1	1	20021	10	9	2130	10	10010	10	23200	23014	33146	6	0	24822	23034	10000	0	1272	0	0	3	15	2	3	15369	10093	0	10000	10010	15531	15494	15621	15669	15638
20024	15518	116	1	375	202	1	367	24920	1	15530	9606	25	20157	10157	10000	10010	10000	130260	729003	0	1	37	49	12468	15690	15576	12945	3	13034	20010	10020	10000	10020	10000	15593	154	1	1	20021	10	9	2181	10	10010	10	22979	23211	33320	0	0	24873	22981	10000	0	1272	0	0	3	16	2	3	15577	10138	16	10000	10010	15575	15659	15591	15434	15451
20024	15501	116	1	378	198	1	375	25005	1	15620	9642	25	20103	10133	10000	10010	10000	129668	729638	0	1	48	49	12477	15577	15668	12981	3	12937	20010	10020	10000	10020	10000	15540	154	1	1	20021	10	9	2224	10	10010	10	23162	23111	33126	0	0	24931	23054	10000	0	1272	0	0	2	16	4	3	15421	10126	0	10000	10010	15676	15751	15492	15491	15611
20024	15601	117	1	371	201	1	377	24836	1	15653	9639	25	20133	10172	10000	10010	10000	131274	729702	0	1	40	49	12576	15635	15495	12990	3	13049	20010	10020	10000	10020	10000	15630	157	1	1	20021	10	9	2059	10	10010	10	23084	23057	33142	0	0	24741	23213	10000	0	1272	0	0	3	16	4	3	15510	10123	0	10000	10010	15608	15557	15496	15501	15529
20024	15587	117	1	373	190	1	372	24831	1	15538	9699	25	20151	10181	10000	10010	10000	130635	728785	0	1	45	49	12437	15694	15602	12831	3	13096	20010	10020	10000	10020	10000	15662	157	1	1	20021	10	9	2136	10	10010	10	23143	23115	33084	0	0	24840	23156	10000	0	1273	0	0	3	16	3	3	15392	10132	0	10000	10010	15597	15570	15554	15565	15601

Test 3: throughput

Code:

  prfm pstl3strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5393

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15380	115	349	192	350	0	0	24641	15386	9412	25	10100	100	10000	100	10000	500	723089	1	49	12379	15394	15486	13836	7	14127	10100	200	10008	200	10024	15373	12131	1	1	10201	100	99	2538	100	100	100	22955	22922	32916	1	24679	22880	10000	1	1	1	718	16	0	15311	0	10000	100	15365	15309	15400	15430	15372
10204	15277	119	348	194	351	4	3	24726	15437	9396	25	10100	100	10000	100	10003	500	717481	1	49	12278	15365	15484	13961	6	14074	10100	200	10016	200	10016	15385	12132	1	1	10201	100	99	2503	100	100	100	22935	22838	32868	1	24683	22958	10000	1	1	1	719	16	0	15330	0	10000	100	15491	15534	15418	15411	15394
10204	15386	115	344	180	356	0	0	24775	15277	9495	25	10100	100	10000	100	10001	500	718650	0	49	12257	15413	15330	13915	6	14099	10101	200	10016	200	10016	15439	12213	1	1	10201	100	99	2518	100	100	100	22909	22898	32875	0	24721	22824	10000	1	1	1	717	16	0	15287	20	10000	100	15451	15359	15421	15422	15430
10204	15474	115	346	190	350	0	0	24793	15380	9395	25	10100	100	10000	100	10001	500	723770	0	49	12266	15421	15457	13977	6	14050	10100	200	10016	200	10024	15449	12211	1	1	10201	100	99	2425	100	100	100	22808	22979	32932	1	24731	22876	10000	1	1	1	718	16	0	15259	0	10000	100	15355	15479	15375	15374	15382
10204	15534	115	344	186	355	0	0	24646	15426	9472	25	10100	100	10000	100	10000	500	720761	0	49	12407	15352	15364	14017	6	14134	10100	200	10016	200	10016	15337	12240	1	1	10201	100	99	2480	100	100	100	22936	22840	32971	1	24601	22856	10000	1	1	1	718	16	0	15360	0	10000	100	15402	15307	15316	15477	15380
10204	15413	116	344	181	357	0	0	24637	15407	9453	25	10100	100	10000	100	10000	500	720538	0	49	12323	15396	15345	13883	6	14097	10100	200	10016	200	10016	15338	12104	1	1	10201	100	99	2467	100	100	100	22891	22997	33182	1	24759	22862	10000	1	1	1	719	16	0	15268	0	10000	100	15440	15446	15397	15408	15406
10204	15401	117	347	182	346	0	0	24710	15392	9382	25	10100	100	10000	100	10008	500	717859	0	49	12355	15463	15345	13985	6	14071	10108	200	10008	200	10016	15360	12192	1	1	10201	100	99	2498	100	100	100	22859	22955	32890	0	24701	22925	10000	1	1	1	719	16	0	15333	0	10000	100	15448	15374	15394	15321	15374
10204	15359	116	343	182	356	0	0	24884	15452	9479	25	10100	100	10000	100	10000	500	720579	0	49	12218	15412	15433	13994	6	14154	10100	200	10016	200	10008	15371	12162	1	1	10201	100	99	2461	100	100	100	22957	22961	32840	0	24645	22800	10000	1	1	1	717	16	0	15330	0	10000	100	15254	15395	15487	15358	15360
10204	15396	115	352	179	352	0	0	24717	15311	9430	25	10100	100	10000	100	10000	500	721122	0	49	12282	15394	15487	13953	7	14015	10100	200	10016	200	10008	15260	12216	1	1	10201	100	99	2386	100	100	100	22977	22850	32920	28	24716	22901	10000	1	1	1	717	16	0	15291	0	10000	100	15382	15411	15347	15413	15455
10204	15350	115	346	183	349	0	0	24712	15311	9413	25	10100	100	10000	100	10000	500	721538	0	49	12316	15353	15451	13992	6	14130	10100	200	10008	200	10008	15396	12125	1	1	10201	100	99	2445	100	100	100	22909	22867	32941	1	24713	22927	10000	1	1	1	718	16	0	15319	0	10000	100	15393	15411	15353	15430	15356

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5584

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15587	117	293	147	290	24086	15533	9658	25	10010	10	10000	10	10000	50	728963	1	49	12465	15556	15646	14144	3	14326	10010	20	10000	20	10000	15494	15426	1	1	10021	10	9	2700	10	10	10	22216	22226	32232	0	0	0	23987	22337	10000	640	2	16	2	2	15417	10000	10	15596	15572	15661	15578	15505
10024	15587	116	291	146	294	24008	15568	9581	25	10010	10	10000	10	10000	50	730758	1	49	12542	15575	15579	14105	3	14280	10010	20	10000	20	10000	15569	15517	1	1	10021	10	9	2678	10	10	10	22220	22353	32228	0	0	0	24020	22354	10000	640	2	16	2	2	15410	10000	10	15592	15525	15582	15550	15596
10024	15593	116	297	145	295	23966	15600	9679	25	10010	10	10000	10	10000	50	728389	1	49	12457	15566	15611	14173	3	14244	10010	20	10000	20	10000	15600	15494	1	1	10021	10	9	2730	10	10	10	22251	22298	32339	0	0	0	23929	22308	10000	640	2	16	2	2	15472	10000	10	15579	15659	15570	15556	15552
10024	15495	116	296	149	296	24011	15622	9611	25	10010	10	10000	10	10000	50	727354	0	49	12473	15589	15587	14168	3	14336	10010	20	10000	20	10000	15535	15476	1	1	10021	10	9	2696	10	10	10	22315	22209	32275	0	0	0	23966	22270	10000	640	2	16	2	2	15374	10000	10	15477	15577	15627	15611	15457
10024	15605	116	297	147	297	24064	15628	9611	25	10010	10	10000	10	10000	50	728382	1	49	12394	15620	15629	14143	3	14307	10010	20	10000	20	10000	15507	15536	1	1	10021	10	9	2710	10	10	10	22346	22268	32282	0	1	0	24013	22313	10000	640	2	16	2	2	15377	10000	10	15576	15576	15495	15688	15617
10024	15622	117	296	148	294	24033	15589	9659	25	10010	10	10000	10	10000	50	729216	0	49	12469	15551	15521	14187	3	14226	10010	20	10000	20	10000	15552	15550	1	1	10021	10	9	2707	10	10	10	22254	22216	32336	0	33	0	23931	22267	10000	640	2	16	2	2	15580	10000	10	15607	15760	15551	15593	15549
10024	15584	116	294	146	298	24027	15515	9565	25	10010	10	10000	10	10000	50	730745	0	49	12535	15578	15549	14179	3	14329	10010	20	10000	20	10000	15451	15563	1	1	10021	10	9	2651	10	10	10	22341	22222	32288	0	32	0	24014	22273	10000	640	2	16	2	2	15458	10000	10	15603	15552	15497	15604	15642
10024	15599	117	291	148	296	23898	15615	9506	25	10010	10	10000	10	10000	50	729882	0	49	12466	15593	15644	14099	3	14293	10010	20	10000	20	10000	15508	15511	1	1	10021	10	9	2637	10	10	10	22263	22366	32292	0	40	0	24047	22290	10000	640	2	16	2	2	15402	10000	10	15523	15579	15638	15486	15611
10024	15571	117	299	148	295	24010	15562	9630	25	10010	10	10000	10	10000	50	723144	0	49	12438	15593	15586	14094	3	14329	10010	20	10000	20	10000	15564	15579	1	1	10021	10	9	2626	10	10	10	22256	22301	32293	0	0	0	24062	22246	10000	640	2	16	2	2	15374	10000	10	15592	15557	15613	15643	15643
10024	15592	117	294	147	299	23880	15553	9563	25	10010	10	10000	10	10000	50	731233	0	49	12394	15581	15564	14178	3	14192	10010	20	10000	20	10000	15402	15430	1	1	10021	10	9	2729	10	10	10	22364	22266	32302	0	0	0	24008	22324	10000	640	2	16	2	2	15471	10000	10	15531	15533	15614	15534	15570

PRFM (register, PSTL3STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations