Firestorm: LDRSW (post-index) measurements

Code:

  ldrsw x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	20	22	23	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1041	8	1	0	1	0	0	0	0	72	0	21	0	0	0	0	4	0	1025	9	2	15	8	16	25	2000	1000	1000	1000	1000	52828	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1016	0	2	46	1027	4	0	24	6	27	1038	27	2	44	48	0	0	75	6	16	6	6	1037	1000	15	15	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	0	0	41	0	16	0	0	0	0	4	0	1025	11	3	8	4	26	25	2000	1000	1000	1000	1000	52832	45823	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1026	0	1	58	1046	2	0	28	12	29	1036	47	4	41	72	0	0	75	6	16	7	7	1037	1000	28	23	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	0	0	76	0	20	0	0	0	0	5	0	1025	13	5	14	7	14	25	2000	1000	1000	1000	1000	52796	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1028	0	1	47	1065	4	1	12	0	25	1039	31	2	28	24	13	0	75	6	16	7	7	1037	1000	22	35	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	1	0	66	0	26	0	0	0	0	5	0	1025	0	4	14	10	19	25	2000	1000	1000	1000	1000	52816	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	6	0	54	1031	0	0	12	6	31	1032	28	4	29	48	0	0	75	7	16	6	6	1037	1000	11	9	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	0	0	51	0	12	0	0	0	0	7	0	1025	0	5	12	4	16	25	2000	1000	1000	1000	1000	52828	45828	1	1040	1040	700	3	777	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	2	1016	6	2	39	1046	0	0	0	0	39	1040	39	4	39	80	0	0	75	7	16	6	6	1037	1000	22	15	1000	1000	1041	1041	1045	1041	1055
2004	1040	8	1	0	1	0	0	0	0	39	0	0	0	0	0	0	6	0	1025	0	1	2	12	20	25	2000	1000	1000	1000	1000	52840	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	6	1	87	1052	9	1	12	20	32	1038	20	4	25	48	0	0	75	6	16	7	7	1037	1000	32	21	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	0	0	57	0	28	0	0	0	0	6	0	1025	8	6	12	12	18	25	2000	1000	1000	1000	1000	52820	46904	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	0	0	69	1051	5	0	16	0	13	1013	23	2	11	40	0	0	75	7	16	7	7	1037	1000	22	13	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	0	0	84	0	28	0	0	0	0	8	0	1025	0	5	14	16	20	25	2000	1000	1000	1000	1000	52840	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1012	6	0	61	1028	7	2	0	0	45	1036	21	2	33	40	0	0	75	7	16	6	6	1037	1000	26	15	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	0	0	74	0	20	1	0	0	0	5	12	1036	17	6	12	14	22	25	2000	1000	1000	1000	1000	52824	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1026	0	0	75	1039	3	0	14	18	27	1045	30	3	29	40	0	0	75	6	16	7	7	1025	1000	29	23	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	1	0	0	0	0	80	0	0	0	0	0	0	5	0	1025	0	3	6	4	19	25	2000	1000	1000	1000	1000	52808	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	0	1020	0	0	54	1029	0	0	0	0	27	1043	29	3	23	64	0	0	75	6	16	6	6	1037	1000	28	19	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1746

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	20	22	24	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72184	538	1	0	0	0	0	0	0	717	0	848	1	0	712	2	100	71831	813	2	1	71337	25	50785	40616	10127	40100	10000	613398	2718643	49	68511	72035	71896	65069	3	65268	50100	40200	10000	70200	10000	71834	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10902	1	145	495	10618	266	8	883	42	24	10935	132	2	118	1	0	8	2610	3	51	2	2	71565	40464	866	888	860	10000	40100	71619	71637	71773	71605	71850
50204	71576	537	1	0	0	0	0	0	0	598	0	864	1	0	696	1	136	71736	774	1	1	71480	25	50730	40608	10127	40100	10000	676080	2717582	49	68838	72027	71934	65252	3	65439	50100	40200	10000	70200	10000	71934	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10910	2	158	466	10642	257	15	905	48	23	10919	118	3	113	1	0	9	2610	2	51	2	2	71766	40536	856	904	890	10000	40100	71698	71674	71834	71673	71873
50204	71480	537	1	0	0	0	0	0	0	568	0	790	1	0	736	2	116	71892	786	1	1	71261	25	50790	40648	10130	40100	10000	675946	2709355	49	68549	71884	71647	65217	3	65475	50100	40200	10000	70200	10000	71668	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10877	1	147	480	10650	265	12	929	66	26	10941	130	2	142	1	0	3	2610	2	51	2	2	71596	40536	942	928	890	10000	40100	71674	71844	71615	71812	71763
50204	71875	538	1	0	0	0	0	1	0	552	0	813	1	0	680	1	100	71759	800	1	0	71464	25	50735	40652	10129	40261	10000	672999	2713538	49	68726	72005	71733	65265	3	65448	50100	40200	10000	70200	10000	71768	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10930	2	149	476	10661	260	10	948	46	36	10841	129	3	145	1	0	5	2610	2	51	2	2	71573	40516	998	916	890	10000	40100	71784	71941	71640	71993	71444
50204	71943	539	1	0	0	0	0	0	0	497	0	830	1	0	680	1	100	71658	784	1	1	71448	25	50755	40644	10126	40100	10000	676737	2710472	49	68751	71811	71670	65230	3	65356	50100	40200	10000	70200	10000	71727	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10893	1	153	511	10661	253	7	927	52	24	10905	126	3	121	1	0	8	2610	2	51	2	4	71536	40544	928	912	884	10000	40100	71771	71693	71773	71901	71685
50204	71705	538	1	0	0	0	0	0	0	538	0	809	1	0	784	1	132	71650	791	1	1	71431	25	50805	40608	10134	40100	10000	677095	2710993	49	68697	71904	71847	65220	3	65268	50100	40200	10000	70200	10000	71772	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10927	1	146	475	10626	270	9	895	48	32	10884	120	2	131	1	0	3	2610	2	51	2	2	71493	40504	880	930	908	10000	40100	71723	71672	71571	71618	71779
50204	71715	539	1	0	0	0	0	0	0	531	0	826	1	0	696	1	132	71681	815	1	1	71621	25	50710	40664	10126	40100	10000	676449	2716425	49	68656	71973	71819	65117	3	65424	50100	40200	10000	70200	10000	71797	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10857	1	154	462	10679	262	12	930	74	21	10900	110	2	128	1	0	6	2610	2	51	2	2	71569	40492	942	908	998	10000	40100	71733	71577	71891	71686	71795
50204	71820	537	1	0	0	1	0	0	0	561	0	809	1	0	736	1	112	71882	786	1	1	71336	25	50805	40616	10123	40100	10000	676650	2715377	49	68512	71923	71956	65332	3	65487	50100	40200	10000	70200	10000	71562	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10914	1	139	505	10637	284	12	878	48	38	10902	133	2	124	1	0	7	2610	2	51	2	2	71463	40540	918	948	894	10000	40100	71782	71764	71838	71915	71681
50204	71627	537	1	0	0	0	0	0	0	549	0	796	1	0	696	1	128	71431	807	1	1	71452	25	50790	40560	10134	40100	10000	676992	2716885	49	68560	71845	71680	64987	3	65534	50100	40200	10000	70200	10000	71817	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10884	1	151	460	10704	304	14	925	36	29	10902	127	3	125	1	0	3	2610	2	51	2	2	71531	40500	924	816	972	10000	40100	71692	71743	71753	71867	71983
50204	71784	536	1	0	0	0	0	1	0	536	0	819	1	0	688	1	136	71682	789	1	1	71615	25	50740	40580	10143	40100	10000	677153	2706179	49	68618	71958	71712	65203	3	65294	50100	40200	10000	70200	10000	71646	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10945	2	171	453	10656	263	7	872	32	29	10929	134	2	120	1	0	3	2610	2	51	2	2	71537	40524	894	854	858	10000	40100	71688	71598	71748	71763	71605

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1609

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	71789	538	1	0	0	0	0	2	0	499	834	2	520	1	280	71796	804	0	1	71318	25	50595	40482	10151	40010	10000	630236	2723559	49	68465	71600	71799	65043	3	65344	50010	40020	10000	70020	10000	71820	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10963	1	126	504	10620	246	10	914	122	22	10892	114	2	133	1	0	4	2520	4	65	0	6	6	71372	40516	914	784	924	10000	40010	71528	71630	71571	71755	71642
50024	71731	537	1	0	0	0	1	0	0	442	850	2	552	1	192	71616	826	0	1	71386	25	50595	40474	10111	40010	10000	629172	2709102	49	68582	71758	71740	65142	3	65430	50010	40020	10000	70020	10000	71718	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10910	1	150	482	10664	256	8	905	152	16	10894	122	2	118	1	0	12	2520	4	65	0	4	6	71535	40536	842	892	878	10000	40010	71639	71642	71802	71749	71697
50024	71523	537	1	0	0	0	0	0	0	504	851	2	552	1	276	71829	808	1	0	71313	25	50640	40486	10115	40010	10000	627907	2716217	49	68414	71686	71602	65123	3	65701	50010	40020	10000	70020	10000	71498	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10893	1	151	504	10661	243	6	932	156	19	10908	123	2	124	1	6	7	2520	6	65	1	4	4	71447	40452	854	892	886	10000	40010	71669	71475	71563	71757	71665
50024	71837	536	1	0	0	0	0	0	0	541	854	2	576	1	312	71636	803	1	0	71231	25	50700	40486	10134	40010	10000	628725	2709906	49	68590	71794	71599	65027	3	65254	50010	40020	10000	70020	10000	71458	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10904	1	141	488	10663	248	6	918	168	19	10922	120	2	121	1	3	20	2520	4	65	1	4	5	71584	40500	874	878	818	10000	40010	71596	71524	71705	71665	71682
50024	71557	537	1	0	0	0	0	0	0	445	830	2	576	1	284	71808	793	0	0	71531	25	50656	40558	10120	40010	10000	629545	2712806	49	68601	71641	71692	64991	3	65341	50010	40020	10000	70020	10000	71741	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10901	1	137	490	10621	253	8	918	138	19	10933	116	1	118	1	3	8	2520	3	65	1	4	5	71404	40476	838	876	824	10000	40010	71537	71546	71495	71704	71653
50024	71483	537	1	0	0	0	0	0	0	520	822	2	440	1	228	71663	839	0	1	71190	25	50595	40462	10113	40010	10000	628948	2710935	49	68556	71586	71588	65063	3	65256	50010	40020	10000	70020	10000	71477	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10928	1	143	488	10652	259	7	907	112	17	10924	106	1	126	1	1	4	2520	4	65	1	4	4	71560	40492	918	928	892	10000	40010	71560	71795	71629	71749	71531
50024	71489	536	1	0	0	1	0	0	0	495	826	2	464	1	180	71643	796	0	0	71196	25	50590	40470	10135	40010	10000	628991	2706957	49	68459	71496	71464	65139	3	65208	50010	40020	10000	70020	10000	71650	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10895	1	152	487	10645	255	9	899	70	19	10917	129	1	120	1	2	9	2520	4	65	0	4	4	71372	40484	782	750	906	10000	40010	71698	71622	71541	71686	71555
50024	71726	536	1	0	0	0	0	0	0	464	835	3	432	1	132	71650	767	0	0	71280	25	50645	40498	10118	40010	10000	630146	2717098	49	68589	71552	71751	65037	3	65331	50010	40020	10000	70020	10000	71512	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10886	1	144	495	10645	260	9	908	112	20	10908	122	2	119	1	2	6	2520	4	65	1	4	4	71668	40464	858	872	886	10000	40010	71554	71598	71620	71768	71579
50024	71437	537	1	0	0	0	0	0	0	535	841	2	592	1	320	71676	812	1	0	71403	25	50525	40510	10123	40010	10000	629870	2708528	49	68494	71508	71808	65110	3	65362	50010	40020	10000	70020	10000	71606	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10908	1	177	495	10665	251	9	929	170	32	10891	117	2	123	1	1	9	2520	4	65	1	4	4	71432	40512	902	772	940	10000	40010	71710	71738	71604	71593	71529
50024	71674	537	1	0	0	0	0	0	0	340	850	2	536	1	392	71580	809	0	0	71326	25	50580	40486	10119	40010	10000	629973	2718223	49	68585	71775	71682	65015	3	65357	50010	40020	10000	70020	10000	71744	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10892	2	143	485	10630	244	9	896	116	25	10877	117	1	118	1	3	7	2520	4	65	1	4	3	71411	40504	866	870	886	10000	40010	71720	71578	71676	71638	71655

Test 3: throughput

Count: 8

Code:

  ldrsw x0, [x6], #8
  ldrsw x0, [x7], #8
  ldrsw x0, [x8], #8
  ldrsw x0, [x9], #8
  ldrsw x0, [x10], #8
  ldrsw x0, [x11], #8
  ldrsw x0, [x12], #8
  ldrsw x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3671

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29888	220	1	0	0	0	0	1	0	7092	0	830	1	776	116	160	29450	801	346	1836	2060	2146	25	160173	80179	80000	80120	80015	400837	1298815	1	58	49	26397	29362	29310	9490	0	6	9554	160135	80224	80020	80752	80020	29312	35	1	1	80201	100	99	55	100	80000	100	80000	0	100	80918	32	393	5489	0	84986	670	10	913	92	4967	85671	665	141	5191	5458	16	3	5	1	1	1	5117	0	16	0	0	29367	44	80074	531	628	103	80000	80100	29328	29376	29522	29380	29445
160204	29493	222	1	0	0	0	1	0	0	6803	0	815	1	704	113	180	29508	778	366	1703	1752	2170	25	160147	80159	80000	80100	80000	400785	1290811	1	56	49	26260	29143	29328	9459	0	3	9444	160100	80200	80000	80200	80000	29377	35	1	1	80201	100	99	20	100	80000	100	80000	0	100	80954	36	420	5167	0	84937	663	10	914	42	4652	85404	844	132	4547	5057	34	2	5	0	0	0	5110	1	16	1	1	29123	27	80046	694	606	107	80000	80100	29357	29303	29405	29477	29357
160204	29232	219	1	0	0	0	1	0	0	6671	0	812	1	720	127	100	29351	791	340	1773	1642	2309	25	160156	80161	80000	80100	80000	400750	1298532	1	70	49	26347	29479	29455	9324	0	3	9458	160100	80200	80000	80200	80000	29379	35	1	1	80201	100	99	30	100	80000	100	80000	0	100	80912	16	401	5150	0	85267	638	7	924	80	4956	86034	750	133	4855	5071	18	2	3	0	0	0	5110	1	16	1	1	29336	39	80060	588	642	100	80000	80100	29354	29366	29275	29464	29583
160204	29480	220	1	1	0	0	0	0	0	6807	0	832	1	736	134	140	29375	791	348	1702	1670	2370	25	160160	80163	80000	80100	80000	400814	1298812	1	64	49	26304	29071	29236	9398	0	3	9664	160100	80200	80000	80200	80000	29398	35	1	1	80201	100	99	36	100	80000	100	80000	0	100	80936	18	366	5354	0	85010	614	11	913	82	4809	85930	834	119	5426	5235	16	3	3	0	0	0	5110	1	16	1	1	29509	24	80071	659	630	86	80000	80100	29332	29404	29467	29412	29381
160204	29414	220	1	0	0	0	1	0	0	6810	0	804	1	744	122	140	29145	790	349	1784	1685	2167	25	160157	80151	80000	80100	80000	400784	1301400	1	63	49	26377	29271	29402	9190	0	3	9426	160100	80200	80000	80200	80000	29407	35	1	1	80201	100	99	44	100	80000	100	80000	0	100	80928	31	415	5655	0	85830	649	11	918	92	5232	86220	827	125	4558	5888	34	0	111	0	0	0	5110	1	17	1	1	29464	31	80065	586	613	96	80000	80100	29456	29521	29547	29677	29571
160204	29308	221	2	1	2	0	1	0	0	6567	0	830	1	696	119	140	29405	806	355	1629	1600	2126	25	160149	80164	80000	80100	80000	400775	1298462	1	45	49	26424	29191	29185	9433	0	3	9280	160100	80200	80000	80200	80000	29500	35	1	1	80201	100	99	36	100	80000	100	80000	0	100	81200	36	423	5408	0	84961	676	8	931	38	4525	86230	679	125	5028	4992	34	0	4	0	0	0	5110	1	16	1	1	29362	36	80050	630	645	113	80000	80100	29467	29458	29374	29484	29447
160204	29447	219	2	2	0	0	1	0	0	6765	0	812	1	728	115	256	29302	799	363	1603	1685	2123	25	160163	80159	80000	80100	80000	400747	1294423	1	56	49	26646	29249	29399	9271	0	3	9322	160100	80200	80000	80200	80000	29579	35	1	1	80201	100	99	39	100	80000	100	80000	0	100	80991	35	415	5504	0	85028	653	6	898	34	4817	85849	908	140	4855	5372	35	0	5	0	0	0	5110	1	16	1	1	29360	28	80057	548	614	85	80000	80100	29463	29423	29417	29483	29498
160204	29417	221	2	0	2	2	1	0	0	6822	0	812	1	744	121	260	29395	808	386	1809	1622	1966	25	160164	80154	80000	80100	80000	400794	1297278	1	60	49	26363	29537	29356	9287	0	3	9418	160100	80200	80000	80200	80504	29475	35	1	1	80201	100	99	45	100	80000	100	80000	0	100	80921	34	392	5443	0	85069	657	11	914	46	4627	85705	849	124	4413	5570	35	0	8	0	0	0	5110	1	17	1	1	29264	43	80067	649	609	102	80000	80100	29460	29457	29635	29337	29245
160204	29309	220	2	0	0	2	1	0	0	6771	0	796	1	536	115	100	29413	804	361	1761	1798	2229	25	160160	80154	80000	80100	80000	400756	1308578	1	58	49	26362	29431	29544	9480	0	3	9310	160100	80200	80000	80200	80000	29282	35	1	1	80201	100	99	43	100	80000	100	80000	0	100	80936	36	391	4891	0	85253	638	8	868	46	5289	85709	769	122	4968	5055	36	2	3	0	0	0	5110	1	17	1	1	29274	24	80065	610	515	109	80000	80100	29527	29562	29383	29256	29483
160204	29300	219	2	0	0	0	1	0	0	7242	0	809	1	680	130	156	29405	810	382	1693	1742	2134	25	160150	80155	80000	80100	80000	400755	1304005	1	52	49	26315	29529	29201	9333	0	3	9332	160100	80200	80000	80200	80000	29383	35	1	1	80201	100	99	31	100	80000	100	80000	0	100	80926	36	414	5299	0	85154	643	9	930	42	4880	85805	813	136	5007	4913	36	0	3	0	0	0	5110	1	16	1	1	29347	35	80059	579	582	129	80000	80100	29456	29389	29499	29325	29382

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3678

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	0e	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29930	221	0	0	0	6385	834	1	720	111	128	29453	813	412	1740	1920	2306	91	160384	80085	80000	80010	80000	400292	1300230	0	1	71	49	26570	29395	29391	9535	3	9668	160010	80020	80000	80020	80000	29585	35	1	1	80021	10	9	40	10	80000	10	80000	0	10	80938	0	422	5685	0	85032	707	9	954	118	5133	85885	802	134	4708	5468	3	6	5020	3	0	0	1	15	0	0	1	1	29326	28	80048	601	561	93	80000	80010	29524	29370	29617	29635	29467
160024	29374	221	0	0	0	6537	837	1	712	119	120	29284	811	424	1767	1670	2094	25	160068	80079	80000	80010	80000	400279	1298007	0	0	53	49	26236	29576	29597	9542	3	9773	160010	80020	80000	80020	80000	29563	35	1	1	80021	10	9	43	10	80000	10	80000	0	10	80916	0	430	5912	0	85102	693	6	898	108	4955	85726	818	139	4825	5271	0	3	5020	0	0	0	1	16	2	0	1	1	29677	34	80075	608	609	116	80000	80010	29250	29445	29514	29333	29525
160024	29492	222	0	0	0	6909	824	1	736	128	200	29522	815	440	1708	1879	2051	25	160081	80073	80000	80010	80000	400373	1286737	1	1	68	49	26233	29423	29271	9262	3	9737	160010	80020	80000	80020	80000	29394	35	1	1	80021	10	9	47	10	80000	10	80000	0	10	80950	0	418	5037	0	84721	690	9	940	82	4697	86121	844	130	5046	5486	3	3	5020	0	0	0	1	15	0	0	1	1	29372	41	80074	624	553	105	80000	80010	29540	29285	29240	29396	29500
160024	29399	219	0	0	0	7231	825	1	720	108	120	29356	827	520	1906	1817	2253	25	160071	80074	80000	80010	80000	400382	1295461	1	1	68	49	26392	29336	29611	9183	3	9567	160010	80020	80000	80020	80000	29234	35	1	1	80021	10	9	58	10	80000	10	80000	0	10	80936	0	420	5719	0	85540	716	6	922	76	5985	85583	722	132	4677	4988	0	3	5020	0	0	0	1	16	0	0	1	1	29701	31	80063	672	560	97	80000	80010	29386	29625	29501	29394	29454
160024	29547	220	0	0	0	6608	812	1	712	121	96	29515	847	440	1890	1997	2132	25	160070	80066	80000	80010	80000	400355	1292295	0	0	52	49	26138	29231	29296	9501	3	9735	160010	80020	80000	80020	80000	29467	35	1	1	80021	10	9	36	10	80000	10	80000	0	10	80892	0	394	5746	0	85414	669	11	932	26	4697	86311	780	129	4828	5869	0	3	5020	0	0	1	1	16	0	0	1	1	29451	29	80067	540	647	117	80000	80010	29240	29242	29443	29397	29551
160024	29141	221	0	0	0	6855	868	1	776	137	108	29286	794	444	1722	1920	2156	25	160087	80071	80000	80010	80000	400373	1304664	0	1	68	49	26271	29459	29525	9470	3	10082	160010	80020	80000	80020	80000	29512	35	1	1	80021	10	9	59	10	80000	10	80000	0	10	80903	0	450	5751	0	85582	749	5	964	28	4928	85851	770	124	5310	5717	3	4	5020	0	1	0	1	16	0	0	1	1	29478	24	80074	647	639	98	80000	80010	29311	29474	29536	29422	29430
160024	29417	221	0	1	0	6871	822	1	720	108	112	29497	804	482	1773	1901	2372	25	160073	80072	80000	80010	80000	400362	1315183	0	1	74	49	26402	29413	29519	9478	3	9990	160010	80020	80000	80020	80000	29475	35	1	1	80021	10	9	45	10	80000	10	80000	1	10	80934	0	394	5654	0	85797	693	8	916	74	4940	86304	847	136	4955	5406	0	3	5105	0	0	0	1	16	0	0	1	1	29624	22	80059	560	620	108	80000	80010	29440	29369	29477	29500	29390
160024	29543	220	0	0	0	7221	835	1	728	127	112	29685	805	447	1771	1661	2036	25	160065	80077	80000	80010	80000	400339	1296330	0	0	65	49	26418	29453	29330	9191	3	9727	160010	80020	80000	80020	80000	29608	35	1	1	80021	10	9	60	10	80000	10	80000	0	10	80924	0	422	5478	0	84913	678	9	956	76	5116	86138	891	134	4946	5164	0	4	5020	0	0	0	1	16	0	0	1	1	29367	26	80071	609	581	87	80000	80010	29404	29239	29280	29354	29384
160024	29448	220	0	0	0	7348	824	1	728	131	124	29517	798	487	1918	1866	2251	25	160078	80078	80000	80010	80000	400326	1299273	1	1	73	49	26347	29510	29469	9251	3	9670	160010	80020	80000	80020	80000	29457	35	1	1	80021	10	9	58	10	80000	10	80000	0	10	80885	0	400	5385	0	85314	651	11	898	24	4859	86222	786	122	5064	5049	0	3	5020	0	0	0	1	15	0	0	1	1	29207	32	80062	709	635	102	80000	80010	29406	29316	29338	29340	29391
160024	29443	220	0	0	0	6999	848	1	720	122	124	29307	803	477	1763	1713	2088	25	160075	80069	80000	80010	80000	400376	1298113	0	1	66	49	26300	29523	29483	9274	3	9586	160010	80020	80000	80020	80000	29564	35	1	1	80021	10	9	40	10	80000	10	80000	0	10	80942	0	429	5064	0	85609	699	11	947	76	5331	86148	729	120	4958	5047	0	8	5020	0	0	0	4	16	0	0	1	1	29306	40	80065	537	598	96	80000	80010	29485	29502	29327	29504	29478

LDRSW (post-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations