Firestorm: LDP (32-bit) measurements

Code:

  ldp w0, w1, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	394	3	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15014	1	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	3	16	1	1	391	10	10	4	1000	1000	395	396	395	395	395
2004	394	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15014	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15014	1	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	2	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15053	1	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	394	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15065	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	1000	395	395	395	395	395
2004	394	3	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15014	0	394	394	92	3	127	1000	2000	1000	394	35	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	39	43	73	1	16	1	1	391	10	10	4	1000	1000	399	399	399	399	399
2004	394	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15288	1	398	398	96	3	127	1000	2000	1000	398	35	1	1	1001	1000	1000	1000	43	1039	2	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	1000	399	399	399	399	399
2004	398	3	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15288	1	398	398	96	3	131	1000	2000	1000	394	35	1	1	1001	1000	1000	1000	43	1040	0	39	1038	6	1	39	43	73	1	16	1	1	395	14	14	7	1000	1000	399	399	399	399	399
2004	398	2	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15246	0	398	398	96	3	131	1000	2000	1000	398	35	1	1	1001	1000	1000	1000	43	1039	0	39	1038	6	1	39	43	73	1	16	2	2	391	14	10	7	1000	1000	395	395	399	395	395
2004	394	3	1	1	45	0	0	1	383	2	1	1	19	25	1000	1000	1000	15065	0	398	398	96	3	131	1000	2000	1000	398	35	1	1	1001	1000	1000	1000	43	1039	0	39	1039	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	1000	399	399	399	399	399

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	19	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70047	525	1	1	1	0	453	1	0	70035	69698	59684	25	40100	30103	10002	30100	10000	613915	3342056	1	49	66970	70050	70050	63406	3	63710	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	2610	3	64	1	1	69798	30003	9	6	6	10000	40100	70036	70051	70048	70048	70051
50204	70050	524	0	1	0	0	103	0	0	70020	69714	59684	25	40104	30103	10000	30100	10000	613652	3342056	0	49	66970	70050	70035	63388	3	63710	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2636	1	64	1	1	69798	30000	9	0	9	10000	40100	70088	70036	70051	70051	70100
50204	70050	525	0	0	0	0	244	1	0	70220	69698	59684	25	40104	30100	10001	30100	10000	613756	3341906	0	49	66970	70050	70035	63400	3	63695	40100	30200	20000	60584	10000	70047	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	0	0	2610	1	64	1	1	69813	30003	9	0	9	10000	40100	70048	70036	70051	70051	70051
50204	70035	524	0	0	0	0	73	1	0	70035	69714	59700	25	40104	30100	10001	30100	10000	613915	3342056	1	49	66970	70035	70050	63403	3	63707	40100	30200	20000	60200	10000	70050	37	2	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	2610	1	64	1	1	69810	30003	6	0	0	10000	40100	70048	70051	70036	70051	70051
50204	70035	524	0	0	0	0	73	1	0	70020	69714	59700	25	40104	30103	10001	30100	10000	613915	3341304	0	49	66970	70050	70035	63502	3	63695	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	64	1	1	69798	30003	0	6	9	10000	40100	70051	70051	70051	70051	70051
50204	70035	525	0	0	0	0	67	0	0	70035	69698	59700	25	40104	30100	10000	30100	10000	613652	3342056	0	49	66970	70035	70050	63388	3	63710	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	2610	1	64	1	1	69813	30000	9	6	9	10000	40100	70051	70056	70051	70051	70051
50204	70050	524	0	0	0	0	316	1	0	70023	69714	59700	25	40104	30103	10001	30100	10000	613915	3341304	0	49	66970	70050	70047	63400	3	63707	40100	30200	20000	60200	10000	70050	37	3	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	1	2	6	10000	1	1	0	0	2610	1	64	1	1	69798	30000	9	6	0	10000	40100	70052	70051	70036	70051	70036
50204	70035	525	0	0	0	0	10	1	0	70036	69715	59684	25	40104	30103	10001	30100	10000	613924	3342056	0	49	66968	70050	70047	63418	3	63707	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	6	0	3	10000	1	0	0	0	2610	1	64	1	1	69800	30000	9	6	6	10000	40100	70048	70051	70057	70061	70053
50204	70035	524	0	0	1	0	375	0	0	70035	69714	59694	25	40104	30103	10001	30100	10000	613652	3341906	0	49	66955	70050	70050	63403	3	63707	40100	30200	20000	60200	10000	70050	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	0	0	2610	1	64	1	1	69813	30003	9	6	9	10000	40100	70051	70051	70051	70051	70051
50204	70047	525	0	1	0	0	153	1	0	70032	69711	59694	25	40100	30103	10001	30100	10000	613756	3341304	0	49	66967	70035	70047	63400	3	63707	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	1	64	1	1	69810	30003	9	6	9	10000	40100	70036	70051	70051	70036	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70117	525	0	0	0	0	0	0	4	0	1	0	0	0	70020	69719	59689	25	40010	30013	10001	30010	10000	615126	3341899	0	49	66955	70050	70077	63447	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	1	99	1	1	69851	30003	9	6	6	10000	40010	70051	70051	70036	70051	70051
50024	70050	524	0	1	0	0	0	0	1	0	1	0	0	0	70032	69714	59677	25	40014	30013	10001	30010	10000	614994	3342046	0	49	66970	70128	70124	63438	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	0	1	0	2520	1	78	1	1	69817	30003	0	6	0	10000	40010	70051	70051	70051	70051	70036
50024	70050	525	0	0	0	0	0	0	0	0	1	0	0	0	70035	69714	59692	25	40014	30010	10001	30010	10000	615126	3342046	0	49	66970	70146	70105	63406	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	0	0	2520	2	99	2	1	69817	30003	9	0	6	10000	40010	70051	70051	70051	70151	70036
50024	70050	525	0	0	0	0	0	0	1	0	0	0	0	0	70020	69719	59692	25	40010	30013	10001	30010	10000	614994	3341899	1	49	66970	70066	70047	63403	3	63682	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	2520	1	78	1	1	69801	30003	9	6	0	10000	40010	70036	70036	70051	70051	70036
50024	70050	524	0	0	0	0	0	0	1	0	1	0	0	0	70020	69714	59692	25	40014	30013	10001	30010	10000	614994	3342046	1	49	66955	70143	70091	63420	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	0	2520	1	78	1	1	69817	30003	6	0	6	10000	40010	70051	70036	70051	70051	70051
50024	70035	525	0	0	0	0	0	0	6	0	1	0	0	0	70020	69714	59677	25	40014	30010	10001	30010	10000	614994	3341295	2	49	66970	70113	70110	63404	3	63718	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	3	10000	0	0	0	2520	1	78	1	2	69801	30000	9	9	9	10000	40010	70052	70048	70036	70051	70051
50024	70035	525	0	0	0	0	0	0	1	0	0	0	0	0	70035	69719	59692	25	40014	30013	10001	30010	10000	615126	3341295	0	49	66970	70070	70051	63418	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	0	1	0	2520	2	99	1	1	69818	30003	9	0	0	10000	40010	70036	70048	70048	70051	70036
50024	70035	525	0	0	0	0	0	0	1	0	1	0	0	0	70035	69714	59692	25	40010	30013	10000	30010	10000	614994	3342046	0	49	66970	70089	70046	63415	3	63718	40010	30020	20000	60020	10000	70050	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	3	10000	0	0	0	2520	1	99	2	1	69817	30003	6	0	6	10000	40010	70051	70048	70051	70051	70051
50024	70050	525	0	0	0	0	0	0	1	0	0	0	0	0	70032	69718	59693	25	40010	30013	10001	30010	10000	615126	3342046	1	49	66970	70136	70099	63431	3	63718	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	2520	1	78	1	1	69817	30003	9	9	0	10000	40010	70051	70051	70036	70036	70051
50024	70050	524	0	0	0	0	0	0	1	0	1	0	0	0	70035	69719	59692	25	40010	30013	10000	30010	10000	615120	3341899	0	49	66967	70120	70081	63419	3	63682	40010	30020	20000	60020	10000	70073	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2520	1	99	1	2	69817	30003	9	0	9	10000	40010	70051	70051	70051	70051	70051

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50205	70051	524	1	0	0	0	0	0	1	0	1	0	70039	69719	59700	25	40104	30103	10002	30100	10000	613652	3342104	0	49	66955	70036	70051	63407	3	63714	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	1	0	2610	2	64	1	1	69814	30003	0	10	10	10000	40100	70036	70052	70052	70052	70052
50204	70035	525	0	0	0	0	0	0	1	0	1	0	70036	69719	59703	25	40104	30103	10001	30100	10000	613888	3341304	0	49	66981	70054	70051	63388	3	63714	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	2610	1	64	1	1	69814	30003	10	10	0	10000	40100	70052	70052	70052	70052	70052
50204	70054	525	0	0	0	0	0	0	0	0	1	0	70039	69698	59703	25	40100	30100	10001	30100	10000	613930	3342104	1	49	66971	70051	70051	63388	3	63711	40100	30200	20000	60200	10000	70052	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	0	0	0	2610	1	64	1	1	69821	30003	13	10	0	10000	40100	70055	70036	70056	70053	70055
50204	70051	525	0	0	0	0	0	0	1	0	0	0	70036	69698	59703	25	40104	30100	10001	30262	10000	613930	3342104	0	49	66972	70035	70051	63404	3	63711	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	1	0	2610	1	64	1	1	69814	30003	13	0	13	10000	40100	70052	70052	70055	70055	70055
50204	70051	524	0	0	0	0	0	0	6	0	0	0	70036	69715	59723	25	40104	30103	10000	30100	10000	613930	3341304	1	49	66955	70056	70054	63393	3	63743	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	2610	1	64	1	1	69814	30000	0	0	10	10000	40100	70052	70052	70052	70036	70052
50204	70035	525	0	0	0	0	0	0	0	0	0	0	70036	69719	59684	25	40104	30103	10001	30100	10000	613888	3341304	0	49	66986	70054	70054	63407	3	63714	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	1	64	1	1	69798	30003	0	10	13	10000	40100	70055	70052	70055	70055	70055
50204	70054	525	0	0	0	0	0	0	0	0	0	0	70039	69698	59700	25	40100	30103	10000	30100	10000	613652	3342104	0	49	66972	70054	70051	63407	3	63695	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	2610	1	64	1	1	69815	30003	0	13	10	10000	40100	70036	70055	70036	70055	70055
50204	70054	524	0	0	0	0	0	0	1	0	0	0	70039	69698	59703	25	40104	30103	10001	30100	10000	613888	3341304	1	49	66976	70054	70054	63407	3	63714	40100	30200	20000	60200	10000	70035	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	1	0	0	10000	1	1	0	2610	1	64	1	1	69814	30003	13	13	0	10000	40100	70052	70052	70052	70052	70055
50204	70035	524	0	0	0	0	0	0	1	0	1	0	70079	69700	59684	25	40104	30103	10001	30100	10000	615263	3346232	0	49	66974	70035	70054	63407	3	63714	40100	30200	20000	60200	10000	70054	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	2610	1	64	1	1	69798	30003	0	10	13	10000	40100	70036	70052	70052	70052	70052
50204	70035	524	0	0	1	1	0	0	1	0	1	0	70036	69719	59684	25	40104	30103	10000	30100	10000	613652	3342104	1	49	67348	70148	70056	63388	3	63714	40100	30200	20000	60200	10000	70051	37	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	2610	1	64	1	1	69817	30003	10	10	13	10000	40100	70055	70055	70055	70055	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50025	70051	525	0	0	0	0	1	1	0	0	1	0	1	0	70036	69719	59769	25	40014	30013	10001	30010	10000	614994	3342254	49	66956	70052	70036	63419	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10014	0	0	0	0	10000	1	1	0	2520	1	64	1	1	69818	30003	13	10	0	10000	40010	70052	70055	70052	70055	70036
50024	70063	527	0	0	0	0	1	0	0	4	1	0	0	0	70076	69719	59693	25	40014	30010	10001	30010	10000	615145	3342095	49	66972	70051	70051	63403	3	63719	40010	30020	20000	61324	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	2	1	10000	0	0	0	0	10000	1	1	0	2520	1	99	1	1	69818	30009	13	13	13	10000	40010	70055	70055	70055	70036	70036
50024	70055	525	0	0	0	0	1	0	0	0	52	352	1	0	70360	69719	59707	25	40014	30013	10001	30010	10204	615481	3342254	49	66971	70051	70051	63403	3	63736	40010	30020	20000	60020	10000	70035	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	2520	1	64	2	2	69818	30003	13	0	13	10000	40010	70036	70055	70057	70036	70056
50024	70051	525	0	0	0	0	1	1	0	0	0	0	0	0	70039	69715	59678	25	40014	30013	10001	30010	10000	615481	3341295	49	66971	70054	70051	63422	3	63736	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	3	10000	0	1	0	2520	1	100	1	1	69817	30013	10	0	10	10000	40010	70055	70036	70052	70055	70052
50024	70127	525	0	0	0	0	1	0	0	1	0	0	1	0	70039	69715	59693	25	40014	30013	10001	30010	10051	614994	3344322	49	66971	70051	70035	63422	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	0	10000	1	0	0	2520	1	64	1	1	69818	30003	13	13	0	10000	40010	70055	70052	70036	70055	70036
50024	70054	524	0	0	0	0	1	0	0	0	1	0	1	0	70020	69715	59693	25	40010	30013	10000	30010	10000	615145	3341295	49	66977	70057	70035	63422	3	63682	40010	30020	20000	60020	10000	70054	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	2520	1	99	1	1	69818	30003	13	0	13	10000	40010	70052	70055	70055	70055	70055
50024	70054	524	0	0	0	0	1	0	0	0	0	0	1	0	70020	69962	59707	25	40014	30013	10001	30010	10000	615481	3342254	49	66972	70054	70054	63422	3	63736	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	5	0	0	10000	1	0	0	2520	1	64	1	1	69803	30003	0	13	13	10000	40010	70055	70052	70052	70036	70036
50024	70035	524	0	0	0	0	1	1	0	0	1	0	1	0	70039	69725	59709	25	40010	30010	10001	30010	10000	615481	3342254	49	66971	70051	70054	63403	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	1	10000	0	0	0	0	10000	1	1	0	2520	1	78	1	1	69817	30003	10	10	0	10000	40010	70064	70055	70036	70036	70055
50024	70056	525	0	0	0	0	1	0	0	0	1	0	0	0	70039	69719	59707	25	40014	30013	10000	30010	10000	615481	3341295	49	66974	70054	70054	63422	3	63682	40787	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10003	0	3	0	0	10000	1	1	0	2520	1	64	2	1	69817	30000	13	10	0	10000	40010	70055	70055	70055	70055	70055
50024	70039	525	0	0	0	0	1	1	0	0	0	0	0	0	70231	69719	59851	25	40014	30013	10003	30010	10000	615481	3341295	49	66971	70054	70051	63422	3	63719	40010	30020	20000	60020	10000	70051	37	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	0	10000	0	30	2	0	10000	1	1	0	2520	1	64	1	1	69817	30000	0	13	13	10000	40010	70036	70055	70036	70055	70052

Test 4: throughput

Count: 8

Code:

  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]
  ldp w0, w1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	26729	200	1	1	1	1	1	1	66	1	0	3	26721	0	0	7	0	25	80100	100	80000	100	80000	500	1169281	1	49	23627	26707	26707	6650	3	6685	80100	200	160000	200	80000	26824	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80000	0	43	0	80039	0	0	39	80039	6	0	58	0	19	1	5110	1	16	1	1	26711	13	13	5	80000	80100	26737	26737	26737	26737	26737
160204	26736	200	1	1	0	0	0	0	66	1	0	2	26721	3	0	7	20	25	80100	100	80000	100	80000	500	1173690	1	49	23656	26736	26714	6637	3	6694	80100	200	160000	200	80000	26714	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	20	43	0	80019	0	1	1017	80039	6	1	58	43	19	0	5110	1	16	1	1	26711	13	0	5	80000	80100	26737	26737	26717	26738	26715
160204	26736	202	1	1	1	1	0	0	21	0	0	3	26721	0	7	7	0	25	80100	100	80000	100	80000	500	1168753	1	49	23634	26736	26736	6658	3	6694	80100	200	160000	200	80000	26714	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	43	0	80058	0	0	21	80000	0	1	58	43	19	1	5110	1	16	1	1	26733	13	13	5	80000	80100	26737	26737	26737	26737	26737
160204	26736	201	1	0	0	1	0	0	21	1	0	3	26721	0	0	7	0	25	80100	100	80000	100	80000	500	1171251	1	49	23656	26736	26736	6659	3	6694	80100	200	160000	200	80000	26737	35	1	1	80201	100	99	1	100	80000	100	80000	0	100	80019	20	0	0	80019	1	1	61	80040	6	0	19	43	19	2	5110	1	16	1	1	26733	13	13	5	80000	80100	26737	26737	26715	26737	26715
160204	26736	200	1	1	1	1	0	0	21	0	0	2	26721	0	7	0	20	25	80100	100	80000	100	80000	500	1175184	1	49	23634	26736	26736	6658	3	6694	80100	200	160000	200	80000	26714	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80019	1	0	21	80039	0	0	59	43	19	0	5110	1	16	1	1	26711	13	13	0	80000	80100	26737	26737	26715	26737	26737
160204	26714	200	1	0	0	1	0	0	67	0	0	2	26699	3	0	7	19	25	80100	100	80000	100	80000	500	1174381	1	49	23634	26714	26714	6659	3	6672	80100	200	160000	200	80000	26736	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80059	1	1	21	80040	6	1	19	0	19	1	5110	1	16	1	1	26711	0	13	5	80000	80100	26737	26715	26737	26737	26715
160204	26736	200	1	1	1	1	0	0	67	1	0	3	26721	3	7	7	20	25	80100	100	80000	100	80000	500	1168485	1	49	23635	26736	26736	6659	3	6694	80100	200	160000	200	80000	26714	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80020	19	0	0	80059	1	1	60	80040	6	1	19	45	19	2	5110	1	16	1	1	26733	13	13	5	80000	80100	26737	26737	26737	26737	26737
160204	26714	200	1	0	1	1	0	0	67	0	0	2	26721	0	7	7	21	25	80100	100	80000	100	80000	500	1167892	1	49	23656	26736	26736	6659	3	6694	80100	200	160000	200	80000	26736	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	20	43	0	80149	0	0	61	80039	0	0	59	45	19	0	5138	1	16	1	1	26733	13	13	5	80000	80100	26737	26737	26972	26814	26737
160204	26714	201	1	0	0	1	0	0	67	0	0	3	26699	3	7	7	19	25	80100	100	80000	100	80000	500	1175341	1	49	23656	26714	26736	6659	3	6694	80100	200	160000	200	80000	26726	35	1	1	80201	100	99	0	100	80000	100	80000	0	100	80019	19	43	0	80059	0	1	21	80039	6	0	19	0	19	1	5110	1	16	1	1	26733	13	0	5	80000	80100	26715	26737	26716	26737	26737
160204	26714	200	1	0	0	1	0	0	66	0	0	1	26699	0	7	0	19	25	80100	100	80000	100	80000	500	1176542	1	49	23656	26736	26736	6659	3	6672	80100	200	160000	200	80000	26736	35	1	1	80201	100	99	0	100	80000	100	80000	1	100	80019	20	43	0	80058	0	0	61	80040	6	1	19	0	19	1	5110	1	16	1	1	26733	13	13	5	80000	80100	26737	26737	26715	26737	26737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	26735	201	1	1	1	0	0	65	0	0	0	3	26717	2	18	18	17	25	80010	10	80000	10	80000	50	1170443	0	1	49	23642	26722	26722	6668	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	1	35	80035	6	1	35	39	0	5020	0	9	16	17	17	26719	0	6	6	0	80000	80010	26723	26723	26723	26723	26723
160024	26727	200	0	0	0	0	0	41	0	0	0	0	26692	2	18	18	12	25	80010	10	80000	10	80000	50	1168935	0	1	49	23642	26722	26722	6668	3	6702	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	41	80035	0	1	0	0	0	5020	0	17	16	6	17	26719	0	6	6	2	80000	80010	26708	26723	26708	26723	26723
160024	26734	200	0	0	0	0	0	41	0	1	0	1	26707	2	18	18	0	25	80010	10	80000	10	80000	50	1175409	0	1	49	23642	26722	26722	6668	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80130	0	35	80035	6	1	35	39	0	5020	0	8	16	6	17	26704	0	6	6	2	80000	80010	26723	26723	26723	26723	26723
160024	26728	201	0	0	0	0	0	0	0	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1173343	1	1	49	23631	27200	26723	6668	3	6702	80010	20	160000	20	80000	26727	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	110	80035	6	1	36	39	0	5020	0	17	16	15	6	26719	0	6	0	2	80000	80010	26723	26723	26723	26723	26708
160024	26798	201	0	0	0	0	0	41	0	0	0	1	26692	2	18	18	12	25	80010	10	80000	10	80000	50	1170107	0	1	49	23642	26707	26722	6668	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	1	38	80035	0	1	0	39	0	5020	1	6	16	8	17	26719	0	6	6	2	80000	80010	26723	26723	26723	26708	26723
160024	26732	200	0	0	0	0	0	0	0	1	0	0	26707	0	18	18	12	25	80010	10	80000	10	80000	50	1170107	0	0	49	23642	26722	26722	6668	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	1	128	80035	0	1	35	0	0	5020	0	17	16	15	6	26719	0	6	6	2	80000	80010	26723	26723	26723	26723	26723
160024	26873	200	0	0	0	0	0	41	0	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1170107	0	0	49	23642	26722	26707	6668	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	1	137	80035	6	1	0	39	0	5020	0	17	16	8	17	26704	0	6	6	2	80000	80010	26723	26723	26723	26723	26723
160024	26732	200	0	0	0	0	0	41	0	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1178815	1	1	49	23642	26722	26722	6668	3	6702	80010	20	160000	20	80000	26707	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	35	80035	6	1	35	0	0	5020	0	17	16	6	17	26719	0	6	6	2	80000	80010	26723	26723	26708	26723	26723
160024	26732	200	0	0	0	0	0	41	0	1	0	1	26694	2	18	18	0	25	80010	10	80000	10	80000	50	1170395	0	1	49	23642	26722	26722	6668	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	41	80000	6	1	35	39	0	5020	0	7	16	17	6	26719	0	6	6	2	80000	80010	26723	26723	26723	26723	26723
160024	26727	200	0	0	0	0	0	41	0	1	0	1	26707	0	18	0	12	25	80010	10	80000	10	80000	50	1170491	1	1	49	23642	26722	26722	6668	3	6702	80010	20	160000	20	80000	26722	35	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	38	80035	6	1	36	39	0	5020	0	6	16	17	6	26719	0	6	6	2	80000	80010	26723	26723	26723	26723	26723

LDP (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations