Firestorm: LDRSB (64-bit) measurements

Code:

  ldrsb x0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	399	3	1	1	41	0	0	1	374	2	18	18	12	25	1000	1000	1000	14774	389	389	212	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1000	39	0	1035	35	1035	6	1	35	39	73	0	1	16	1	1	386	6	6	2	1000	390	390	390	391	390
1004	389	3	0	0	41	0	0	1	377	2	18	18	11	25	1000	1000	1000	14838	389	389	212	3	247	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1000	43	0	1039	39	1039	6	1	35	43	73	0	1	16	1	1	391	10	10	4	1000	395	395	395	392	390
1004	394	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	394	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	0	1035	39	1039	6	1	35	43	73	0	1	16	1	1	391	10	10	2	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	1	379	2	12	18	11	25	1000	1000	1000	14989	389	389	217	3	252	1000	1000	1000	394	72	1	1	1001	1000	1000	0	1000	39	0	1035	39	1035	6	1	35	39	73	0	1	16	1	1	391	10	6	4	1000	395	390	406	390	390
1004	394	3	0	0	45	0	0	1	379	2	18	18	16	25	1000	1000	1000	14989	394	394	217	3	252	1000	1000	1000	389	71	1	1	1001	1000	1000	0	1000	43	0	1039	39	1039	6	1	35	39	73	0	1	16	1	1	391	10	10	4	1000	395	395	407	397	390
1004	394	3	0	0	45	0	0	2	379	2	12	12	17	25	1000	1000	1000	15018	394	394	216	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	43	0	1039	39	1039	6	1	35	43	73	0	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15018	394	394	216	3	252	1000	1000	1000	391	71	1	1	1001	1000	1000	0	1000	43	0	1039	39	1039	6	1	35	43	73	0	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	2	379	2	18	7	16	25	1000	1000	1000	15018	394	389	212	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	0	1035	39	1035	6	1	39	39	73	0	1	16	1	1	391	10	6	4	1000	396	395	395	395	395
1004	389	3	0	0	45	0	0	2	379	2	12	12	11	25	1000	1000	1000	15037	389	394	217	3	252	1000	1000	1000	394	71	1	1	1001	1000	1000	0	1000	39	0	1035	39	1039	6	1	35	39	73	0	1	16	1	1	386	10	6	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	0	2	379	2	12	12	16	25	1000	1000	1000	14989	394	394	217	3	252	1000	1000	1000	391	71	1	1	1001	1000	1000	0	1000	39	0	1035	35	1035	6	1	35	39	73	0	1	16	1	1	386	10	6	4	1000	395	395	395	395	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	1	1	0	0	0	0	6	0	1	0	0	70039	69785	59713	25	40108	30100	10001	30100	10000	616041	3342398	0	49	66955	0	70035	70035	64631	3	64957	40100	30200	10000	60200	10000	70051	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	2611	4	71	4	2	69816	30003	10	10	13	10000	30100	70055	70052	70055	70055	70055
40204	70051	525	0	1	0	0	0	0	1	0	0	0	0	70020	69782	59695	25	40104	30103	10000	30100	10000	616014	3342254	1	98	66971	0	70051	70051	64631	3	64954	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	1	2611	2	71	2	2	69823	30003	13	13	0	10000	30100	70036	70055	70055	70055	70036
40204	70035	525	0	0	0	0	0	0	0	0	0	0	0	70039	69785	59713	25	40104	30103	10001	30100	10000	616041	3342398	0	49	66956	0	70057	70056	64631	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	2646	2	71	2	2	69817	30003	13	13	0	10000	30100	70055	70055	70036	70055	70055
40204	70051	524	0	0	0	0	0	0	1	0	1	0	0	70020	69785	59695	25	40104	30103	10001	30100	10000	616041	3341470	0	49	66971	0	70054	70054	64650	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	3	10000	1	1	2611	2	71	2	2	69856	30000	13	10	0	10000	30100	70055	70036	70036	70055	70055
40204	70051	524	0	0	0	0	0	0	1	0	0	1	1	70036	69764	59713	25	40104	30103	10001	30100	10000	616175	3342398	1	49	66974	0	70057	70035	64650	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	2611	2	71	2	2	69816	30003	13	13	0	10000	30100	70052	70036	70038	70055	70038
40204	70035	525	0	0	1	0	0	0	0	0	0	1	0	70036	69785	59695	25	40104	30103	10000	30100	10000	616041	3342398	0	49	66974	0	70051	70054	64650	3	64957	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	0	2611	2	71	2	2	69818	30003	0	13	13	10000	30100	70055	70055	70055	70055	70055
40204	70035	525	0	0	0	0	0	0	1	0	0	1	0	70039	69785	59755	25	40104	30103	10000	30100	10000	616175	3342398	1	49	66974	0	70054	70054	64650	3	65014	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	2611	2	71	2	2	69814	30003	13	13	0	10000	30100	70055	70036	70052	70055	70036
40204	70051	524	0	0	0	0	0	0	1	0	0	0	0	70039	69785	59713	25	40104	30100	10001	30100	10000	616175	3342398	0	49	66974	0	70035	70054	64650	3	64957	40100	30200	10000	60200	10000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	10000	1	0	0	10000	0	1	2611	2	71	3	2	69800	30000	13	13	10	10000	30100	70055	70055	70037	70055	70055
40204	70054	525	0	0	0	0	0	0	1	0	0	1	0	70036	69785	59713	44	40104	30100	10000	30100	10000	616922	3342974	0	49	66974	0	70054	70035	64655	3	64938	40100	30200	10000	60200	10000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	2645	2	71	2	2	69800	30000	13	13	13	10000	30100	70055	70055	70098	70036	70055
40204	70035	525	0	1	1	1	0	0	1	0	0	1	0	70039	69782	59713	25	40104	30100	10001	30100	10000	616041	3341470	1	49	66974	0	70157	70052	64650	3	64957	40100	30200	10000	60200	10000	70054	35	2	1	40201	100	99	100	10000	30100	10000	1	100	10000	1	10000	0	0	3	10000	1	1	2611	2	71	2	2	69815	30003	0	13	13	10000	30100	70036	70036	70052	70055	70055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70053	525	0	0	0	0	1	0	1	0	0	0	70035	69728	59709	25	40010	30013	10002	30010	10000	617068	3342206	0	49	66970	70050	70035	64668	3	64975	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	5	71	0	2	1	69801	30000	9	0	9	10000	30010	70036	70036	70051	70048	70036
40024	70047	524	0	0	0	0	0	0	1	1	0	0	70035	69760	59709	25	40010	30013	10001	30010	10000	617068	3342206	0	49	66970	70050	70050	64653	3	64975	40010	30020	10000	60020	10000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	2520	1	71	0	2	1	69810	30000	9	6	9	10000	30010	70048	70051	70036	70051	70051
40024	70050	524	0	0	0	0	0	0	1	0	0	0	70020	69743	59706	25	40014	30013	10001	30010	10000	616982	3342206	0	49	66967	70050	70035	64653	3	64960	40010	30020	10055	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	2520	1	71	0	1	1	69811	30003	0	6	9	10000	30010	70051	70036	70051	70051	70051
40024	70049	524	0	0	0	0	0	0	1	0	0	0	70035	69760	59695	25	40014	30013	10001	30010	10000	617036	3342494	0	49	66970	70050	70050	64653	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	2520	1	71	0	1	1	69819	30003	9	0	9	10000	30010	70051	70048	70048	70036	70054
40024	70050	525	0	0	0	0	0	0	1	1	0	0	70032	69760	59709	25	40014	30013	10000	30010	10000	616982	3342206	0	49	66967	70035	70050	64668	3	64972	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	1	71	0	1	1	69854	30003	6	6	6	10000	30010	70051	70036	70048	70051	70051
40024	70047	525	0	0	0	0	0	0	1	0	0	0	70032	69760	59709	25	40010	30010	10001	30010	10000	617068	3342062	0	49	66967	70047	70049	64668	3	64972	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	2520	1	71	0	2	1	69814	30003	6	0	9	10000	30010	70036	70048	70036	70048	70036
40024	70047	524	0	0	0	0	0	0	0	0	0	0	70035	69760	59709	25	40010	30010	10000	30010	10000	616982	3342206	0	49	66955	70050	70050	64668	3	64975	40010	30020	10000	60410	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	1	71	0	3	1	69844	30003	0	6	0	10000	30010	70036	70051	70051	70036	70051
40024	70035	525	0	0	0	0	0	0	0	1	0	0	70020	69728	59709	25	40010	30013	10000	30010	10000	616982	3342206	0	49	67028	70047	70047	64653	3	64960	40010	30020	10000	60020	10000	70038	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	2520	1	17	0	1	1	69813	30003	9	6	9	10000	30010	70048	70048	70036	70048	70048
40024	70047	524	0	0	0	0	0	0	1	1	0	0	70035	69743	59695	25	40014	30010	10001	30010	10000	616982	3342206	0	49	66970	70035	70035	64668	3	64960	40010	30020	10000	60020	10000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	2520	1	71	0	1	1	69816	30000	9	9	9	10000	30010	70051	70036	70051	70036	70036
40024	70047	524	0	0	0	0	0	1	1	1	0	0	70035	69760	59709	25	40014	30013	10001	30010	10000	617068	3342206	0	49	66967	70050	70050	64668	3	64975	40010	30020	10000	60020	10000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2520	1	71	0	1	1	69817	30003	0	0	9	10000	30010	70051	70056	70051	70051	70036

Test 3: throughput

Count: 8

Code:

  ldrsb x0, [x6]
  ldrsb x0, [x6]
  ldrsb x0, [x6]
  ldrsb x0, [x6]
  ldrsb x0, [x6]
  ldrsb x0, [x6]
  ldrsb x0, [x6]
  ldrsb x0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26723	200	0	0	0	1	0	45	1	0	2	26712	2	18	0	12	25	80100	100	80000	100	80000	500	1165789	0	0	49	23642	26727	26727	16630	3	16685	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	1	100	80000	0	0	0	80039	1	0	42	80000	6	0	35	0	0	0	5110	2	16	1	1	26734	10	6	4	80000	100	26708	26728	26728	26723	26728
80204	26727	200	0	0	0	0	0	50	1	0	0	26707	2	0	18	12	25	80100	100	80000	100	80000	500	1167808	0	0	49	23627	26722	26707	16645	3	16665	80100	200	80000	200	80000	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	0	80035	0	0	35	80035	6	1	0	39	0	0	5110	1	16	1	1	26723	0	6	2	80000	100	26723	26728	26708	26723	26728
80204	26727	200	0	0	0	0	0	41	1	0	1	26707	2	18	18	12	25	80100	100	80000	100	80000	500	1167808	0	0	49	23642	26722	26722	16645	3	16680	80100	200	80000	200	80000	26727	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	80035	6	1	35	39	0	0	5110	1	16	1	1	26724	10	0	4	80000	100	26728	26728	26728	26708	26728
80204	26722	200	0	0	0	0	0	45	1	0	2	26712	2	12	12	12	25	80100	100	80000	100	80000	500	1166525	0	0	49	23647	26727	26727	16650	3	16665	80100	200	80000	200	80000	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80039	0	0	36	80035	0	0	39	43	0	0	5110	1	16	1	1	26733	0	6	0	80000	100	26728	26728	26728	26708	26728
80204	26707	200	0	0	0	0	0	45	1	0	1	26712	0	0	12	12	25	80100	100	80000	100	80000	500	1167231	0	0	49	23647	26727	26727	16630	3	16665	80100	200	80000	200	80000	26707	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	31	80132	0	0	0	80035	0	1	0	0	0	0	5110	1	16	1	1	26709	10	10	4	80000	100	26728	26708	26728	26723	26730
80204	26722	200	0	0	0	0	0	0	0	0	0	26707	0	18	18	12	25	80100	100	80000	100	80000	500	1167808	1	0	49	23642	26822	26727	16630	3	16680	80100	200	80000	200	80000	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	80035	0	1	35	39	0	0	5110	1	16	1	1	26721	6	6	0	80000	100	26708	26723	26723	26723	26723
80204	26707	200	0	0	0	0	0	42	1	0	0	26707	2	18	18	12	25	80100	100	80000	100	80000	500	1167231	0	0	49	23642	26707	26727	16650	3	16665	80100	200	80000	200	80000	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	35	80035	6	1	35	0	0	0	5110	1	16	1	1	26719	6	6	2	80000	100	26723	26708	26723	26708	26723
80204	26722	200	0	0	0	0	0	0	0	0	0	26716	3	18	0	12	25	80100	100	80000	100	80000	500	1167808	1	0	49	23642	26722	26722	16630	3	16680	80100	200	80000	200	80000	26722	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	80035	0	0	35	39	0	0	5110	1	16	0	1	26719	0	6	4	80000	100	26708	26723	26723	26723	26723
80204	26707	200	0	0	0	0	0	41	0	0	1	26712	2	18	12	16	25	80100	100	80000	100	80000	500	1165789	0	0	49	23627	26727	26727	16645	3	16685	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	35	80000	6	1	35	43	0	0	5110	1	16	1	1	26719	0	6	0	80000	100	26723	26723	26723	26708	26708
80204	26722	200	0	0	0	0	0	0	1	0	1	26692	2	18	18	0	25	80100	100	80000	100	80000	500	1166525	0	0	49	23627	26722	26722	16645	3	16683	80100	200	80000	200	80000	26722	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	0	80035	0	0	0	80035	6	1	0	39	0	0	5110	1	16	1	1	26763	0	6	2	80000	100	26725	26723	26723	26723	26723

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	0	1	41	1	0	1	26707	0	18	0	11	25	80010	10	80000	10	80000	50	1167605	1	49	23647	26722	26722	16667	3	16702	80010	20	80000	20	80769	26734	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80035	0	0	80035	6	1	0	39	5020	8	16	0	10	5	26705	10	6	0	80000	10	26709	26709	26709	26728	26728
80024	26722	200	0	0	45	1	0	0	26712	2	0	12	12	25	80010	10	80000	10	80000	50	1168843	1	49	23647	26708	26727	16667	3	16722	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	3	80035	6	1	35	0	5020	12	16	0	12	6	26719	10	6	0	80000	10	26723	26709	26723	26729	26709
80024	26708	200	0	0	45	0	0	2	26707	2	12	0	16	25	80010	10	80000	10	80000	50	1167605	1	49	23628	26728	26727	16652	3	16708	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	0	80000	6	0	35	43	5020	13	16	0	11	7	26705	10	6	0	80000	10	26709	26723	26709	26709	26728
80024	26708	200	0	0	41	0	0	0	26707	2	0	18	12	25	80010	10	80000	10	80000	50	1166886	1	49	23647	26728	26728	16672	3	16707	80010	20	80000	20	80000	26727	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	35	80039	6	1	35	43	5020	6	16	0	5	6	26724	0	6	4	80000	10	26709	26723	26723	26709	26729
80024	26728	200	0	0	0	0	0	2	26693	2	0	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23628	26708	26722	16667	3	16688	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80039	0	39	80039	6	1	35	39	5020	6	16	0	5	4	26725	0	0	4	80000	10	26729	26709	26729	26728	26728
80024	26728	200	0	0	45	1	0	2	26707	0	12	18	0	25	80010	10	80000	10	80000	50	1168843	1	49	23647	26708	26708	16672	3	16708	80010	20	80579	20	80000	26740	56	1	1	80021	10	9	10	80000	10	80000	1	10	80000	39	80039	1	39	80039	6	1	36	43	5020	7	16	0	6	12	26724	6	10	0	80000	10	26709	26709	26729	26729	26729
80024	26727	200	0	0	45	1	0	1	26707	2	18	18	12	25	80010	10	80000	10	80000	50	1167605	1	49	23642	26722	26722	16652	3	16688	80010	20	80000	20	80000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	45	80000	6	0	35	39	5020	7	16	0	7	7	26705	10	6	4	80000	10	26723	26723	26728	26709	26729
80024	26708	200	0	0	41	0	0	2	26712	2	0	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23628	26728	26727	16672	3	16708	80010	20	80000	20	80000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80035	1	39	80000	6	1	35	43	5020	5	16	0	12	7	26725	0	6	4	80000	10	26729	26728	26728	26729	26709
80024	26727	200	0	0	0	1	0	2	26707	0	0	18	0	25	80010	10	80000	10	80000	50	1166750	1	49	23647	26727	26708	16667	3	16688	80010	20	80000	20	80000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80000	0	39	80039	0	1	35	43	5020	10	16	0	6	6	26724	10	0	4	80000	10	26723	26709	26723	26723	26728
80024	26727	200	0	1	45	0	0	2	26712	2	0	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23628	26728	26722	16667	3	16688	80010	20	80000	20	80000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	39	80039	0	38	80035	6	0	35	43	5020	6	16	0	7	5	26724	10	10	0	80000	10	26723	26820	26709	26728	26729

LDRSB (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations