Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ldrb w0, [x6, w7, sxtw]
mov x7, #4 mov x8, 0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | 0e | 0f | 1e | 22 | 23 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int load (95) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | f5 | f6 | f7 | f8 | fd |
| 1005 | 403 | 3 | 0 | 0 | 44 | 1 | 0 | 0 | 0 | 379 | 2 | 1 | 0 | 16 | 25 | 1000 | 1000 | 1000 | 14989 | 398 | 394 | 217 | 3 | 255 | 1000 | 1000 | 2000 | 374 | 56 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1000 | 43 | 1000 | 32 | 0 | 1038 | 6 | 1 | 39 | 43 | 73 | 1 | 16 | 1 | 1 | 391 | 13 | 10 | 7 | 1000 | 406 | 375 | 407 | 399 | 399 |
| 1004 | 394 | 3 | 0 | 0 | 44 | 0 | 0 | 0 | 1 | 383 | 0 | 1 | 0 | 19 | 25 | 1000 | 1000 | 1000 | 15208 | 394 | 398 | 221 | 3 | 232 | 1000 | 1000 | 2000 | 398 | 56 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1000 | 44 | 1038 | 0 | 38 | 1000 | 0 | 1 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 371 | 10 | 14 | 0 | 1000 | 381 | 375 | 415 | 375 | 401 |
| 1004 | 398 | 2 | 0 | 0 | 53 | 1 | 0 | 0 | 0 | 383 | 2 | 0 | 1 | 19 | 25 | 1000 | 1000 | 1000 | 15208 | 374 | 398 | 221 | 3 | 256 | 1000 | 1000 | 2000 | 398 | 56 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 0 | 1000 | 0 | 0 | 1038 | 6 | 1 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 371 | 13 | 10 | 4 | 1000 | 399 | 375 | 399 | 399 | 399 |
| 1004 | 374 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 383 | 2 | 0 | 1 | 19 | 25 | 1000 | 1000 | 1000 | 15267 | 399 | 398 | 221 | 3 | 256 | 1000 | 1000 | 2000 | 398 | 56 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1000 | 43 | 1038 | 0 | 39 | 1038 | 6 | 1 | 39 | 0 | 73 | 1 | 16 | 1 | 1 | 395 | 10 | 10 | 5 | 1000 | 399 | 395 | 399 | 399 | 395 |
| 1004 | 398 | 3 | 0 | 0 | 44 | 0 | 0 | 0 | 1 | 383 | 2 | 1 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 15274 | 398 | 398 | 197 | 3 | 256 | 1000 | 1000 | 2000 | 398 | 77 | 1 | 1 | 1001 | 1000 | 1000 | 1 | 1000 | 0 | 1000 | 0 | 38 | 1038 | 6 | 0 | 38 | 44 | 73 | 1 | 16 | 1 | 1 | 371 | 13 | 0 | 0 | 1000 | 399 | 399 | 399 | 375 | 375 |
| 1004 | 398 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 383 | 2 | 1 | 1 | 19 | 25 | 1000 | 1000 | 1000 | 15208 | 398 | 398 | 221 | 3 | 256 | 1000 | 1000 | 2000 | 374 | 77 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 0 | 1038 | 1 | 38 | 1038 | 6 | 1 | 0 | 0 | 73 | 1 | 16 | 1 | 1 | 391 | 10 | 10 | 7 | 1000 | 375 | 378 | 399 | 399 | 399 |
| 1004 | 398 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 383 | 0 | 1 | 1 | 20 | 25 | 1000 | 1000 | 1000 | 15274 | 398 | 398 | 197 | 3 | 232 | 1000 | 1000 | 2000 | 398 | 56 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 0 | 1038 | 0 | 0 | 1038 | 6 | 1 | 39 | 44 | 73 | 1 | 16 | 1 | 1 | 395 | 10 | 14 | 7 | 1000 | 399 | 399 | 399 | 399 | 399 |
| 1004 | 374 | 3 | 0 | 1 | 44 | 0 | 0 | 0 | 1 | 379 | 2 | 1 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 15208 | 374 | 374 | 221 | 3 | 256 | 1000 | 1000 | 2000 | 398 | 77 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1000 | 0 | 38 | 1038 | 6 | 1 | 38 | 43 | 73 | 1 | 16 | 1 | 1 | 371 | 10 | 10 | 7 | 1000 | 402 | 399 | 375 | 375 | 395 |
| 1004 | 394 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 359 | 2 | 1 | 0 | 0 | 25 | 1000 | 1000 | 1000 | 14060 | 398 | 374 | 221 | 3 | 256 | 1000 | 1000 | 2000 | 394 | 77 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 43 | 1038 | 0 | 0 | 1038 | 0 | 0 | 39 | 44 | 73 | 1 | 16 | 1 | 1 | 371 | 0 | 0 | 7 | 1000 | 375 | 399 | 399 | 399 | 375 |
| 1004 | 374 | 3 | 0 | 0 | 44 | 1 | 0 | 0 | 1 | 383 | 2 | 0 | 1 | 0 | 25 | 1000 | 1000 | 1000 | 14060 | 398 | 374 | 199 | 3 | 256 | 1000 | 1000 | 2000 | 398 | 77 | 1 | 1 | 1001 | 1000 | 1000 | 0 | 1000 | 44 | 1000 | 0 | 39 | 1038 | 6 | 1 | 39 | 43 | 73 | 1 | 16 | 1 | 1 | 395 | 13 | 14 | 7 | 1000 | 399 | 399 | 399 | 399 | 399 |
Chain cycles: 3
Code:
ldrb w0, [x6, w7, sxtw] eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x7, #4 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.0057
| retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40205 | 70057 | 525 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 70036 | 69782 | 59713 | 25 | 40104 | 30103 | 10002 | 30100 | 10000 | 616041 | 3341470 | 1 | 49 | 67013 | 70431 | 70067 | 64681 | 3 | 64960 | 40100 | 30200 | 10000 | 60200 | 20000 | 70041 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10004 | 2 | 0 | 10002 | 1 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69820 | 30006 | 13 | 10 | 13 | 10000 | 30100 | 70058 | 70061 | 70061 | 70061 | 70061 |
| 40204 | 70057 | 525 | 1 | 1 | 1 | 0 | 1 | 2 | 0 | 0 | 70045 | 69791 | 59716 | 25 | 40108 | 30106 | 10001 | 30100 | 10000 | 616078 | 3342686 | 1 | 49 | 67030 | 70060 | 70057 | 64656 | 3 | 64963 | 40100 | 30200 | 10000 | 60200 | 20000 | 70060 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 1 | 0 | 10002 | 8 | 0 | 1 | 10000 | 0 | 1 | 0 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69823 | 30006 | 0 | 13 | 10 | 10000 | 30100 | 70042 | 70058 | 70058 | 70061 | 70058 |
| 40204 | 70060 | 525 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 70026 | 69791 | 59719 | 25 | 40108 | 30103 | 10002 | 30100 | 10000 | 616095 | 3341769 | 1 | 49 | 66966 | 70058 | 70057 | 64656 | 3 | 64963 | 40100 | 30200 | 10000 | 60200 | 20000 | 70060 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 100 | 10002 | 1 | 1 | 10002 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69817 | 30003 | 10 | 0 | 13 | 10000 | 30100 | 70061 | 70135 | 70062 | 70049 | 70061 |
| 40204 | 70041 | 524 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 70036 | 69785 | 59713 | 25 | 40100 | 30100 | 10000 | 30100 | 10000 | 616041 | 3342254 | 1 | 49 | 66993 | 70035 | 70035 | 64650 | 3 | 64957 | 40100 | 30200 | 10000 | 60200 | 20000 | 70035 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 2610 | 1 | 71 | 1 | 1 | 69814 | 30003 | 13 | 10 | 13 | 10000 | 30100 | 70052 | 70055 | 70036 | 70036 | 70036 |
| 40204 | 70035 | 525 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 70045 | 69791 | 59719 | 25 | 40108 | 30106 | 10001 | 30100 | 10000 | 616095 | 3342686 | 1 | 49 | 67006 | 70057 | 70057 | 64653 | 3 | 64963 | 40100 | 30200 | 10000 | 60200 | 20000 | 70041 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 2 | 0 | 10002 | 0 | 2 | 1 | 10000 | 1 | 1 | 0 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69823 | 30006 | 0 | 13 | 13 | 10000 | 30100 | 70042 | 70061 | 70042 | 70042 | 70061 |
| 40204 | 70041 | 524 | 1 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 70042 | 69791 | 59716 | 25 | 40104 | 30106 | 10002 | 30100 | 10000 | 616068 | 3341769 | 1 | 49 | 66989 | 70083 | 70062 | 64653 | 3 | 65016 | 40100 | 30200 | 10000 | 60200 | 20000 | 70041 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10002 | 3 | 1 | 10003 | 0 | 1 | 1 | 10000 | 0 | 1 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69823 | 30003 | 0 | 10 | 13 | 10000 | 30100 | 70046 | 70046 | 70058 | 70064 | 70042 |
| 40204 | 70042 | 525 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 70042 | 69791 | 59719 | 25 | 40108 | 30106 | 10002 | 30100 | 10000 | 616095 | 3342686 | 1 | 49 | 67010 | 70041 | 70060 | 64656 | 3 | 64963 | 40100 | 30200 | 10000 | 60200 | 20000 | 70060 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 2 | 1 | 10001 | 0 | 0 | 1 | 10000 | 1 | 1 | 0 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69820 | 30006 | 13 | 13 | 0 | 10000 | 30100 | 70058 | 70061 | 70058 | 70058 | 70058 |
| 40204 | 70060 | 524 | 1 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 70026 | 69791 | 59701 | 25 | 40104 | 30106 | 10001 | 30100 | 10000 | 616068 | 3341769 | 1 | 49 | 66986 | 70041 | 70060 | 64653 | 3 | 64944 | 40100 | 30200 | 10000 | 60200 | 20000 | 70060 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10001 | 1 | 1 | 10001 | 0 | 2 | 1 | 10000 | 0 | 1 | 1 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69804 | 30003 | 13 | 13 | 13 | 10000 | 30100 | 70042 | 70061 | 70061 | 70066 | 70042 |
| 40204 | 70060 | 524 | 1 | 1 | 1 | 0 | 0 | 2 | 0 | 1 | 70042 | 69791 | 59719 | 25 | 40104 | 30103 | 10002 | 30100 | 10000 | 616078 | 3342686 | 1 | 49 | 67006 | 70060 | 70041 | 64656 | 3 | 64963 | 40100 | 30200 | 10000 | 60200 | 20000 | 70041 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10003 | 1 | 1 | 10001 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69820 | 30006 | 0 | 0 | 13 | 10000 | 30100 | 70061 | 70058 | 70061 | 70061 | 70058 |
| 40204 | 70060 | 525 | 1 | 0 | 1 | 1 | 0 | 2 | 0 | 0 | 70042 | 69702 | 59719 | 25 | 40104 | 30106 | 10002 | 30100 | 10000 | 616095 | 3341769 | 1 | 49 | 67013 | 70041 | 70060 | 64656 | 3 | 64963 | 40100 | 30200 | 10000 | 60200 | 20000 | 70041 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10002 | 2 | 1 | 10002 | 0 | 2 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69820 | 30006 | 13 | 0 | 10 | 10000 | 30100 | 70058 | 70061 | 70042 | 70061 | 70042 |
Result (median cycles for code, minus 3 chain cycles): 4.0047
| retire uop (01) | cycle (02) | 03 | 09 | 0e | 0f | 1e | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40025 | 70047 | 525 | 1 | 0 | 1 | 1 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10002 | 30010 | 10000 | 616952 | 3342062 | 1 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 3 | 71 | 2 | 3 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 1 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617068 | 3342062 | 1 | 49 | 66967 | 70047 | 70035 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 2 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70036 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 0 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10051 | 619298 | 3342062 | 1 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 1 | 6 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 2 | 3 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 525 | 0 | 1 | 0 | 43 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 70035 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 2 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70036 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 525 | 0 | 0 | 0 | 1 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40010 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 3 | 71 | 2 | 3 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 525 | 0 | 0 | 0 | 1 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30161 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 2 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70051 |
| 40024 | 70047 | 525 | 0 | 1 | 1 | 1 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 1 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 2 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 210 | 1 | 0 | 70020 | 69728 | 59707 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 3 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 2 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 1 | 1 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3341470 | 0 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 3 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 1 | 0 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 70047 | 70047 | 64665 | 3 | 64972 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 2 | 71 | 2 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
Chain cycles: 3
Code:
ldrb w0, [x6, w7, sxtw] eor x8, x8, x0 eor x8, x8, x0 add x7, x7, x8
mov x7, #4 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 4.0051
| retire uop (01) | cycle (02) | 03 | 09 | 0f | 18 | 19 | 1e | 22 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40205 | 70051 | 525 | 1 | 1 | 0 | 0 | 1 | 1 | 70020 | 69782 | 59695 | 25 | 40104 | 30103 | 10002 | 30100 | 10000 | 616014 | 3342254 | 49 | 66971 | 70051 | 70054 | 64647 | 3 | 64954 | 40100 | 30200 | 10000 | 60200 | 20000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 1 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69798 | 30003 | 10 | 10 | 0 | 10000 | 30100 | 70052 | 70052 | 70052 | 70052 | 70052 |
| 40204 | 70051 | 525 | 0 | 1 | 0 | 0 | 1 | 1 | 70020 | 69782 | 59710 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616014 | 3342254 | 49 | 66989 | 70051 | 70051 | 64631 | 3 | 64938 | 40100 | 30200 | 10000 | 60200 | 20000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 17 | 1 | 1 | 69800 | 30003 | 0 | 10 | 10 | 10000 | 30100 | 70052 | 70052 | 70052 | 70052 | 70052 |
| 40204 | 70051 | 525 | 0 | 1 | 0 | 0 | 6 | 1 | 70036 | 69782 | 59710 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 616014 | 3342254 | 49 | 66971 | 70051 | 70051 | 64647 | 3 | 64938 | 40100 | 30200 | 10000 | 60200 | 20000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69815 | 30003 | 10 | 10 | 0 | 10000 | 30100 | 70052 | 70036 | 70052 | 70052 | 70052 |
| 40204 | 70035 | 524 | 0 | 1 | 0 | 0 | 1 | 1 | 70020 | 69782 | 59710 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 616175 | 3342254 | 49 | 66971 | 70051 | 70051 | 64647 | 3 | 64938 | 40100 | 30200 | 10000 | 60200 | 20000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69814 | 30003 | 10 | 0 | 10 | 10000 | 30100 | 70052 | 70036 | 70052 | 70052 | 70052 |
| 40204 | 70051 | 524 | 0 | 1 | 0 | 0 | 1 | 1 | 70036 | 69764 | 59710 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616014 | 3342254 | 49 | 66971 | 70035 | 70051 | 64647 | 3 | 64954 | 40100 | 30200 | 10000 | 60200 | 20000 | 70035 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69814 | 30003 | 10 | 10 | 10 | 10000 | 30100 | 70052 | 70052 | 70052 | 70052 | 70052 |
| 40204 | 70051 | 524 | 0 | 1 | 0 | 0 | 0 | 0 | 70036 | 69782 | 59710 | 25 | 40100 | 30103 | 10001 | 30100 | 10000 | 616014 | 3342302 | 49 | 66973 | 70035 | 70051 | 64631 | 3 | 64954 | 40100 | 30200 | 10000 | 60200 | 20000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69814 | 30000 | 0 | 10 | 0 | 10000 | 30100 | 70036 | 70052 | 70052 | 70052 | 70052 |
| 40204 | 70051 | 525 | 0 | 1 | 0 | 0 | 0 | 0 | 70036 | 69764 | 59710 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616175 | 3341470 | 49 | 66955 | 70051 | 70051 | 64647 | 3 | 64938 | 40100 | 30200 | 10000 | 60200 | 20000 | 70035 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69814 | 30003 | 10 | 10 | 10 | 10000 | 30100 | 70036 | 70052 | 70052 | 70052 | 70052 |
| 40204 | 70051 | 525 | 0 | 1 | 0 | 0 | 1 | 1 | 70043 | 69782 | 59710 | 25 | 40104 | 30100 | 10001 | 30100 | 10000 | 616175 | 3342254 | 49 | 66971 | 70054 | 70055 | 64680 | 3 | 64954 | 40100 | 30200 | 10000 | 60200 | 20000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 2610 | 1 | 71 | 1 | 1 | 69798 | 30003 | 10 | 10 | 10 | 10000 | 30100 | 70052 | 70052 | 70052 | 70052 | 70036 |
| 40204 | 70051 | 543 | 0 | 1 | 0 | 0 | 1 | 1 | 70036 | 69782 | 59695 | 25 | 40104 | 30100 | 10001 | 30100 | 10000 | 616014 | 3342254 | 49 | 66971 | 70051 | 70035 | 64631 | 3 | 64938 | 40100 | 30200 | 10000 | 60200 | 20000 | 70035 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 2610 | 1 | 71 | 1 | 1 | 69814 | 30003 | 10 | 10 | 10 | 10000 | 30100 | 70052 | 70036 | 70052 | 70052 | 70052 |
| 40204 | 70051 | 524 | 0 | 1 | 0 | 0 | 1 | 1 | 70036 | 69764 | 59710 | 25 | 40104 | 30103 | 10001 | 30100 | 10000 | 616014 | 3342254 | 49 | 66971 | 70051 | 70051 | 64647 | 3 | 64938 | 40100 | 30200 | 10000 | 60200 | 20000 | 70051 | 35 | 1 | 1 | 40201 | 100 | 99 | 100 | 10000 | 30100 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 1 | 2610 | 1 | 71 | 1 | 1 | 69798 | 30000 | 10 | 10 | 10 | 10000 | 30100 | 70052 | 70036 | 70036 | 70052 | 70052 |
Result (median cycles for code, minus 3 chain cycles): 4.0047
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 24 | 3a | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cf | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 40025 | 70047 | 525 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 0 | 0 | 0 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 0 | 70047 | 70047 | 64665 | 0 | 3 | 64984 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 1 | 2 | 71 | 1 | 1 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70036 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10000 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 0 | 70047 | 70047 | 64653 | 0 | 3 | 65001 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 2520 | 0 | 3 | 71 | 1 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 0 | 70047 | 70035 | 64711 | 0 | 3 | 65000 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 0 | 1 | 71 | 1 | 1 | 69810 | 30003 | 0 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | 0 | 0 | 0 | 70032 | 69728 | 59706 | 50 | 40027 | 30025 | 10001 | 30010 | 10000 | 617068 | 3342062 | 1 | 49 | 66967 | 0 | 70047 | 70047 | 64665 | 0 | 3 | 64973 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 0 | 1 | 71 | 2 | 1 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70036 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30010 | 10000 | 30010 | 10000 | 616952 | 3341470 | 0 | 49 | 66967 | 0 | 70047 | 70047 | 64653 | 0 | 3 | 65027 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 0 | 1 | 71 | 1 | 1 | 69810 | 30003 | 0 | 6 | 0 | 10000 | 30010 | 70036 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3341470 | 0 | 49 | 66967 | 0 | 70047 | 70047 | 64668 | 0 | 3 | 65000 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 2520 | 0 | 1 | 71 | 1 | 1 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70036 | 70048 | 70048 | 70036 |
| 40024 | 70035 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 70032 | 69743 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 0 | 49 | 66967 | 0 | 70047 | 70047 | 64653 | 0 | 3 | 65027 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 0 | 1 | 71 | 1 | 1 | 69810 | 30003 | 6 | 0 | 6 | 10000 | 30010 | 70048 | 70036 | 70048 | 70048 | 70048 |
| 40024 | 70047 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 70032 | 69728 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 616952 | 3342062 | 1 | 49 | 66967 | 0 | 70047 | 70047 | 64665 | 0 | 3 | 64994 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 0 | 1 | 71 | 1 | 2 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70048 | 70048 |
| 40024 | 70035 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 70020 | 69728 | 59706 | 25 | 40027 | 30013 | 10000 | 30010 | 10000 | 617068 | 3342206 | 0 | 49 | 66967 | 0 | 70047 | 70047 | 64665 | 0 | 3 | 64973 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 1 | 0 | 10000 | 1 | 1 | 0 | 2520 | 0 | 1 | 71 | 1 | 1 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70056 | 70048 | 70048 | 70049 | 70048 |
| 40024 | 70047 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 70032 | 69782 | 59706 | 25 | 40014 | 30013 | 10001 | 30010 | 10000 | 617068 | 3342062 | 0 | 49 | 66967 | 0 | 70047 | 70035 | 64656 | 0 | 3 | 65007 | 40010 | 30020 | 10000 | 60020 | 20000 | 70047 | 35 | 1 | 1 | 40021 | 10 | 9 | 10 | 10000 | 30010 | 10000 | 1 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 2520 | 0 | 1 | 71 | 1 | 1 | 69810 | 30003 | 6 | 6 | 6 | 10000 | 30010 | 70048 | 70048 | 70048 | 70051 | 70048 |
Count: 8
Code:
ldrb w0, [x6, w7, sxtw] ldrb w0, [x6, w7, sxtw] ldrb w0, [x6, w7, sxtw] ldrb w0, [x6, w7, sxtw] ldrb w0, [x6, w7, sxtw] ldrb w0, [x6, w7, sxtw] ldrb w0, [x6, w7, sxtw] ldrb w0, [x6, w7, sxtw]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.3341
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80205 | 26737 | 200 | 0 | 1 | 1 | 45 | 1 | 0 | 1 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1167303 | 49 | 23631 | 26733 | 26717 | 16635 | 6 | 16659 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 77 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 1 | 100 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 39 | 80000 | 6 | 1 | 0 | 0 | 1 | 1 | 1 | 5118 | 2 | 16 | 0 | 0 | 26724 | 0 | 10 | 10 | 0 | 80000 | 100 | 26728 | 26728 | 26728 | 26728 | 26728 |
| 80204 | 26707 | 200 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 26712 | 0 | 0 | 12 | 0 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1165856 | 49 | 23652 | 26736 | 26729 | 16655 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26727 | 77 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 39 | 80000 | 0 | 1 | 39 | 43 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26704 | 0 | 0 | 10 | 4 | 80000 | 100 | 26708 | 26728 | 26708 | 26728 | 26708 |
| 80204 | 26727 | 200 | 0 | 0 | 1 | 48 | 0 | 0 | 1 | 26692 | 0 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166596 | 49 | 23627 | 26734 | 26727 | 16635 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 56 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 0 | 80039 | 0 | 1 | 38 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 1 | 1 | 26729 | 0 | 0 | 10 | 4 | 80000 | 100 | 26708 | 26728 | 26728 | 26708 | 26708 |
| 80204 | 26707 | 200 | 0 | 0 | 1 | 45 | 0 | 0 | 1 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1165856 | 49 | 23655 | 26707 | 26727 | 16635 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26707 | 56 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 0 | 58 | 43 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 1 | 26704 | 0 | 0 | 10 | 4 | 80000 | 100 | 26728 | 26708 | 26728 | 26728 | 26708 |
| 80204 | 26727 | 200 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 26692 | 2 | 1 | 0 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80016 | 500 | 1166596 | 49 | 23636 | 26716 | 26727 | 16655 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26727 | 56 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 0 | 80039 | 6 | 0 | 0 | 43 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26704 | 0 | 0 | 14 | 7 | 80000 | 100 | 26728 | 26728 | 26732 | 26732 | 26732 |
| 80204 | 26727 | 200 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 26712 | 2 | 0 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80014 | 500 | 1167303 | 49 | 23634 | 26707 | 26727 | 16635 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26727 | 77 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 0 | 80039 | 6 | 0 | 39 | 43 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26724 | 0 | 10 | 10 | 0 | 80000 | 100 | 26728 | 26728 | 26728 | 26728 | 26728 |
| 80204 | 26727 | 200 | 0 | 0 | 1 | 45 | 1 | 0 | 1 | 26712 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1166596 | 49 | 23635 | 26727 | 26727 | 16635 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26727 | 77 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 0 | 1 | 0 | 43 | 1 | 1 | 1 | 5118 | 0 | 16 | 0 | 0 | 26724 | 0 | 10 | 0 | 0 | 80000 | 100 | 26728 | 26728 | 26728 | 26708 | 26728 |
| 80204 | 26707 | 200 | 0 | 0 | 1 | 45 | 0 | 0 | 1 | 26712 | 2 | 0 | 0 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80015 | 500 | 1167303 | 49 | 23952 | 26797 | 26709 | 16655 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26727 | 77 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80000 | 0 | 0 | 39 | 80039 | 6 | 0 | 0 | 0 | 1 | 1 | 1 | 5118 | 1 | 16 | 0 | 0 | 26724 | 0 | 0 | 0 | 0 | 80000 | 100 | 26708 | 26728 | 26728 | 26728 | 26728 |
| 80204 | 26727 | 200 | 0 | 0 | 1 | 45 | 0 | 0 | 1 | 26712 | 0 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80016 | 500 | 1165856 | 49 | 23778 | 26785 | 26729 | 16656 | 6 | 16679 | 80115 | 200 | 80024 | 200 | 160048 | 26727 | 56 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 0 | 0 | 80039 | 0 | 0 | 39 | 80039 | 0 | 0 | 39 | 0 | 1 | 1 | 1 | 5118 | 0 | 16 | 1 | 1 | 26705 | 0 | 10 | 10 | 4 | 80000 | 100 | 26728 | 26709 | 26709 | 26728 | 26728 |
| 80204 | 26711 | 200 | 0 | 0 | 1 | 69 | 0 | 1 | 1 | 26693 | 2 | 12 | 12 | 16 | 25 | 80100 | 100 | 80000 | 100 | 80021 | 500 | 1166714 | 49 | 23817 | 26715 | 26714 | 16648 | 10 | 16666 | 80121 | 200 | 80030 | 200 | 160060 | 26731 | 77 | 1 | 1 | 80201 | 100 | 99 | 100 | 80000 | 100 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 0 | 2 | 2 | 2 | 5128 | 1 | 23 | 2 | 1 | 26724 | 0 | 10 | 10 | 4 | 80000 | 100 | 26728 | 26709 | 26709 | 26831 | 26728 |
Result (median cycles for code divided by count): 0.3341
| retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int load (95) | inst int alu (97) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80025 | 26723 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 0 | 0 | 0 | 26693 | 0 | 12 | 12 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166896 | 1 | 49 | 23628 | 26727 | 26728 | 16672 | 3 | 16707 | 80010 | 20 | 80000 | 20 | 160000 | 26727 | 71 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80035 | 0 | 0 | 42 | 80000 | 6 | 1 | 35 | 0 | 0 | 5020 | 27 | 16 | 26 | 19 | 26725 | 10 | 6 | 0 | 80000 | 10 | 26709 | 26728 | 26728 | 26728 | 26728 |
| 80024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 26693 | 0 | 0 | 0 | 12 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 1 | 49 | 23648 | 26708 | 26708 | 16672 | 3 | 16707 | 80010 | 20 | 80000 | 20 | 160000 | 26727 | 72 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 1 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 35 | 80039 | 6 | 1 | 35 | 43 | 0 | 5020 | 28 | 16 | 15 | 28 | 26725 | 0 | 10 | 4 | 80000 | 10 | 26709 | 26728 | 26709 | 26728 | 26709 |
| 80024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 2 | 26693 | 2 | 12 | 0 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 0 | 49 | 23628 | 26708 | 26728 | 16652 | 3 | 16707 | 80010 | 20 | 80000 | 20 | 160000 | 26727 | 71 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 5020 | 27 | 16 | 15 | 28 | 26719 | 0 | 10 | 0 | 80000 | 10 | 26723 | 26709 | 26723 | 26723 | 26723 |
| 80024 | 26722 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 1 | 0 | 2 | 26713 | 2 | 0 | 12 | 11 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168843 | 0 | 49 | 23628 | 26728 | 26708 | 16672 | 3 | 16707 | 80010 | 20 | 80000 | 20 | 160000 | 26727 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80000 | 0 | 0 | 39 | 80039 | 6 | 0 | 35 | 43 | 0 | 5020 | 27 | 16 | 28 | 28 | 26724 | 10 | 10 | 4 | 80000 | 10 | 26728 | 26728 | 26729 | 26711 | 26728 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 2 | 26707 | 2 | 0 | 12 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1167605 | 0 | 49 | 23628 | 26708 | 26708 | 16672 | 3 | 16707 | 80010 | 20 | 80000 | 20 | 160000 | 26746 | 71 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80000 | 0 | 0 | 0 | 80000 | 6 | 1 | 39 | 43 | 0 | 5020 | 29 | 16 | 29 | 29 | 26705 | 0 | 10 | 0 | 80000 | 10 | 26729 | 26709 | 26709 | 26723 | 26729 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 0 | 26693 | 2 | 0 | 0 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168843 | 0 | 49 | 23628 | 26757 | 26735 | 16672 | 3 | 16688 | 80010 | 20 | 80000 | 20 | 160000 | 26722 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 0 | 0 | 0 | 80035 | 6 | 1 | 35 | 0 | 0 | 5020 | 28 | 16 | 28 | 29 | 26725 | 10 | 0 | 4 | 80000 | 10 | 26709 | 26723 | 26728 | 26709 | 26728 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 2 | 26712 | 2 | 12 | 12 | 16 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168843 | 0 | 49 | 23642 | 26728 | 26708 | 16652 | 3 | 16702 | 80010 | 20 | 80000 | 20 | 160000 | 26722 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80000 | 0 | 0 | 0 | 80039 | 6 | 0 | 0 | 43 | 0 | 5020 | 28 | 16 | 14 | 26 | 26724 | 0 | 0 | 4 | 80000 | 10 | 26728 | 26723 | 26729 | 26729 | 26729 |
| 80024 | 26708 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 2 | 26693 | 2 | 12 | 0 | 11 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1168843 | 0 | 49 | 23628 | 26728 | 26727 | 16652 | 3 | 16707 | 80010 | 20 | 80000 | 20 | 160000 | 26722 | 56 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 39 | 80039 | 1 | 0 | 0 | 80035 | 6 | 1 | 0 | 43 | 0 | 5020 | 28 | 16 | 28 | 27 | 26724 | 0 | 10 | 2 | 80000 | 10 | 26723 | 26728 | 26723 | 26723 | 26728 |
| 80024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 57 | 0 | 0 | 0 | 0 | 26713 | 2 | 12 | 12 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166896 | 0 | 49 | 23648 | 26727 | 26708 | 16672 | 3 | 16710 | 80010 | 20 | 80000 | 20 | 160000 | 26735 | 71 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 43 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 39 | 43 | 0 | 5020 | 15 | 16 | 27 | 16 | 26724 | 10 | 0 | 2 | 80000 | 10 | 26723 | 26723 | 26728 | 26728 | 26709 |
| 80024 | 26727 | 200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 26693 | 2 | 12 | 12 | 0 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 1166750 | 1 | 49 | 23648 | 26727 | 26728 | 16652 | 3 | 16708 | 80010 | 20 | 80000 | 20 | 160000 | 26727 | 71 | 1 | 1 | 80021 | 10 | 9 | 10 | 80000 | 10 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80039 | 0 | 0 | 35 | 80035 | 0 | 0 | 35 | 39 | 0 | 5020 | 30 | 16 | 14 | 28 | 26734 | 10 | 10 | 2 | 80000 | 10 | 26709 | 26728 | 26728 | 26729 | 26729 |