Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (register, ror, 64-bit)

Test 1: uops

Code:

  orr x0, x0, x1, ror #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10042035150000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000732671117812000100020362036203620362036
10042035150000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036
10042035150000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036
10042035150000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036
10042035160000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036
10042035150000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036
10042035150000000082100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036
10042035160000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036
10042035150000000061100017352520002000100032570120352035157531842100010002000203542111001100000001030731671117812000100020362036203620362036
10042035150000000061100017352520002000100032570120352035157531842100010002000203542111001100000000000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  orr x0, x0, x1, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204200351500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110202100991001010010000710159111979120000101002003620036200362003620036
1020420035150002520611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
1020420035150002402511000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
1020420035150001260611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515000006110000198032520100201001010018534214916955200352003518429141870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
10204200351500000611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101010640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310049169552003520035184513187181001010020200202008042111002110910100101003640263221979220000100102003620036200362003620036
1002420035149015761100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
1002420035150000325100001974325200102001010163185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515010961100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310049169552003520035184513187181001010020200202003542111002110910100101000640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  orr x0, x1, x0, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515006110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534249169552003520035184733187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150053610000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003514966110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
1020420035150061100001980325201002010010100185342491695520035200351842917187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003515006110000197422520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534249169552003520035184293187001010010399202002003542111020110099100101001000710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534249169552003520035184293187001010010200202002003542111020110099100101001000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100242003515006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
1002420035150025110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100001640263221979220000100102003620036200362003620036
100242003515008410000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515008410000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515006110000197432520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  orr x0, x8, x9, ror #17
  orr x1, x8, x9, ror #17
  orr x2, x8, x9, ror #17
  orr x3, x8, x9, ror #17
  orr x4, x8, x9, ror #17
  orr x5, x8, x9, ror #17
  orr x6, x8, x9, ror #17
  orr x7, x8, x9, ror #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)033f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426767201618000026094251601001601008010016431814923645267252672516615316677801008020016020026725391180201100991008010010000051103221126717160000801002672626726267262672626726
8020426725200618000026094251601001601008010016431814923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
8020426725201618000026094251601001601008010016431814923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
8020426725200618000026094251601001601008010016431814923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
8020426725200618000026094251601001601008010016431814923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
80204267842005368000026094251601001601008010016431814923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
8020426725200618000026094251601001603748010016431804923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
8020426725200618000026094251601001601008010016431804923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
80204267252005338000026094251601001601008010016431804923645267252672516615316677801008020016020026725391180201100991008010010000051101221126717160000801002672626726267262672626726
80204267252001938000026094251601001601008010016431804923645267252672516615316677801008020016020026725391180201100991008010010013051101221126717160000801002672626726267902672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800242671720100000061800002128025160010160010800101631420049236312671126711166233166858001080020160020267113911800211091080010100000050300010228526704160000800102671226712267122671226712
800242671120000000010580000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005020006226426704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005020005226626704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000005028006226426704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005022007224626704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005020006226626704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005022007225726704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005023008226626704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005025006226426704160000800102671226712267122671226712
80024267112000000006180000212802516001016001080010163142104923631267112671116623316685800108002016002026711391180021109108001010000005020307225626704160000800102671226712267122671226712