Firestorm: XAFLAG measurements

Code:

  xaflag

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	1035	8	0	82	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	4	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	201	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	0	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	0	1035	1035	805	3	882	1000	1000	1000	1035	104	1	1	1001	3	0	73	3	27	3	3	990	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->1

Code:

  xaflag

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	82	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	2	12	0	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	3	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	22	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	135	88	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8757	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	1	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	2	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	76	0	0	0	61	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10035	110	1	1	10201	100	99	100	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	429	9920	25	10200	10200	10200	647652	0	49	6955	10035	10035	8656	3	8732	10200	10200	10200	10127	110	1	1	10201	100	99	100	0	0	0	0	0	0	710	1	27	1	1	9990	10100	100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	76	0	0	0	126	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	83	0	0	12	84	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	2	27	2	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	3	27	3	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	208	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	78	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	2	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	3	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	12	84	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	2	27	3	3	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	130	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	3	27	2	2	9993	10010	10	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10020	10020	10020	647296	49	6955	10035	10035	8678	3	8754	10020	10020	10020	10035	104	1	1	10021	10	9	10	0	0	0	0	640	2	27	3	2	9993	10010	10	10036	10036	10036	10036	10036

Test 3: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag
  ands xzr, xzr, xzr
  xaflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53408	400	0	0	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	0	49	50328	0	53408	53408	33347	6	33357	160128	160240	80220	53408	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	10119	2	16	2	2	53405	160020	100	53409	53409	53409	53409	53409
160204	53408	400	0	0	0	0	0	0	0	0	598	27	160120	160120	160128	1063738	0	49	50328	0	53408	53408	33347	6	33357	160128	160240	80220	53408	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	10119	2	16	2	2	53405	160020	100	53409	53409	53409	53409	53409
160204	53408	400	0	0	0	0	0	0	0	0	28	27	160120	160120	160128	1063738	0	49	50328	0	53408	53408	33347	6	33357	160128	160240	80220	53408	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	10119	2	16	2	2	53405	160020	100	53409	53409	53409	53409	53409
160204	53408	400	0	0	0	16	20	2004	1232	0	3874	453	161488	161570	161592	1021139	0	49	51143	0	54413	53982	33618	95	34005	161670	161855	80730	54459	66	22	1	160201	100	99	100	80100	100	0	0	0	0	0	0	2	0	0	0	10312	16	172	6	4	54206	161302	100	54272	54176	54321	54368	54274
160204	54223	406	2	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	0	10110	2	19	2	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	399	0	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	0	10110	2	19	2	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	0	10110	2	19	2	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	0	208	25	160100	160100	160100	1063588	0	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	0	10110	2	19	2	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	0	10110	2	19	2	2	53400	160000	100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	6	0	0	597	25	160100	160100	160100	1063588	1	49	50324	0	53404	53404	33339	3	33359	160100	160200	80200	53404	66	1	1	160201	100	99	100	80100	100	0	0	0	0	0	0	0	0	0	0	10110	2	19	6	2	53400	160000	100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53403	399	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	2	0	17	19	2	1	1	4	9	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	328	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	1	0	6	19	2	1	1	6	5	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10024	6	1	2	0	4	19	4	1	1	9	3	53370	160000	40	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	613	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	1	0	9	19	2	1	2	4	5	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	1	0	6	19	2	1	1	6	5	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	49	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10024	6	2	1	0	6	19	4	1	2	6	3	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	1	0	9	19	2	1	1	6	4	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	400	0	1	0	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	1	0	10	19	2	1	1	10	5	53370	160000	20	11	10	53375	53375	53375	53414	53375
160024	53374	399	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	1	0	9	19	2	1	1	5	5	53370	160000	20	11	10	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	0	3	33351	160010	160020	80020	53374	66	1	1	160021	10	9	10	80010	10	0	0	0	0	10022	3	1	1	0	4	19	2	1	1	6	9	53370	160000	20	11	10	53375	53375	53375	53375	53375

Test 4: throughput

Count: 4

Code:

  fcmp s0, s0
  xaflag
  xaflag
  xaflag
  xaflag

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13416	101	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	13	12	3210	4	19	3	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	45	25	50100	40100	10000	40100	10000	580184	80000	1	13385	13414	13414	6128	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	1	3	3210	3	19	3	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	63	3210	3	19	3	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6128	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	0	3210	4	19	3	4	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6128	2456	16	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	2	0	3210	3	19	3	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	0	3210	3	19	3	4	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6128	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	15	3210	3	19	3	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	101	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6130	2456	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	30	3210	3	19	3	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13414	100	0	45	25	50100	40100	10032	40100	10000	574757	80000	1	13385	13414	13414	6128	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	0	3210	3	19	3	3	13411	40000	100	13415	13415	13415	13415	13415
50204	13462	100	0	45	25	50100	40100	10000	40100	10000	574757	80000	1	13385	13414	13414	6128	2467	3	7119	50100	40200	10000	40200	20000	13414	13414	1	1	50201	100	99	100	100	10000	100	0	0	0	3210	3	19	3	3	13411	40000	100	13415	13415	13415	13415	13415

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13408	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	1	48	3140	4	19	4	7	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	1	153	3140	6	19	5	4	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	3140	5	19	4	4	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	66	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	3140	5	19	5	5	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5577	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	3140	4	19	5	5	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	7	6	3140	5	19	3	5	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	66	3140	5	19	3	5	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	101	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5575	3784	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	3140	5	19	5	6	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	3140	4	19	5	5	13379	40000	10	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5577	3795	3	7109	50010	40020	10000	40020	20000	13382	13382	1	1	50021	10	9	10	10	10000	10	0	0	3140	4	19	6	4	13379	40000	10	13383	13383	13383	13383	13383

XAFLAG

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations