Firestorm: SUBS (uxth, 64-bit) measurements

Code:

  subs x0, x0, w1, uxth

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	103	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	3	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	0	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	16	3	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2073	2036
1004	2035	15	0	61	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	1	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036
1004	2035	15	0	103	1000	1862	25	2000	2000	1000	126235	1	2035	2035	1729	3	1866	1000	1000	2000	2035	41	1	1	1001	1000	0	0	73	0	1	43	1	1	1920	2000	1000	2036	2036	2036	2036	2036

Test 2: Latency 1->2

Code:

  subs x0, x0, w1, uxth

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	3	710	1	39	1	2	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	66	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10208	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	149	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	22	3	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20081	151	1	1	1	156	103	10000	19862	25	20100	20100	10100	1305863	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	49	16955	20035	20035	18581	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	1	3	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	336	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	41	2	2	19930	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 1->3

Code:

  subs x0, x1, w0, uxth

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20035	150	0	0	0	0	103	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18595	0	3	18771	10100	10200	20200	20081	41	1	1	10201	100	99	100	10100	100	0	0	3	710	1	39	2	1	19922	20000	10100	20036	20036	20086	20036	20081
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10349	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	1	3	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	4	9	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	191	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	1	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	61	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	2	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036
10204	20035	150	0	0	0	0	726	10000	19862	25	20100	20100	10100	1305121	0	49	16955	20035	20035	18581	0	3	18720	10100	10200	20200	20035	41	1	1	10201	100	99	100	10100	100	0	0	0	710	1	39	1	1	19922	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20035	150	0	0	0	0	0	458	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	7	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	1	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	0	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	149	0	0	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	82	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	251	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	414	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036
10024	20035	150	0	0	0	0	0	61	10000	19862	25	20010	20010	10010	1305229	0	49	16955	20035	20035	18603	3	18740	10010	10020	20020	20035	41	1	1	10021	10	9	10	10010	10	0	0	0	0	0	0	640	3	41	3	3	19930	20000	10010	20036	20036	20036	20036	20036

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, w2, uxth
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	0	0	0	0	0	0	124	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	1	1	1	1320	0	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29911	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	0	0	0	126	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	8	27485	20183	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	0	0	0	0	0	0	103	10000	29899	25	30100	30100	20183	1956240	49	26955	30305	30352	27460	39	27646	20719	20848	31302	30263	85	9	1	20201	100	99	100	20100	10100	4	0	2	0	1	0	7088	2	1	1	1	1388	0	72	3	0	30221	30155	20100	30355	30353	30353	30354	30403
20204	30355	227	0	0	1	7	8	3	616	983	10042	29928	192	30259	30285	20644	1961295	49	27181	30351	30399	27465	17	27668	20726	20933	31164	30398	85	9	1	20201	100	99	100	20100	10100	0	4	0	0	0	4	8180	0	1	1	1	1441	0	80	2	0	30218	30176	20100	30356	30357	30402	30401	30401
20204	30350	228	2	1	0	8	8	936	264	2156	10048	29935	192	30284	30122	20645	1961257	49	27318	30397	30354	27477	38	27670	20648	20488	31160	30353	85	8	1	20201	100	99	100	20100	10100	4	0	2	1	0	4	9925	0	1	1	1	1417	0	88	1	1	30120	30133	20100	30492	30445	30526	30490	30442
20204	30445	225	0	0	0	9	9	1188	880	3421	10060	29941	237	30303	30307	20805	1962776	49	27459	30490	30444	27488	54	27721	20874	21117	31567	30396	85	10	1	20201	100	99	100	20100	10100	0	0	0	0	0	2	6763	2	1	1	1	1473	0	48	2	0	30288	30224	20100	30491	30491	30172	30492	30488
20204	30441	228	0	0	0	7	5	276	616	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	1	1	1	1320	0	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	0	0	0	0	0	0	61	10000	29899	25	30100	30100	20107	1956240	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	0	1	1	1	1319	0	16	0	0	29982	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30491	228	0	0	11	10	1350	968	3207	10060	29931	262	30274	30230	20774	1964298	0	49	27458	30490	30172	27504	43	27761	20854	21001	31368	30446	85	11	1	20021	10	9	10	20010	10010	4	2	0	3	2	10351	1431	6	105	5	6	30323	30223	20010	30448	30489	30532	30534	30536
20024	30538	228	1	1	10	11	1452	880	2979	10066	29935	238	30230	30253	20776	1964277	0	49	27367	30262	30398	27487	30	27703	20621	20730	30693	30402	85	9	1	20021	10	9	10	20010	10010	0	0	3	0	2	9070	1318	3	106	1	2	30262	30088	20010	30263	30401	30264	30447	30265
20024	30400	225	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956684	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	6	1270	2	33	2	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	2	33	2	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	3	33	2	2	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	2	33	2	2	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	27000	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20022	10	9	10	20010	10010	0	0	0	0	0	0	1270	2	33	3	2	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	2	33	2	3	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	2	33	3	2	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	1270	2	33	2	2	29959	30000	20010	30036	30036	30036	30036	30036

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, w2, uxth
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	1	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	2	0	0	1	1	1	1319	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	0	29982	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	84	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	7	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	170	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27486	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	225	0	61	10000	29899	25	30100	30100	20107	1957711	1	49	26955	30035	30035	27391	7	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	0	29983	30000	20100	30036	30036	30036	30036	30036
20204	30035	224	0	61	10000	29899	25	30100	30100	20107	1956240	1	49	26955	30035	30035	27391	8	27485	20107	20224	30236	30035	85	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	16	0	29983	30000	20100	30036	30036	30036	30036	30036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	123	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30067	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	21	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30081	27402	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	117	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	135	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	1	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	132	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	224	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	138	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	132	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	0	120	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036
20024	30035	225	0	0	0	61	10000	29891	25	30010	30010	20010	1956289	0	49	26955	30035	30035	27391	3	27498	20010	20020	30020	30035	85	1	1	20021	10	9	10	20010	10010	0	4	147	1270	1	33	1	1	29959	30000	20010	30036	30036	30036	30036	30036

Test 6: throughput

Count: 8

Code:

  subs x0, x8, w9, uxth
  subs x1, x8, w9, uxth
  subs x2, x8, w9, uxth
  subs x3, x8, w9, uxth
  subs x4, x8, w9, uxth
  subs x5, x8, w9, uxth
  subs x6, x8, w9, uxth
  subs x7, x8, w9, uxth

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	53449	400	0	0	0	0	0	0	0	0	66	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53461	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	89	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53462	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	2909	12	43395	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	12	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	536	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411
80204	53410	400	0	0	0	0	0	0	0	0	61	80000	48741	25	160100	160100	80100	3440005	1	49	50330	53410	53410	43298	3024	3	43360	80100	80200	160200	53410	39	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	2	24	2	2	53390	160000	80100	53411	53411	53411	53411	53411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	4c	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	53401	400	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	0	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	204	5020	0	0	9	24	7	5	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	0	49	50300	53380	53431	43290	3251	18	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	81	5020	0	0	5	24	5	7	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	1	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	0	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	162	5020	0	0	5	24	5	7	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	0	49	50300	53380	53380	43290	2936	3	43352	80010	80216	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	249	5020	0	0	7	24	7	5	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	61	80000	47946	25	160116	160010	80010	3438130	1	0	49	50300	53380	53380	43290	3251	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	219	5020	0	0	5	24	5	7	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	0	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	219	5020	0	0	7	24	5	7	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	0	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	168	5020	0	0	7	24	7	5	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	399	0	0	0	61	80000	47946	25	160010	160010	80010	3438130	1	5	49	50300	53380	53380	43290	2749	3	43352	80010	80020	160020	53380	82	1	1	80021	10	9	10	80010	10	0	0	174	5020	5	2	5	24	7	5	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	399	0	1	0	61	80000	47946	25	160010	160010	80112	3438130	1	5	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	171	5020	5	2	7	24	5	7	53360	160000	0	80010	53381	53381	53381	53381	53381
80024	53380	400	0	0	0	726	80000	47946	25	160010	160010	80010	3438130	1	5	49	50300	53380	53380	43290	2936	3	43352	80010	80020	160020	53380	39	1	1	80021	10	9	10	80010	10	0	0	234	5020	5	3	7	24	7	5	53360	160000	0	80010	53381	53381	53381	53381	53381

SUBS (uxth, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations