Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMSUBL

Test 1: uops

Code:

  umsubl x0, w0, w1, x2
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10043033240611922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
100430332301031922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
10043033230611922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
100430332401561922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
10043033230611922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
100430332402721922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
10043033250611922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
10043033230611922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
100430332306571922251000100010008144004030333033276032891100010003000303338011100110000732162229391000100030343034303430343034
10043033220611922251000100010008144004030333033276032891100010003000303338011100110001732162229391000100030343034303430343034

Test 2: Latency 1->2

Code:

  umsubl x0, w0, w1, x2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102043003322506119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
1020430033224061199222510100101001010082894049269533003330033286103287411010010200302003003337411102011009910010100100223710116112993910000101003003430034300343003430034
102043003322406119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010020710116112993910000101003003430034300343003430034
102043003322406119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322406119922251010010100101008289404926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322506119922251010010100101008289404926953300333003328610328741101001020030200300333742110201100991001010010040710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100243003322506119922251001010010100108284900492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103003430034300343003430034
100243003322506119922251001010010100108284900492695303003330033286323287631001010020300203003338011100211091010010100001640216222993910000100103003430034300343003430034
100243003322506119922251001010010100108284900492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103003430034300343003430034
100243003322506119922251001010010100108284901492695303003330033286323287631001010020300203003338011100211091010010102000640216222993910000100103003430034300343003430034
100243003322506119922251001010010100108284900492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103003430034300343003430034
100243003322506119922251001010010100108284901492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103003430034300343003430034
100243003322506119922251001010010100108284901492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103007730034300343003430034
100243003322506119922251001010010100108284901492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103003430034300343003430034
1002430033225025319922251001010010100108284900492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103003430034300343003430034
100243003322506119922251001010010100108284900492695303003330033286323287631001010020300203003338011100211091010010100000640216222993910000100103003430034300343003430034

Test 3: Latency 1->3

Code:

  umsubl x0, w1, w0, x2
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102043003322500726199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894014926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332240061199222510100101001010082894014926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332240061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
102043003322500726199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000731116112993910000101003003430034300343003430034
102043003322500346199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332240061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034
10204300332250061199222510100101001010082894004926953300333003328610328741101001020030200300333741110201100991001010010000710116112993910000101003003430034300343003430034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)0309l2 tlb miss data (0b)181e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024300332250000061199222510010100101001082849014926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332250000061199222510010100101001082849004926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332250000061199222510010100101001082849004926953300333003328632328763100101002030020300333801110021109101001010013640216222993910000100103003430034300343003430034
10024300332240000061199222510010100101001082849004926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332250000061199222510010100101001082849004926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332250000061199222510010100101001082849004926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332240000061199222510010100101001082849014926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332240000061199222510010100101001082849014926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332250000061199222510010100101001082849004926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034
10024300332250000061199222510010100101001082849014926953300333003328632328763100101002030020300333801110021109101001010000640216222993910000100103003430034300343003430034

Test 4: Latency 1->4

Code:

  umsubl x0, w1, w2, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0037

retire uop (01)cycle (02)0318193f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020410040750053671010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010000710216111003310000101001003810038100381003810038
1020410037750048251010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010006710116111003310000101001003810038100381003810038
10204100377500398251010010100101007049804969571003710037871438745101001020030200100373331110201100991001010010000710116111003310000101001003810038100381003810038
10204100377500692510100101001010070498049695710037100378714387451010010200302001003716211102011009910010100100036710116111003310000101001003810038100381003810038
10204100377600754251010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010000710116111003310000101001003810038100381003810038
1020410037750048251010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010000710116111003310000101001003810038100381003810038
10204100377500220251010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010000710116111003310000101001003810038100381003810038
1020410037750048251010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010000710116111003310000101001003810038100381003810038
1020410037750048251010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010000710116111003310000101001003810038100381003810038
1020410037750048251010010100101007049804969571003710037871438745101001020030200100371621110201100991001010010040710116111003310000101001003810038100381003810038

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0037

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024100377504825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
100241003775023825100101001010010700480496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
10024100377504825100101001010010700480496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
10024100377504825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
10024100377504825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
10024100377504825100101001010010700481496957100371003787363876710010100203015210037164111002110910100101000640216221003310000100101003810038100381003810038
10024100377504825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
1002410037750188225100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
10024100377504825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038
100241003775023825100101001010010700481496957100371003787363876710010100203002010037164111002110910100101000640216221003310000100101003810038100381003810038

Test 5: throughput

Count: 8

Code:

  umsubl x0, w8, w9, x9
  umsubl x1, w8, w9, x9
  umsubl x2, w8, w9, x9
  umsubl x3, w8, w9, x9
  umsubl x4, w8, w9, x9
  umsubl x5, w8, w9, x9
  umsubl x6, w8, w9, x9
  umsubl x7, w8, w9, x9
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020480036599000004625801008010080100400500149769550800358003569964369993801008020024020080035164118020110099100801001001005110216118003180000801008003680036800368003680036
8020480035599000004625801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
8020480035599000004646801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
8020480035599000004625801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
8020480035599000004625801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
8020480035600000004625801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
80204800356000003033125801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
8020480035599000004625801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
8020480035599000004625801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110116118003180000801008003680036800368003680036
80204800355990000071125801008010080100400500049769550800358003569964369993801008020024020080035164118020110099100801001000005110016118003180000801008003680036800368003680036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002480036599345462580010800108001040005000497695508003580035699863700158001080020240020800351641180021109108001010000502011160788003280000800108003680036800368003680036
8002480035600424625800108001080010400050014976955080035800356998637001580010800202400208003516411800211091080010100005020121601388003280000800108003680036800368003680036
800248003559939462580010800108001040005000497695508003580035699863700158001080020240020800351641180021109108001010000502061605128003280000800108003680036800368003680036
8002480035600394625800108001080010400050014976955080035800356998637001580010800202400208003516411800211091080010100005020131611158003280000800108003680036800368003680036
80024800356003046258001080010800104000500049769550800358003569986370015800108002024002080035164118002110910800101000050204160458003280000800108003680036800368003680036
80024800356002446258001080010800104000500149769550800358003569986370015800108002024002080035164118002110910800101000050205170948003280000800108003680036800368003680036
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