Firestorm: LDRSB (pre-index, 32-bit) measurements

Code:

  ldrsb w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	20	22	23	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
2005	1040	8	1	0	2	0	1	67	13	1	0	0	1	0	1025	0	1	1	5	17	25	2000	1000	1000	1000	1000	52828	45824	0	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1022	8	0	80	1030	2	0	10	6	35	1047	44	7	40	55	6	0	0	73	1	16	1	1	1037	1000	31	40	9	1000	1000	1057	1041	1041	1041	1041
2004	1040	8	1	1	0	0	0	69	20	0	0	0	2	0	1025	7	1	2	3	21	25	2000	1000	1000	1000	1000	52844	45824	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1028	8	0	41	1022	0	0	0	0	23	1020	41	7	22	39	6	2	0	73	2	16	2	2	1037	1000	27	16	0	1000	1000	1041	1057	1041	1041	1041
2004	1040	8	1	1	0	0	0	53	0	0	0	0	4	4	1025	0	1	3	5	17	25	2000	1000	1000	1000	1000	52848	45825	1	1042	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1025	8	0	52	1039	3	0	13	12	40	1037	33	5	37	48	6	3	0	73	2	16	2	2	1037	1000	21	19	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	0	1	0	0	53	10	0	0	0	1	0	1025	0	1	1	4	24	25	2000	1000	1000	1000	1000	52832	45824	1	1049	1040	699	3	788	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1017	8	0	50	1040	4	0	17	0	32	1027	22	5	25	39	6	3	0	73	1	16	1	2	1033	1000	33	32	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	0	1	0	0	55	14	0	0	0	2	4	1025	12	2	4	11	17	25	2000	1000	1000	1000	1000	52836	45824	0	1040	1042	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1024	9	0	36	1032	1	0	14	10	21	1027	29	4	29	47	7	3	0	73	2	16	1	2	1037	1000	24	15	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	61	20	0	0	0	2	0	1025	16	1	0	2	10	25	2000	1000	1000	1000	1000	52836	45825	1	1040	1049	699	3	773	2000	1000	1000	1000	1000	1049	44	1	1	1001	1000	1000	1007	8	0	44	1023	0	0	1	0	24	1032	28	5	24	47	7	1	0	73	1	16	1	2	1037	1000	29	28	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	53	28	0	0	0	2	0	1025	13	3	1	4	14	25	2000	1000	1000	1000	1000	52844	45824	0	1059	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1008	8	1	51	1033	0	0	15	12	25	1031	21	5	19	47	6	4	0	73	2	16	2	2	1037	1000	36	35	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	7	1	1	1	0	0	53	28	1	0	0	5	0	1025	16	2	2	2	12	25	2000	1000	1000	1000	1000	52836	45824	0	1050	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1033	6	0	90	1034	6	0	12	0	30	1021	22	5	31	19	7	0	0	73	1	16	2	2	1037	1000	25	19	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	1	0	0	53	26	1	0	0	1	0	1025	12	1	1	5	16	25	2000	1000	1000	1000	1000	52844	45824	0	1040	1042	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1007	7	0	57	1033	0	0	0	0	37	1023	39	5	33	63	7	1	0	73	1	16	1	1	1036	1000	29	31	0	1000	1000	1041	1041	1041	1041	1041
2004	1040	8	1	1	2	0	0	60	14	1	0	0	1	0	1025	14	1	5	2	23	25	2000	1000	1000	1000	1000	52852	45825	1	1040	1040	699	3	773	2000	1000	1000	1000	1000	1040	44	1	1	1001	1000	1000	1007	7	0	52	1034	0	0	0	0	29	1021	50	5	28	47	7	32	44	73	2	16	1	1	1020	1000	40	31	0	1000	1000	1041	1041	1041	1041	1041

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1982

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50209	72281	538	1	0	0	0	0	0	0	487	807	1	720	1	124	72006	793	5	1	71914	25	50770	40648	10134	40110	10007	613195	2728884	0	49	69087	0	71830	72010	65449	7	65538	50117	40232	10008	70256	10008	71844	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10919	1	155	514	10658	258	9	902	108	34	10902	131	5	131	1	3	3	1	1	1	2619	0	16	0	0	71742	40568	1041	1071	1093	10000	40100	71836	71995	71895	72073	72036
50204	71994	546	1	0	0	0	0	0	0	467	805	1	768	0	112	71805	797	4	1	71780	25	50830	40628	10133	40110	10007	614276	2732609	0	49	68851	0	71958	71948	65441	7	65684	50117	40232	10008	70256	10008	71986	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10910	0	146	473	10622	262	12	897	48	35	10914	128	5	129	0	0	4	1	1	1	2619	0	16	0	0	71879	40512	1114	1036	1001	10000	40100	72023	72055	72064	71812	72064
50204	72021	539	0	0	0	0	0	0	0	469	830	1	704	0	116	71987	778	5	5	71690	25	50715	40620	10145	40100	10000	614106	2724645	0	49	68859	0	71965	71986	65354	3	65568	50100	40200	10000	70200	10000	71896	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10907	0	155	478	10639	259	8	898	74	38	10942	119	12	136	0	0	5	0	0	0	2610	1	57	1	1	71724	40576	932	1151	1119	10000	40100	71976	72252	71979	71997	71984
50204	71957	539	0	0	0	0	1	0	0	403	827	1	720	0	116	72004	812	8	1	71823	25	50795	40628	10144	40100	10000	616396	2730328	0	49	68809	0	72054	71909	65478	3	65771	50100	40200	10000	70200	10000	72173	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10921	1	160	474	10659	270	12	943	50	44	10933	132	8	138	1	3	3	0	0	0	2610	1	64	1	1	71725	40520	1057	999	1087	10000	40100	72119	72140	72226	72184	71980
50204	71912	540	1	0	0	0	0	0	0	400	822	1	672	2	116	72006	801	9	6	71814	25	50845	40656	10134	40100	10000	613851	2732289	0	49	69099	0	72023	71940	65262	3	65613	50100	40200	10000	70790	10000	72056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10928	1	152	508	10643	285	7	890	42	42	10933	117	4	133	1	0	7	0	0	0	2610	1	65	1	1	71557	40540	1127	1140	1010	10000	40100	71828	72019	71953	71764	71905
50204	71870	540	1	0	0	0	0	0	0	445	830	1	672	1	140	71931	831	5	6	71578	25	50825	40704	10148	40100	10000	614378	2732505	0	49	68793	0	72027	72058	65495	3	65809	50100	40200	10000	70200	10000	72054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10905	1	157	485	10640	260	9	906	92	56	10953	131	7	124	1	3	3	0	0	0	2610	1	70	1	1	71743	40552	1017	1028	1167	10000	40100	71834	72213	72068	72063	71931
50204	72274	539	1	0	0	0	0	0	0	440	801	1	696	1	92	71945	795	9	7	71843	25	50745	40644	10142	40100	10000	617194	2734169	0	49	69083	0	72175	72002	65369	3	65535	50100	40200	10000	70200	10000	72105	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10930	1	154	483	10651	266	12	918	74	41	10906	133	6	138	1	1	0	0	0	0	2610	1	58	1	1	71532	40504	1122	1143	1006	10000	40100	72084	72198	72011	71932	71998
50204	71719	538	0	0	0	0	0	0	0	421	844	1	728	0	116	71900	789	5	5	71795	25	50825	40584	10133	40100	10000	615765	2730425	0	49	68749	0	72114	72045	65409	3	65597	50100	40200	10000	70200	10000	71998	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10880	0	163	478	10679	269	15	910	42	34	10934	128	10	121	0	0	4	0	0	0	2610	1	58	1	1	71916	40488	1073	1184	1052	10000	40100	71825	72238	72000	72016	71871
50204	71876	538	0	0	0	0	0	0	0	432	832	1	704	1	116	71883	800	3	3	71745	25	50770	40644	10134	40100	10000	614793	2731021	0	49	68913	0	71775	71780	65470	3	65679	50100	40200	10000	70200	10000	71991	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10954	0	154	512	10663	283	11	904	46	30	10919	130	4	137	0	0	3	0	0	0	2610	1	63	1	1	71885	40560	1144	1030	944	10000	40100	71846	72001	71965	71992	71985
50204	71881	538	0	0	0	0	0	0	0	416	805	1	800	0	136	71646	791	4	1	71962	25	50790	40617	10129	40100	10000	616032	2733309	0	49	68752	0	72066	72042	65569	3	65678	50100	40200	10041	70200	10000	71991	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10916	1	154	471	10665	244	7	909	126	29	10903	134	8	118	1	0	3	0	0	0	2610	1	64	1	1	71821	40576	1155	1154	1104	10000	40100	72057	72265	71956	72074	72067

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.1914

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	20	22	29	3a	3e	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
50029	72192	537	3	0	0	0	0	0	0	556	829	1	728	2	140	71756	822	4	3	71625	25	50715	40578	10148	40010	10000	631399	2722918	1	49	68810	72000	71758	65499	3	65675	50010	40020	10000	70020	10000	71865	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10960	3	152	538	10677	258	8	951	38	34	10958	121	7	126	1	16	5	0	0	2520	2	65	1	1	71660	40576	1000	990	924	10000	40010	71759	72142	71737	71908	71886
50024	71814	539	2	0	0	0	0	0	0	581	866	1	744	2	128	71892	812	4	4	71720	25	50685	40566	10145	40010	10000	630745	2720045	1	49	68840	71914	71769	65290	3	65581	50010	40020	10000	70020	10000	71888	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10939	3	148	519	10659	266	12	947	48	31	10959	133	7	140	3	3	3	0	0	2520	2	65	1	3	71770	40552	1002	998	908	10000	40010	71902	71895	71863	71930	71706
50024	71803	538	3	0	0	1	0	0	0	574	854	1	736	3	104	72064	827	5	3	71676	25	50715	40546	10147	40010	10000	631994	2723992	1	49	68761	71914	71896	65252	3	65627	50010	40020	10000	70020	10000	71844	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10951	6	132	509	10668	284	13	966	48	35	10958	137	7	144	2	3	5	0	0	2520	1	65	2	2	71383	40572	1036	900	1004	10000	40010	72004	72020	71917	71926	72053
50024	71963	540	3	1	0	3	0	0	0	546	851	1	744	2	148	71915	827	4	3	71655	25	50745	40590	10132	40010	10000	631763	2719286	1	49	68878	72018	71898	65377	3	65539	50010	40020	10000	70020	10000	71950	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10952	3	145	518	10676	305	11	989	50	43	10974	139	7	135	3	0	5	0	0	2520	1	65	1	1	71759	40621	992	870	1028	10000	40010	71917	71870	71927	72093	72015
50024	71904	538	3	0	0	1	0	0	0	605	847	1	744	2	116	71845	835	4	2	71683	25	50675	40602	10146	40010	10000	632109	2718112	1	49	68835	71841	71766	65323	3	65664	50010	40020	10000	70020	10000	71967	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10948	6	162	506	10693	267	9	958	74	38	11011	131	8	138	3	3	11	0	0	2520	1	65	2	1	71787	40536	990	994	998	10000	40010	71836	72103	71789	71857	71788
50024	71849	539	3	0	0	0	0	0	0	527	837	1	736	3	108	71822	856	5	2	71515	25	50685	40542	10143	40010	10000	630867	2721853	1	49	68921	71971	71801	65551	3	65654	50010	40020	10000	70020	10000	71873	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10953	3	135	558	10642	288	13	963	40	40	10939	145	12	140	2	0	3	0	0	2520	1	65	2	1	71827	40544	972	934	914	10000	40010	71906	72032	71833	71968	71923
50024	71915	537	3	0	0	0	0	0	4	571	830	1	752	3	148	71786	826	5	3	71520	25	50700	40550	10137	40010	10000	630611	2721070	1	49	68869	71917	71881	65317	3	65419	50010	40020	10000	70020	10000	71837	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10950	3	169	528	10693	268	12	922	46	39	10962	141	7	141	3	3	9	0	0	2520	3	71	2	2	71507	40588	932	1016	932	10000	40010	71907	71791	71865	72019	71879
50024	71949	540	3	0	3	0	0	0	0	593	863	1	752	3	140	71930	802	5	3	71522	25	50740	40566	10159	40010	10000	630929	2717993	1	49	68768	71927	71786	65330	3	65489	50010	40020	10000	70020	10000	72131	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10903	6	177	497	10671	287	10	940	34	37	10924	131	7	141	3	0	3	0	0	2520	3	65	1	1	71870	40564	1028	1100	1052	10000	40010	72012	71895	71845	71870	71942
50024	72012	538	3	0	0	0	0	0	0	610	863	1	736	2	140	71865	819	5	2	71704	25	50740	40554	10152	40010	10000	630540	2720895	1	49	68858	71799	71716	65359	3	65401	50010	40020	10000	70020	10000	71875	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10963	10	153	528	10669	291	9	944	36	43	10958	148	7	130	2	3	3	0	0	2520	2	65	1	3	71836	40600	1056	1040	952	10000	40010	72173	72067	71911	71884	71776
50024	71957	540	3	1	0	0	0	0	0	534	852	1	744	3	112	71870	812	4	3	71663	25	50695	40586	10135	40010	10000	631865	2728360	1	49	68913	71896	71918	65436	3	65554	50010	40020	10000	70020	10000	71933	35	1	1	40021	10	9	10	10000	30010	10000	0	10	11003	7	152	520	10685	288	10	947	50	35	10951	130	7	144	2	3	9	0	0	2520	2	65	2	2	71835	40576	967	958	1014	10000	40010	71843	71922	71863	71996	72110

Test 3: throughput

Count: 8

Code:

  ldrsb w0, [x6, #8]!
  ldrsb w0, [x7, #8]!
  ldrsb w0, [x8, #8]!
  ldrsb w0, [x9, #8]!
  ldrsb w0, [x10, #8]!
  ldrsb w0, [x11, #8]!
  ldrsb w0, [x12, #8]!
  ldrsb w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3648

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160209	29745	219	4	4	4	0	6677	787	1	720	115	100	29321	789	290	2312	1912	1974	127	160176	80175	80000	80120	80016	400852	1276267	0	53	49	26015	29110	29049	9169	6	9213	160135	80224	80028	80224	80024	29092	35	1	1	80201	100	99	11	100	80000	100	80000	1	100	80958	74	447	5283	85322	767	14	907	46	4817	86208	767	117	4761	4518	66	1	0	1	1	1	5117	0	16	1	0	29261	34	80080	408	359	66	80000	80100	29208	29038	29162	29186	29099
160204	29132	218	4	1	4	0	6550	797	1	728	117	96	29167	800	334	2057	2160	1841	25	160169	80166	80000	80124	80016	400838	1294677	0	62	49	25965	28863	29181	9044	6	9034	160493	80220	80020	80224	80024	29355	35	1	1	80201	100	99	24	100	80000	100	80000	1	100	81109	63	390	4771	84784	718	12	896	50	5090	85757	699	136	4248	5575	73	0	0	0	0	0	5110	1	16	1	1	29252	21	80055	371	436	61	80000	80100	29262	29077	29258	29228	29197
160204	28826	216	4	0	0	0	6832	831	1	736	106	100	29425	800	317	1894	2144	1840	59	161375	80168	80000	80270	80000	400750	1285362	0	63	49	25997	29138	29167	9127	3	8965	160477	80200	80000	80200	80000	29164	35	1	1	80201	100	99	14	100	80000	100	80000	1	100	80985	67	444	4638	84178	759	15	871	46	4690	85545	765	140	4659	4783	71	0	3	0	0	0	5110	1	16	1	1	29235	27	80056	397	372	58	80000	80100	28909	29214	29078	29239	29145
160204	29254	219	4	0	0	0	6087	827	1	720	86	152	29053	792	369	1853	1908	1986	25	160158	80146	80000	80100	80000	400785	1277374	0	57	49	25823	29203	29065	9150	3	9096	160100	80200	80000	80200	80000	29043	35	1	1	80201	100	99	16	100	80000	100	80000	1	100	80977	68	400	5576	84961	735	13	898	38	4761	85736	688	137	4385	5152	72	4	3	0	0	0	5110	1	16	1	1	29184	45	80054	397	339	62	80000	80100	29268	29129	29073	29154	29114
160204	29201	218	4	0	0	0	6643	829	1	752	119	144	29038	806	323	1909	2154	2055	25	160153	80160	80000	80100	80000	400733	1293426	0	55	49	26334	29188	29335	9180	3	9078	160100	80200	80000	80200	80000	29131	35	1	1	80201	100	99	23	100	80000	100	80000	1	100	80954	72	419	5565	84800	782	11	878	68	4712	85427	813	126	4715	5564	63	0	0	0	0	0	5110	1	16	1	1	29428	27	80240	428	424	58	80000	80100	29197	29213	29305	29340	29473
160204	29336	219	4	0	2	0	6491	837	1	696	110	148	29164	771	371	2207	2085	1850	128	160166	80328	80000	80264	80172	400773	1286485	0	68	49	26142	29168	29087	9159	3	9173	160100	80200	80000	80200	80000	29334	35	1	1	80201	100	99	9	100	80000	100	80000	1	100	80959	67	442	5769	84653	793	11	935	74	4579	85550	825	133	5011	5515	71	0	9	0	0	0	5110	1	16	1	1	29065	34	80056	403	393	60	80000	80100	29264	29150	29221	29210	29205
160204	29063	218	4	4	0	0	6755	795	1	736	111	92	29131	772	348	1984	1906	1647	25	160169	80161	80000	80100	80000	400747	1286400	0	51	49	26041	29299	29227	9039	3	9176	160100	80200	80000	80200	80000	29099	35	1	1	80201	100	99	24	100	80000	100	80000	1	100	81012	67	426	4883	84778	748	14	917	46	4839	86163	857	139	4445	5173	70	0	3	0	0	0	5110	1	17	1	1	29041	28	80047	389	378	68	80000	80100	29130	29014	29080	29108	29306
160204	29263	218	4	0	0	0	6780	823	1	744	98	100	29202	816	358	2120	2269	1949	25	160160	80160	80000	80100	80000	400778	1286014	0	61	49	26042	29094	28954	9116	3	9153	160100	80200	80000	80200	80000	29194	35	1	1	80201	100	99	22	100	80000	100	80000	1	100	80978	72	423	5646	85077	757	12	930	76	4994	86110	753	144	4100	5069	71	1	3	0	0	0	5110	1	17	1	1	29127	31	80066	405	412	69	80000	80100	29137	29125	29302	29508	29228
160204	29157	219	4	0	0	0	6158	785	1	728	95	96	29031	808	331	1966	1989	1812	25	160159	80153	80000	80100	80000	400735	1292477	0	49	49	26047	29141	29098	9099	3	9227	160100	80200	80000	80200	80000	29362	35	1	1	80201	100	99	30	100	80000	100	80000	1	100	80945	72	485	4729	84897	785	11	897	46	4971	85519	763	112	5086	5283	72	3	3	0	0	0	5110	1	16	1	1	29114	35	80057	381	400	71	80000	80100	29158	29276	29421	29400	29254
160204	29017	219	4	1	0	0	6665	841	1	704	120	108	29358	768	297	2068	2333	2099	25	160175	80161	80000	80100	80000	400751	1287225	0	64	49	26081	29056	29078	8986	3	9057	160100	80200	80000	80200	80000	29095	35	1	1	80201	100	99	30	100	80000	100	80000	1	100	81009	63	458	4972	84631	714	8	921	70	4500	85295	755	116	4392	4958	70	4	4	0	0	0	5110	1	17	1	1	29088	30	80055	398	451	60	80000	80100	29359	29288	29146	29099	29149

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3664

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cd	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160029	29501	220	0	1	1	0	0	7181	875	1	760	105	116	29368	758	612	2113	2204	1998	25	160074	80068	80000	80010	80000	400282	1301672	1	64	49	26266	29450	29404	9248	0	3	9448	160010	80020	80000	80020	80000	29507	35	1	1	80021	10	9	9	10	80000	10	80000	10	80991	39	441	4821	85967	755	16	936	38	5728	86100	786	144	5054	5408	37	2	3	0	1	5020	0	12	16	16	9	29466	32	80064	402	353	100	80000	80010	29262	29209	29129	29300	29359
160024	29417	218	0	1	0	0	0	7574	812	1	712	104	104	29278	819	522	2090	2110	1985	25	160077	80071	80000	80010	80000	400290	1302903	0	58	49	26418	29604	29465	9324	0	3	9362	160010	80020	80000	80020	80000	29404	35	1	1	80021	10	9	18	10	80000	10	80000	10	80945	36	372	5254	85952	741	16	880	72	5436	86015	845	122	5584	5040	36	0	3	0	0	5020	0	17	16	16	12	29345	36	80068	397	400	88	80000	80010	29443	29368	29338	29457	29212
160024	29309	219	0	2	0	2	2	7812	824	1	744	97	112	29410	795	544	2214	2074	2031	25	160079	80076	80000	80010	80000	400340	1299632	1	79	49	26255	29350	29408	9448	0	3	9368	160010	80020	80000	80020	80000	29548	35	1	1	80021	10	9	8	10	80000	10	80000	10	80928	41	384	5478	85656	723	14	931	72	5128	85824	842	140	5759	4975	37	2	5	0	0	5020	0	8	16	17	17	29581	40	80057	377	433	93	80000	80010	29365	29469	29347	29428	29435
160024	29188	217	0	2	2	0	2	7117	800	1	728	102	116	29407	785	593	2116	2124	2013	25	160093	80073	80000	80010	80000	400343	1300657	1	61	49	26237	29265	29376	9332	0	3	9039	160010	80020	80000	80020	80000	29292	35	1	1	80021	10	9	14	10	80000	10	80000	10	80932	37	381	5657	85299	687	17	884	38	5473	86373	803	141	5411	5795	16	3	5	0	0	5020	0	14	16	16	15	29287	35	80070	380	351	86	80000	80010	29305	29240	29583	29329	29373
160024	29342	221	0	1	0	0	0	7831	837	1	776	97	100	29229	810	536	1940	1992	1870	25	160068	80068	80000	80010	80000	400367	1296955	1	59	49	26164	29366	29274	9221	0	3	9225	160010	80020	80000	80020	80000	29146	35	1	1	80021	10	9	8	10	80000	10	80000	10	80885	8	391	5871	85247	668	16	912	72	5677	85810	756	141	5518	5356	18	0	3	0	0	5020	0	16	16	14	16	29377	35	80059	330	382	95	80000	80010	29220	29252	29650	29374	29330
160024	29489	220	0	1	0	0	1	7120	823	1	704	98	136	29222	781	531	2198	2244	1937	25	160077	80075	80000	80010	80000	400345	1293883	1	62	49	26274	29314	29047	9012	0	3	9424	160010	80020	80000	80020	80000	29280	35	1	1	80021	10	9	11	10	80000	10	80000	10	80928	16	421	5775	85000	739	15	927	36	5629	86553	823	149	5369	5447	17	2	3	0	0	5020	0	17	16	17	14	29267	22	80060	397	420	103	80000	80010	29163	29225	29161	29409	29370
160024	29249	219	0	1	0	1	0	7547	839	1	744	108	80	29376	802	626	2211	2137	1873	25	160063	80070	80000	80010	80000	400266	1296128	1	50	49	26154	29388	29574	9200	0	3	9439	160010	80020	80000	80020	80000	29531	35	1	1	80021	10	9	7	10	80000	10	80000	10	80887	18	385	5339	85151	712	13	953	26	5061	86096	863	137	5420	5456	36	0	6	0	0	5020	0	16	16	14	17	29503	26	80047	294	371	89	80000	80010	29331	29207	29365	29426	29340
160024	29372	218	0	2	2	0	0	6649	830	2	792	93	76	29520	781	540	1818	2262	2212	25	160065	80056	80000	80010	80000	400357	1292311	1	62	49	26067	29264	29313	9359	0	3	9266	160010	80020	80000	80020	80000	29323	35	1	1	80021	10	9	15	10	80000	10	80000	10	80961	39	375	4996	85270	715	19	966	84	6072	86040	857	127	5336	5074	37	8	7	0	0	5020	0	19	16	10	17	29092	38	80052	403	413	94	80000	80010	29521	29273	29369	29282	29185
160024	29296	221	0	2	0	0	2	7806	807	1	752	105	104	29265	834	582	2124	2186	1949	25	160072	80068	80000	80010	80000	400333	1286012	1	57	49	26127	29436	29424	9320	0	3	9475	160010	80020	80000	80020	80000	29307	35	1	1	80021	10	9	12	10	80000	10	80000	10	80984	38	417	5558	85947	725	10	929	34	5926	86584	823	132	5773	5280	36	6	5	0	0	5020	0	17	16	16	14	29337	21	80069	374	345	108	80000	80010	29456	29111	29489	29252	29276
160024	29330	220	0	2	0	0	0	6914	840	1	752	120	112	29407	812	570	2191	2124	2047	25	160071	80067	80000	80010	80000	400343	1290235	1	70	49	26290	29465	29182	9217	0	3	9280	160010	80020	80000	80020	80000	29230	35	1	1	80021	10	9	5	10	80000	10	80000	10	80976	39	392	5678	85653	748	16	865	34	5680	86160	777	136	4910	4929	37	3	17	0	0	5020	0	18	16	16	10	29306	28	80059	351	380	107	80000	80010	29227	29383	29164	29308	29340

LDRSB (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations