Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (immediate, 64-bit)

Test 1: uops

Code:

  orr x0, x0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03191e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100410358006186225100010001000169161103510357283868100010001000103541111001100000073241229371000100010361036103610361036
1004103580015686225100010001000169160103510357283868100010001000103541111001100000073241229371000100010361036103610361036
1004103580576186225100010001000169161103510357283868100010001000103541111001100000073241229371000100010361036103610361036
100410357036186225100010001000169161103510357283868100010001000103541111001100002073241229371000100010361036103610361036
100410358006186225100010001000169161103510357283868100010001000103541111001100000073241229371000100010361036103610361036
100410358006186225100010001000169161103510357283868100010001000103541111001100000073241229371000100010361036103610361036
100410358006186225100010001000169161103510357283868100010001000103541111001100000073241229371000100010361036103610361036
1004103580816186225100010001000169161103510357283868100010001000103541111001100000073241229371000100010361036103610361036
100410357006186225100010001000169160103510357283868100010001000103541111001100000073241229371000100010361036103610361036
100410358006186225100010001000169160103510357283868100010001000103541111001100000073241229371000100010361036103610361036

Test 2: Latency 1->2

Code:

  orr x0, x0, #3
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03091e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10204100357509619877251010010100101008866414969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866414969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
102041003575012619877251010010100101008866414969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
102041003576007299877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
1020410035750186619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866414969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
10204100357500619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036
1020410035750246619877251010010100101008866404969551003510035858038722101001020010200100354111102011009910010100100071013711994110000101001003610036100361003610036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002410035760061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010100064034133994010000100101003610036100361003610036
1002410035750061986325100101001010010887840496955100351003586023874010010100201002010035411110021109101001010346064034133994010000100101003610036100361003610036
1002410035750061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010100064034132994010000100101003610036100361003610036
1002410035750061986325100101001010010887840496955100351003586023874010010100201002010035411110021109101001010000064024122994010000100101003610036100361003610036
1002410035750082986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010000064034123994010000100101003610036100361003610036
1002410035750061986325100101001010010887841496955100351003586023874010010100201002010035411110021109101001010000064024133994010000100101003610036100361003610036
1002410035760061986325100101001010010887840496955100351003586023874010010100201002010035411110021109101001010000064034123994010000100101003610036100361003610036
1002410035750061986325100101001010010887840496955100351003586023874010010100201002010035411110021109101001010000064024133994010000100101003610036100361003610036
10024100357500145986325100101001010010887840496955100351003586023874010010100201002010035411110021109101001010000064024133994010000100101003610036100361003610036
1002410035750061986325100101001010010887840496955100351003586023874010010100201002010035411110021109101001010000064024123994010000100101003610036100361003610036

Test 3: throughput

Count: 8

Code:

  orr x0, x8, #3
  orr x1, x8, #3
  orr x2, x8, #3
  orr x3, x8, #3
  orr x4, x8, #3
  orr x5, x8, #3
  orr x6, x8, #3
  orr x7, x8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.1674

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020413414101000210282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000111511901601338780036801001341713391133911339113391
802041339010000000512780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000111511901601338780036801001339113391133911339113391
802041339010000000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000111511901601338780036801001339113391133911339113391
802041339010000000282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000111511901601338780036801001339113391133911339113391
802041339010000090282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000111511901601338780036801001339113391133911339113391
8020413390100000540282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000111511901601338780036801001339113391133911339113391
80204133901000003870282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000000111511901601338780036801001339113391133911339113391
80204133901000001740282780136801368014840071004910310133901339033266333680148802648026413390391180201100991008010010000030111511901601338780036801001339113391133911345313507
8020413516101132582264591120803928051480531402009049104321357613593332618342180282806668065913637395180201100991008010010021220832111521509311362580036801001370013638136551359113665
8020413643102154399264549152807828065380668402637049105971370513640333324341180826805188105613640396180201100991008010010001223000111511901611343180036801001339113391133911339113391

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.1671

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6061696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
800241337710003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000502250419241336880000800101337213372133721337213372
8002413371100024725800108014280010400050004910291133711337133303334880010800208002013371391180021109108001010000502100219241336880000800101337213372133721337213372
800241337110003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010010502100419241336880000800101337213372133721337213372
800241337110003565800108001080010400050104910291133711337133303334880010800208002013371391180021109108001010030502100219241336880000800101337213372133721337213372
80024133711000442258001080010800104000500049102911337113371333033348800108002080020133713911800211091080010100018502203319421336880000800101337213372133721337213372
800241337110003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000502100419241336880000800101337213372133721337213372
80024133711000314258001080010800104000500049102911337113371333033348800108002080020133713911800211091080010100021502250419421336880000800101337213372133721337213372
800241337110003548800108001080010400050054910291133711337133303334880010800208002013371391180021109108001010000502202419421336880000800101337213372133721337213372
800241337110003525800108001080010400050004910291133711337133303334880010800208002013371391180021109108001010000502200419441336880000800101337213372133721337213372
8002413371100058258001080010800104000500049102911337113371333033348800108002080020133713911800211091080010100012502200419431336880000800101337213372133721337213372