Firestorm: LDR (register, 64-bit) measurements

Code:

  ldr x0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	403	3	0	0	0	45	0	0	1	383	2	1	1	19	25	1000	1000	1000	14989	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	1	1000	0	43	1038	0	38	1038	6	1	39	44	73	2	16	1	1	395	14	10	7	1000	399	399	399	399	399
1004	398	2	0	0	0	44	0	0	1	383	0	1	1	16	25	1000	1000	1000	15274	1	398	398	221	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	0	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	395	399	399	395	399
1004	394	3	0	1	1	45	0	0	1	383	0	1	1	19	25	1000	1000	1000	15267	1	401	398	221	3	258	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	0	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	1	1	1	45	1	0	1	383	2	1	12	19	25	1000	1000	1000	15274	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	0	43	1038	0	38	1038	6	1	39	44	73	1	16	1	1	395	14	10	4	1000	399	399	399	399	399
1004	398	3	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	0	43	1039	0	38	1038	6	1	38	44	73	1	16	1	1	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15018	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	0	44	1039	4	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	383	3	1	1	19	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	0	44	1039	0	38	1039	6	1	38	44	73	1	16	1	1	395	14	10	4	1000	399	399	399	399	399
1004	398	3	0	0	0	44	0	0	1	383	2	1	1	19	25	1000	1000	1000	15208	1	398	398	221	3	256	1000	1000	2000	398	85	1	1	1001	1000	1000	0	1000	0	44	1038	0	38	1039	6	1	39	43	73	1	16	1	1	395	10	10	7	1000	399	399	399	399	399
1004	398	3	0	0	0	44	1	0	1	383	2	1	1	19	25	1000	1000	1000	15208	0	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	0	43	1038	0	38	1038	6	1	38	44	73	1	16	1	1	395	14	14	7	1000	399	399	399	399	406
1004	394	3	0	0	0	44	0	0	1	383	3	1	1	19	25	1000	1000	1000	15267	1	398	398	221	3	256	1000	1000	2000	398	77	1	1	1001	1000	1000	0	1000	1	44	1038	0	41	1038	6	1	38	44	73	1	16	1	1	391	10	10	7	1000	395	399	399	399	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	1	1	1	1	0	70032	69735	59709	25	40104	30103	10001	30100	10000	616015	3341470	1	49	66970	70035	70035	64643	0	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	1	0	2610	2	71	1	1	69798	30003	9	6	6	10000	30100	70036	70051	70048	70051	70051
40204	70047	525	1	1	1	1	0	70032	69764	59706	25	40104	30100	10001	30100	10000	616015	3342062	0	49	66974	70050	70047	64646	0	3	64950	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	1	1	2610	1	71	1	1	69798	30003	9	6	0	10000	30100	70051	70048	70048	70048	70051
40204	70035	525	0	0	0	1	0	70032	69781	59709	25	40100	30103	10001	30100	10000	616175	3342062	1	49	66970	70047	70047	64631	0	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	3	0	10000	0	0	1	0	2610	1	71	1	1	69810	30000	6	6	9	10000	30100	70048	70036	70051	70048	70036
40204	70050	524	0	0	1	1	0	70035	69764	59709	25	40104	30103	10000	30100	10000	616005	3342206	1	49	66970	70047	70047	64631	0	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	0	1	0	2610	1	71	1	1	69810	30003	6	6	0	10000	30100	70036	70048	70036	70051	70036
40204	70093	525	0	0	1	1	0	70035	69735	59709	25	40104	30103	10001	30100	10000	616005	3342206	1	49	66955	70047	70035	64646	0	3	64938	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	1	3	10000	1	0	1	0	2610	1	71	1	1	69810	30003	9	9	9	10000	30100	70048	70048	70036	70036	70051
40204	70035	525	0	0	1	1	0	70035	69735	59695	25	40100	30100	10000	30100	10000	616005	3342062	1	49	66956	70047	70035	64631	0	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	1	0	2610	1	71	1	1	69813	30000	6	0	6	10000	30100	70056	70051	70048	70048	70051
40204	70047	525	0	0	0	0	0	70035	69781	59709	25	40104	30103	10001	30100	10000	616175	3342206	1	49	66967	70053	70047	64631	0	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	0	1	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70036	70051	70051	70051	70051
40204	70050	525	0	0	1	1	0	70032	69781	59709	25	40104	30103	10000	30100	10000	616005	3341470	1	49	66955	70050	70035	64631	0	3	64953	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	2610	1	71	1	1	69813	30000	9	0	9	10000	30100	70051	70051	70048	70036	70051
40204	70035	524	0	0	1	0	0	70035	69781	59709	25	40104	30103	10000	30100	10000	616015	3341470	1	49	66970	70035	70050	64643	0	3	64953	40100	30200	10000	60200	20000	70050	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	0	0	0	2610	1	71	1	1	69798	30003	9	9	6	10000	30100	70048	70036	70048	70051	70051
40204	70047	524	0	0	1	0	0	70035	69735	59709	25	40104	30103	10000	30100	10000	616015	3342062	1	49	66970	70047	70050	64643	0	3	64938	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	2610	1	71	1	1	69813	30003	0	6	9	10000	30100	70051	70051	70051	70051	70051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	524	1	1	1	0	0	0	0	2	0	1	0	0	70045	69784	59719	25	40018	30016	10002	30010	10000	616995	3342686	1	1	49	66977	70060	70060	64659	3	64982	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	10	10001	3	1	10002	0	0	1	1	10000	1	1	1	1	0	2520	9	71	9	2	69823	30006	13	0	0	10000	30010	70042	70042	70061	70042	70042
40024	70060	524	1	0	1	0	0	0	0	35	0	0	0	0	70045	69784	59719	25	40018	30016	10001	30010	10000	617090	3341769	2	1	49	66977	70041	70041	64659	3	64985	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	10	10002	2	0	10001	0	0	1	1	10000	0	1	1	1	1	2520	4	71	4	5	69804	30006	13	10	13	10000	30010	70065	70060	70042	70058	70059
40024	70057	525	1	0	1	1	0	0	0	2	0	0	0	0	70042	69781	59701	25	40014	30016	10002	30010	10000	616995	3342686	1	1	49	67182	70041	70060	64675	3	64966	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	10	10001	2	0	10001	0	0	0	4	10012	1	1	0	1	0	2520	4	71	5	4	69823	30006	0	0	0	10000	30010	70061	70042	70058	70061	70042
40024	70041	525	1	1	1	0	0	0	0	2	0	1	0	1	70045	69784	59719	25	40018	30016	10001	30010	10000	617072	3342686	1	1	49	66977	70041	70057	64662	3	64987	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	10	10001	2	1	10001	0	0	1	4	10000	1	1	1	1	0	2520	5	71	6	4	69804	30006	0	10	0	10000	30010	70061	70058	70042	70042	70042
40024	70058	525	1	1	1	1	0	0	0	2	0	0	0	0	70045	69784	59719	25	40018	30016	10002	30010	10000	617072	3342686	1	1	49	66977	70057	70041	64675	3	64966	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	10	10002	2	0	10002	0	0	1	4	10000	1	1	1	1	1	2520	4	71	3	5	69820	30006	0	13	0	10000	30010	70058	70042	70061	70061	70319
40024	70041	524	1	0	1	0	1	0	0	2	0	0	0	0	70045	69781	59716	25	40014	30016	10002	30010	10000	617072	3341769	1	1	49	66980	70060	70060	64678	3	64966	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	10	10001	1	1	10001	1	0	2	1	10000	0	1	0	1	0	2520	5	71	4	4	69820	30003	13	10	10	10000	30010	70061	70061	70061	70061	70064
40024	70060	525	1	1	1	1	0	0	0	2	0	0	0	1	70128	69702	59701	25	40018	30016	10001	30010	10000	617045	3342686	2	1	49	66980	70041	70041	64678	3	64985	40010	30020	10000	60020	20000	70061	35	2	1	40021	10	9	10	10000	30010	10000	10	10001	1	0	10002	0	0	0	4	10000	0	1	1	1	1	2520	6	78	8	5	69969	30003	13	13	0	10000	30010	70062	70061	70058	70058	70061
40024	70060	525	1	0	1	0	1	0	0	5	88	1	0	0	70045	69702	59701	25	40018	30016	10001	30010	10000	617072	3342542	1	1	49	66980	70041	70041	64678	3	64985	40010	30020	10000	60020	20442	70062	35	1	1	40021	10	9	10	10000	30010	10000	10	10003	1	1	10002	0	1	0	1	10000	0	1	1	1	0	2520	4	71	4	4	69820	30003	0	0	10	10000	30010	70061	70058	70061	70058	70064
40024	70430	524	1	0	0	0	0	0	0	2	0	0	0	1	70026	69784	59701	25	40018	30016	10001	30010	10204	617135	3342686	1	1	49	66961	70057	70041	64679	3	64982	40788	30020	10000	60350	20108	70224	35	1	1	40021	10	9	10	10000	30010	10000	10	10001	1	1	10008	0	0	3	7	10000	1	1	1	1	2	2520	4	71	2	4	69805	30006	0	13	10	10000	30010	70061	70066	70058	70061	70066
40024	70060	525	1	0	1	0	1	0	0	2	0	0	0	0	70045	69785	59716	25	40018	30016	10002	30010	10000	616995	3342734	1	1	49	66961	70060	70057	64675	3	65047	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	10	10002	4	1	10002	0	1	0	7	10000	1	1	1	1	0	2520	5	71	5	4	70133	30006	10	0	0	10000	30010	70058	70042	70058	70150	70063

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	22	24	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	524	1	1	0	0	1	0	0	0	70039	69785	59710	25	40104	30103	10002	30100	10000	616175	3342542	1	49	66971	70054	70051	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	2610	2	71	2	2	69819	30003	13	10	0	10000	30100	70055	70055	70055	70055	70052
40204	70051	524	1	0	0	0	1	0	0	0	70020	69782	59713	25	40104	30103	10001	30100	10000	616041	3342398	1	49	66971	70054	70054	64650	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	2610	2	71	2	2	69814	30000	0	10	13	10000	30100	70055	70052	70055	70055	70055
40204	70054	525	1	0	0	0	1	0	0	0	70044	69785	59713	25	40100	30103	10001	30100	10000	616014	3342254	1	49	66978	70054	70051	64650	3	64954	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	2	71	2	2	69817	30003	13	10	13	10000	30100	70055	70055	70157	70036	70055
40204	70054	524	0	0	0	0	0	0	0	0	70039	69785	59713	25	40104	30103	10001	30100	10000	616041	3342398	1	49	66974	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	2	71	2	2	69817	30003	13	13	13	10000	30100	70055	70055	70055	70052	70055
40204	70054	525	0	0	0	0	1	0	1	0	70039	69785	59713	25	40104	30100	10001	30100	10000	616041	3341470	1	49	66974	70054	70051	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	2	71	2	2	69817	30003	10	10	0	10000	30100	70055	70055	70055	70036	70055
40204	70054	525	0	0	0	0	1	0	0	0	70020	69785	59713	25	40104	30100	10001	30100	10000	616041	3342398	1	49	66974	70054	70051	64631	3	64938	40100	30200	10000	60594	20000	70059	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10001	1	1	0	0	2610	2	71	2	2	69814	30003	0	10	0	10000	30100	70055	70055	70055	70055	70055
40204	70054	525	0	0	0	0	1	0	0	0	70039	69785	59713	25	40104	30103	10001	30100	10000	616175	3342398	1	49	66974	70054	70054	64655	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	2	71	2	2	69817	30003	10	13	0	10000	30100	70055	70036	70052	70052	70055
40204	70035	525	0	0	0	0	25	0	1	0	70036	69785	59710	25	40100	30103	10001	30100	10000	616041	3342398	1	49	66971	70054	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	2	71	2	2	69817	30003	13	13	13	10000	30100	70055	70055	70052	70055	70036
40204	70054	524	0	0	0	0	0	0	0	0	70020	69785	59713	25	40104	30100	10001	30100	10000	616041	3341470	1	49	66974	70035	70051	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	0	10000	0	0	0	10000	0	1	0	0	2610	2	71	2	2	69817	30003	13	0	13	10000	30100	70055	70055	70052	70055	70055
40204	70054	524	0	0	0	0	1	0	0	0	70039	69764	59710	25	40100	30103	10001	30100	10000	616175	3341470	1	49	66974	70054	70054	64650	3	64954	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	2610	2	71	2	2	69814	30003	10	10	13	10000	30100	70055	70055	70055	70055	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	524	1	0	1	1	0	0	1	0	0	0	70036	69728	59706	25	40010	30013	10001	30010	10000	617068	3342062	0	49	66955	70035	70047	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	2521	5	71	3	2	69810	30000	6	0	6	10000	30010	70048	70051	70048	70036	70036
40024	70035	524	0	0	0	0	0	0	1	1	0	0	70032	69728	59706	25	40014	30010	10001	30010	10000	617068	3342062	1	49	66967	70047	70047	64665	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	10000	1	0	0	2521	3	71	3	3	69810	30000	6	9	0	10000	30010	70036	70036	70048	70051	70036
40024	70047	524	0	0	0	0	0	0	1	0	0	1	70035	69743	59706	25	40014	30013	10000	30010	10000	616982	3341470	1	49	66955	70047	70053	64665	3	64972	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	0	0	2521	4	71	3	3	69810	30003	6	6	0	10000	30010	70051	70048	70048	70048	70048
40024	70050	524	0	0	0	0	1	1	1	1	0	0	70032	69743	59706	25	40010	30013	10001	30010	10000	617068	3342062	1	49	66955	70047	70047	64665	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	0	0	2521	3	71	3	4	69798	30003	6	6	0	10000	30010	70036	70036	70048	70048	70048
40024	70035	525	0	0	0	0	0	0	1	1	0	0	70034	69743	59700	25	40054	30013	10001	30010	10000	616952	3341470	0	49	66967	70035	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	2521	3	71	3	2	69810	30003	6	6	6	10000	30010	70055	70059	70048	70048	70048
40024	70047	525	0	0	0	0	0	0	1	0	0	0	70032	69743	59695	25	40010	30013	10001	30010	10000	616952	3342062	0	49	67037	70048	70048	64665	3	64972	40010	30020	10000	60020	20000	70122	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	0	10000	1	0	0	2521	3	71	3	4	69798	30000	0	6	6	10000	30010	70048	70048	70036	70048	70048
40024	70047	524	0	0	0	0	0	0	1	0	0	0	70032	69760	59695	25	40014	30013	10001	30010	10000	616952	3341470	1	49	66955	70047	70047	64653	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	0	10000	1	0	0	2521	3	71	3	3	69798	30003	9	9	6	10000	30010	70048	70048	70036	70048	70048
40024	70035	525	0	0	0	0	0	0	0	0	0	0	70032	69743	59706	25	40010	30013	10001	30010	10000	617068	3342062	1	49	66967	70047	70047	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	10000	48	0	0	10000	1	0	0	2554	3	71	4	3	69810	30003	6	0	6	10000	30010	70048	70048	70048	70048	70048
40024	70047	525	0	0	0	0	0	0	1	0	0	0	70032	69743	59706	25	40010	30010	10001	30010	10000	616952	3341470	0	49	66967	70047	70050	64653	3	64972	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	3	10000	0	1	0	2521	3	71	4	3	69810	30003	0	6	6	10000	30010	70036	70036	70048	70048	70048
40024	70047	525	0	0	0	1	0	0	0	1	0	0	70032	69743	59706	25	40014	30013	10001	30010	10000	617068	3342062	0	49	66955	70035	70047	64665	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	0	10000	0	1	0	2521	3	71	3	3	69810	30003	6	6	0	10000	30010	70051	70036	70048	70048	70048

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	09	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26731	200	0	0	0	0	0	67	1	0	2	26725	2	0	7	76	25	80100	100	80000	100	80012	500	1167310	49	23634	0	26736	26714	16642	6	16688	80116	200	80024	200	160048	26714	85	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	43	80059	2	0	1	61	80040	6	1	60	43	19	1	1	1	1	5118	2	16	4	4	26733	13	13	5	80000	100	26737	26737	26737	26832	26742
80204	26736	200	1	1	1	0	0	67	0	0	2	26699	3	7	7	26	25	80100	100	80000	100	80017	500	1168046	49	23634	0	26714	26714	16663	6	16689	80115	200	80024	200	160048	26714	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	43	80019	1	0	1	27	80000	0	1	19	43	19	1	1	1	1	5118	4	16	4	3	26734	13	0	0	80000	100	26738	26737	26737	26797	26717
80204	26727	200	0	0	0	0	0	0	0	0	1	26712	2	12	0	76	25	80100	100	80000	100	80015	500	1177116	49	23647	0	26707	26727	16655	6	16659	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	0	0	48	80039	6	1	0	44	0	0	1	1	1	5118	4	16	3	3	26724	0	10	4	80000	100	26728	26728	26728	26790	26741
80204	26727	200	0	0	0	0	0	0	0	0	1	26692	2	0	0	0	25	80100	100	80000	100	80014	500	1177261	49	23627	0	26727	26707	16635	6	16679	80115	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	46	0	63	80000	0	0	38	0	0	0	1	1	1	5118	4	16	4	4	26724	0	10	4	80000	100	26735	26732	26945	26728	26753
80204	26727	200	0	0	0	0	0	0	0	0	1	26692	2	0	12	69	25	80100	100	80000	100	80015	500	1177116	49	23651	0	26727	26707	16655	6	16679	80113	200	80024	200	160048	26707	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	39	80039	6	1	39	43	0	0	1	1	1	5118	4	16	4	3	26724	14	10	7	80000	100	26728	26728	26728	26865	26733
80204	26727	200	0	0	0	0	0	45	1	0	0	26712	2	12	12	71	25	80100	100	80000	100	80015	500	1165856	49	23647	0	26727	26731	16655	6	16679	80115	200	80024	200	160048	26731	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	3	0	39	80038	0	0	38	0	0	0	1	1	1	5118	3	16	4	3	26724	0	10	4	80000	100	26728	26733	26728	26844	26743
80204	26707	200	0	0	0	0	0	0	1	0	1	26712	0	12	1	69	25	80100	100	80000	100	80015	500	1167198	49	23647	0	26727	26727	16655	6	16683	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	0	80039	0	3	0	39	80039	6	0	0	0	0	0	1	1	1	5118	4	16	2	2	26724	0	14	4	80000	100	26728	26708	26728	26850	26744
80204	26727	200	0	0	0	0	0	0	1	0	1	26692	0	1	12	74	25	80100	100	80000	100	80015	500	1166596	49	23647	0	26727	26727	16635	6	16679	80115	200	80024	200	160048	26727	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80039	0	1	0	0	80039	6	0	39	43	0	0	1	1	1	5118	4	16	3	3	26704	14	10	4	80000	100	26728	26728	26728	26799	26736
80204	26727	200	0	0	0	0	0	45	1	0	0	26692	2	12	12	67	25	80100	100	80000	100	80014	500	1165742	49	23647	0	26707	26727	16655	6	16679	80115	200	80024	200	160048	26727	77	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80038	0	48	0	42	80000	6	0	0	0	0	0	1	1	1	5118	4	16	4	4	26724	14	10	7	80000	100	26728	26728	26936	26740	26796
80204	26730	200	0	0	0	0	0	45	1	0	1	26712	2	1	12	79	25	80100	100	80000	100	80015	500	1166596	49	23647	0	26727	26727	16635	6	16679	80115	200	80024	200	160048	26707	56	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	43	80000	0	1	0	39	80039	6	1	0	43	0	0	1	1	1	5118	4	16	3	4	26724	0	14	7	80000	100	26728	26728	26728	26846	26733

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26727	200	1	1	45	0	0	1	26724	2	12	0	16	25	80010	10	80000	10	80000	50	1168843	1	49	23647	0	26728	26727	16676	3	16688	80010	20	80000	20	160000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80039	0	38	80039	6	0	39	44	5020	8	16	10	10	26801	10	10	4	80000	10	26728	26732	26729	26729	26709
80024	26727	200	0	0	45	1	0	1	26716	2	1	1	0	25	80010	10	80000	10	80000	50	1167124	1	49	23647	0	26728	26708	16672	3	16708	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	38	80039	6	1	0	0	5020	9	16	7	10	26832	10	14	7	80000	10	26728	26728	26728	26732	26729
80024	26728	200	0	0	44	0	0	0	26712	2	1	1	19	25	80010	10	80000	10	80000	50	1168843	1	49	23648	0	26708	26708	16676	3	16707	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80000	0	0	80038	6	1	39	0	5020	10	16	10	10	26734	14	0	4	80000	10	26732	26732	26709	26728	26728
80024	26708	200	0	0	44	0	0	0	26712	2	1	0	19	25	80010	10	80000	10	80000	50	1166750	0	49	23651	0	26708	26708	16672	3	16711	80010	20	80000	20	160000	26731	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80038	0	38	80000	0	1	38	44	5020	7	16	8	10	26805	14	0	7	80000	10	26729	26728	26709	26729	26709
80024	26708	200	0	0	44	1	0	0	26699	2	1	12	19	25	80010	10	80000	10	80178	50	1169254	1	49	23628	0	26727	26727	16672	3	16688	80010	20	80000	20	160000	26708	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80038	0	38	80038	6	1	39	43	5020	10	16	10	7	26734	10	10	4	80000	10	26709	26728	26731	26732	26732
80024	26727	200	1	1	0	1	0	1	26719	3	12	0	0	25	80010	10	80000	10	80000	50	1167201	0	49	23651	0	26727	26708	16672	3	16711	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	44	80039	0	38	80038	6	1	39	43	5020	6	16	7	10	26767	0	0	7	80000	10	26732	26709	26728	26732	26732
80024	26731	200	0	0	45	0	0	1	26693	2	12	12	19	25	80010	10	80000	10	80000	50	1168843	0	49	23647	0	26728	26727	16672	3	16711	80010	20	80000	20	160000	26731	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	44	80038	0	0	80000	6	1	39	43	5020	9	16	7	10	26800	14	10	7	80000	10	26732	26736	26709	26732	26732
80024	26731	200	0	0	44	1	0	1	26693	2	0	1	19	25	80010	10	80000	10	80000	50	1167124	0	49	23647	0	26728	26708	16676	3	16711	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	39	80039	6	1	39	43	5020	9	16	10	8	26798	10	10	4	80000	10	26732	26728	26709	26729	26709
80024	26708	200	0	0	44	1	0	1	26716	0	1	12	19	25	80010	10	80000	10	80000	50	1167201	0	49	23651	0	26708	26708	16676	3	16711	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	43	80039	0	38	80000	6	1	39	44	5020	11	16	10	10	26840	0	0	4	80000	10	26729	26729	26728	26728	26732
80024	26731	200	1	0	45	0	0	0	26722	0	12	1	16	25	80010	10	80000	10	80000	50	1166750	0	49	23651	0	26708	26731	16652	3	16708	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	80039	0	39	80039	0	0	0	44	5020	9	16	11	11	26797	14	14	4	80000	10	26732	26728	26709	26732	26729

LDR (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations