Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CSET (32-bit)

Test 1: uops

Code:

  cset w0, hi
  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369236251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369236251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370
1004369336251000100010005000036936920632251000100010003696611100110001000731181136610001000370370370370370

Test 2: Latency 1->2

Chain cycles: 1

Code:

  cset w0, hi
  tst x0, 1
  mov x0, 1

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020420035150110161199302520200202002021212977330491695520035200351742581748620212202242022420035104112020110099201001000000011113190316222001420100101002003620036200362003620036
2020420035150110161199302520200202002021212977330491695520035200351742571748620212202242022420035104112020110099201001000000011113190216232001420100101002003620036200362003620036
2020420035150110161199302520200202002021212977330491695520035200351742571748620212202242022420035104112020110099201001000000011113190216222001420100101002003620036200362003620036
2020420035150110161199302520200202002021212977330491695520035200351742581748620212202242022420035104112020110099201001000000011113190316222001420123101002003620036200362003620036
2020420035150110161199302520200202002021212977330491695520035200351742581748620212202242022420035104112020110099201001000000011113190216222001420100101002003620036200362003620036
2020420035150110161199302520200202002021212977331491695520035200351742571748520212202242022420035104112020110099201001000000011113190216222001420100101002003620036200362003620036
2020420035150110161199302520200202002021212977330491695520035200351742571748620212202242022420035104112020110099201001000000011113190216322001420100101002003620036200362003620036
2020420035150110161199302520200202002029312977330491695520035200351742571748520212202242022420035104112020110099201001000000011113200316222001420100101002003620036200362003620036
2020420035150110161199302520200202002021212977330491695520035200351742571748520212202242022420035104112020110099201001000000011113200216322001420100101002003620036200362003620036
2020420035150110166199302520200202002021212977330491695520035200351742581748520212202242022420035104112020110099201001000000011113200316222001420100101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515006119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
200242003514906119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
2002420035150020219927252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
20024200351500611991825200202002020020129729704916955200352003517428317504200202002020020200351041120021109200101000008181270127111999520010100102003620036200362003620036
200242003515096119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036
200242003515006119918252002020020200201297297049169552003520035174283175042002020020200202003510411200211092001010000001270127111999520010100102003620036200362003620036

Test 3: throughput

Count: 8

Code:

  cset w0, hi
  cset w1, hi
  cset w2, hi
  cset w3, hi
  cset w4, hi
  cset w5, hi
  cset w6, hi
  cset w7, hi
  mov x0, 0
  cmp x0, x0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8020426740201036258010080100801004797990492365626736267361667231669180100802008020026736661180201100991008010080100005110219112673280000801002673726737267372673726737
8020426736200036258010080100801004797990492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372679026737
802042673620019836258010080100801004797991492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372673726737
80204267362000511258019080100801004797991492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372673726737
8020426736200036258010080100801004797990492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372673726737
8020426736201036258010080100801004797991492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372673726737
8020426736201036258010080100801004797991492062426736267361667231669180100802008020026736661180201100991008010080100005110119112682780000801002673726737267372673726737
8020426736200036258010080100801004797991492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372673726737
8020426736200036258010080100801004797991492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372673726737
8020426736200036258010080100801004797991492365626736267361667231669180100802008020026736661180201100991008010080100005110119112673280000801002673726737267372673726737

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024267242000036258001080010800104720590492362626706267061666531668480010800208002026706661180021109108001080010005020418222670280000800102670726707267072670726707
80024267062000036258001080010800104720591492362626706267061666531668480010800208002026706661180021109108001080010005020218222670280000800102670726707267072670726707
80024267062000036258001080010800104720590492362626706267061666531668480010800208002026706661180021109108001080010005020218222670280000800102670726707267072670726707
80024267062000036258001080010800104720590492362626706267061666531668480010800208002026706661180021109108001080010005020218232670280000800102670726707267072670726707
80024267062000036258001080010800104720591492362626706267061666531668480010800208002026706661180021109108001080010005020218322670280000800102670726707267072670726707
80024267062000036258001080010800104720590492362626706267061666531668480010800208002026706661180022109108001080010005020218222670280000800102670726707267072670726707
80024267062000036258001080010800104720591492362626706267061666531668480010800208002026706661180021109108001080010005020218222670280000800102670726707267072670726707
80024267062000036258001080010800104720591492362626706267061666531668480010800208002026706661180021109108001080010005020218222670280000800102670726707267072670726707
80024267062000036258001080010800104720591492362626706267061666531668480010800208002026706661180021109108001080010035020218332670280000800102670726707267072670726707
80024267062000036258001080010800104720591492362626706267061666531668480010800208002026706661180021109108001080010005020218222670280000800102670726707267072670726707